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Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -1
Arithmetic Circuits
(Part II)
Randy H. KatzUniversity of California,
Berkeley
Fall 2005
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -2
Overview• BCD Circuits
• Combinational Multiplier Circuit
• Design Case Study: 8 Bit Multiplier
• Sequential Multiplier Circuit
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -3
BCD AdditionBCD Number Representation
Decimal digits 0 thru 9 represented as 0000 thru 1001 in binary
Addition:
5 = 0101
3 = 0011
1000 = 8
5 = 0101
8 = 1000
1101 = 13!
Problemwhen digit
sum exceeds 9
Solution: add 6 (0110) if sum exceeds 9!
5 = 0101
8 = 1000
1101
6 = 0110
1 0011 = 1 3 in BCD
9 = 1001
7 = 0111
1 0000 = 16 in binary
6 = 0110
1 0110 = 1 6 in BCD
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -4
BCD AdditionAdder Design
Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)
F A F A F A F A
F A F A
Cin
A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0
Cout S 3 S 2 S 1 S 0
0
CO CI
S
CO CI
S
CO CI
S
CO CI
S
CO CI
S
CO CI
S
1 1XX A1
A2 1X1X
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -5
Combinational MultiplierBasic Concept
multiplicand
multiplier
1101 (13)
1011 (11)
1101
1101
0000
1101
*
10001111 (143)
Partial products
product of 2 4-bit numbersis an 8-bit number
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -6
Combinational MultiplierPartial Product Accumulation
A0
B0
A0 B0
A1
B1
A1 B0
A0 B1
A2
B2
A2 B0
A1 B1
A0 B2
A3
B3
A3 B0
A2 B1
A1 B2
A0 B3
A3 B1
A2 B2
A1 B3
A3 B2
A2 B3A3 B3
S6 S5 S4 S3 S2 S1 S0S7
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -7
Combinational MultiplierPartial Product Accumulation
Note use of parallel carry-outs to form higher order sums
12 Adders, if full adders, this is 6 gates each = 72 gates
16 gates form the partial products
total = 88 gates!
A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3
HA
S 0 S 1
HA
F A
F A
S 3
F A
F A
S 4
HA
F A
S 2
F A
F A
S 5
F A
S 6
HA
S 7
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -8
C
C C C C
C C C C
CC C
Combinational MultiplierAnother Representation of the Circuit
S S S SC
S S S S
S S S S
S S S S
B0
B1
B2
P7 P6 P5 P4 P3 P2 P1 P0
A3 A2 A1 A0
Building block: full adder + and
4 x 4 array of building blocks
F A
X
Y
A B
S CI CO Cin
Sum In
Sum Out
Cout
A3 B0 A2 B0 A1 B0 A0 B0
A3 B1 A2 B1 A1 B1 A0 B1
A3 B2 A2 B2 A1 B2 A0 B2
A3 B3 A2 B3 A1 B3 A0 B3B3
0
0
0
0
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -10
Case Study: 8 x 8 MultiplierProblem Decomposition
How to implement 8 x 8 multiply in terms of 4 x 4 multiplies?A7-4
B7-4
A3-0
B3-0*
A3-0 * B3-0
A7-4 * B3-0
A3-0 * B7-4
A7-4 * B7-4
= PP0
= PP1
= PP2
= PP3
P15-12 P11-8 P7-4 P3-0
8 bit products
P3-0 = PP0
P7-4 = PP0 + PP1 + PP2
P11-8 = PP1 + PP2 + PP3
P15-12 = PP3
3-0
3-0 3-0 3-0
7-4 7-4 3-0
7-4
+ Carry-in
+ Carry-in
+ Carry-in
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -11
Case Study: 8 x 8 MultiplierCalculation of Partial Products
Use 4 4x4 multipliers to create the 4 partial products
4 x 4 Multiplier 74284/285
A7A6
A5A4
B7B6
B5B4
PP37-4
PP33-0
4 x 4 Multiplier 74284/285
A3A2
A1A0
B7B6
B5B4
PP27-4
PP23-0
4 x 4 Multiplier 74284/285
A7A6
A5A4
B3B2
B1B0
PP17-4
PP13-0
4 x 4 Multiplier 74284/285
A3A2
A1A0
B3B2
B1B0
PP07-4
PP03-0
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -12
Case Study: 8 x 8 MultiplierThree-At-A-Time Adder
Clever use of the Carry Inputs
Sum A[3-0], B[3-0], C[3-0]:
Two Level Full Adder Circuit
Note: Carry lookahead schemes also possible!
FA
FA
A0 B0
C0
0
S0
FA
FA
A1 B1
S1
C1FA
FA
A2 B2
C2
S2
FA
A3 B3
S3
C3
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -13
Case Study: 8 x 8 MultiplierThree-At-A-Time Adder with TTL Components
Full Adders(2 per package)
Standard ALU configured as 4-bitcascaded adder
(with internal carry lookahead)
Note the off-set in the outputs
B3 A3 B2 A2 B1 A1 B0 A0
F3 F2 F1 F0
CnGPCn+4
74181
+
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
S0
S1S2S3
A0B0C0A1B1C1A2B2C2A3B3C3
FullAdder
FullAdder
FullAdder
FullAdder
4-bit ALU/Adder
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -14
Case Study: 8 x 8 MultiplierAccumulation of Partial Products
Just a case of cascaded three-at-a-time adders!
B3 A3 B2 A2 B1 A1 B0 A0
F3 F2 F1 F0
CnGPCn+4
74181
+
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
P4
P5
P6
P7
PP04
PP10
PP20
PP05
PP11
PP21
PP06
PP12
PP22
PP07
PP13
PP23
B3 A3 B2 A2 B1 A1 B0 A0
F3 F2 F1 F0
CnGPCn+4
74181
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
Cn B A
Cn+1 S74183
P8
P9
P10
P11
PP14
PP24
PP30
PP15
PP25
PP31
PP16
PP22
PP32
PP17
PP27
PP33
B3 A3 B2 A2 B1 A1 B0 A0
F3 F2 F1 F0
CnGPCn+4
74181
P13
P14
P15
P12
PP34
PP35
PP36
PP37
4-bit ALU/Adder 4-bit ALU/Adder 4-bit ALU/Adder
FA FA FA FA FA FA FA FA
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -15
Case Study: 8 x 8 MultiplierThe Complete System (Actual TTL packages)
Partial Product Calculation 4 x 74284, 74285
8
A7-0
8
B7-0
4
PP37-4
4
PP33-0
4
PP27-4
4
PP23-0
4
PP17-4
4
PP13-0
4
PP07-4
4
PP03-0
P3-0
+
P4
P5P6P7P
8
GPCn+4
Cn
2 x 74183
74181
P9P10P11P
12
GPCn+4
Cn
2 x 74183
74181
P13P14P15
GPCn+4
Cn74181
4 4 4 4 44
0 PP34
PP3PP3PP37 56
Cn+xCn74182
G0P0G1P1G2P2G3P3
Cn+yCn+z
+
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -16
Case Study: 8 x 8 MultiplierPackage Count and Performance
4 74284/74285 pairs = 8 packages4 74183, 3 74181, 1 74182 = 8 packages 16 packages total
Partial product calculation (74284/285) = 40 ns typ, 60 ns max
Intermediate sums (74183) = 9 ns/20ns = 15 ns average, 33 ns max
Second stage sums w/carry lookahead
74LS181: carry G and P = 20 ns typ, 30 ns max
74182: second level carries = 13 ns typ, 22 ns max
74LS181: formations of sums = 15 ns typ, 26 ns max
103 ns typ, 171 ns max
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -17
Sequential Multiplier• 4-Bit Multiplier Example: 3 x 4 = 12
– Four cycles to completion
Cycle Multiplier Multiplicand Product
Initialize 0011 0000 0100 0000 0000
Cycle 0, Multiplier[0]=1 0001 0000 1000 0000 0100
Cycle 1, Multiplier[0]=1 0000 0001 0000 0000 1100
Cycle 2, Multiplier[0]=0 0000 0010 0000 0000 1100
Cycle 3, Multiplier[0]=0 0000 0100 0000 0000 1100
Product = 0For i = 0 to 3 do If Multiplier[0] = 1 then Product = Product + Multiplicand Shift right the Multiplier Shift left the Multiplicand
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -18
Sequential Multiplier
• Datapath and Control Block Diagram– External load signals for Multiplier and Multiplicand– Low order bit of multiplier: if 0, shift; if 1, shift and add
Multiplicand
Multiplier
Product
‘0’
Accumulator
16 16
16
16
Shift
Load3
Control
StartDigit
Digit
Shift Load3
Clock
Clear
Clear
‘0’
8 8
8Load1
Load2
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -19
Sequential Multiplier
• State Diagram– One state for each bit
Start/Clear
Idle
Reset
S0
S1
S2
S3
S4
S5
S6
S7
Digit/Load3,ShiftDigit’/Shift
Start’
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Digit/Load3,ShiftDigit’/Shift
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -20
Sequential Multiplier• Control Timing Behavior
Idle S0
Clk
State
Start
Clear
Load
Shift
S1 S2 S3 S4 S5 S6 S7 Idle
Digit0 Digit1 Digit2 Digit3 Digit4 Digit5 Digit6 Digit7
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -21
Sequential Multiplier• Slightly Revised Block Diagram
– If multiplier low order bit is 0 than assert 0 into accumulator– Else pass multiplicand through to accumulator– Simplifies the control!
Pass or Zero Pass/Zero’
Multiplicand
Multiplier
Product
‘0’
Accumulator
16 16
16
16
Load3-Shift
Digit
Clear
‘0’
8 8
8Load1
Load2
16
Control
Start
Load3-Shift
Clock
Clear
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -22
Sequential Multiplier• Revised State Diagram
– Fewer control outputs!Start/Clear
Idle
Reset
S0
S1
S2
S3
S4
S5
S6
S7
Load3-Shift
Start’
Load3-Shift
Load3-Shift
Load3-Shift
Load3-Shift
Load3-Shift
Load3-Shift
Load3-Shift
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -23
Sequential Multiplier• Symbolic/Encoded State Transition Table
– State assignment chosen as follows:» Idle state set to 0000, i.e., START resets the state FFs» States S0 to S7 set to 1000 to 1111,
easy to implement as a counter
Current State Start Next State Clear Load3-ShiftIdle 0000 0 0000 Idle 0 0Idle 0000 1 1000 S0 1 0S0 1000 - 1001 S1 0 1S1 1001 - 1010 S2 0 1S2 1010 - 1011 S3 0 1S3 1011 - 1100 S4 0 1S4 1100 - 1101 S5 0 1S5 1101 - 1110 S6 0 1S6 1110 - 1111 S7 0 1S7 1111 - 0000 Idle 0 1
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -24
Booth Multiplier
• Tricky encoding scheme to reduce the number of stages in a binary multiplier
• Considers two bits at a time rather than one—this cuts the number of multiplier steps in half
• Each step is slightly more complex compared to the simple multiplier, but is almost as fast as the basic multiplier stage that it replaces
Searching for ways to speed up the basic multiply step
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -25
Alternative Multiply Hardware
• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg)
• Rather than shift multiplier right and multiplicand left, we can shift BOTH the product and the multiplier to the right …
Product (Multiplier)
Multiplicand
32-bit ALU
WriteControl
32 bits
64 bits
Shift Right
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -26
Multiply Control
Multiplicand Product0010 0000 0011
Done
Yes: 32 repetitions
2. Shift the Product register right 1 bit.
No: < 32 repetitions
1. TestProduct0
Product0 = 0Product0 = 1
1a. Add multiplicand to the left half of product & place the result in the left half of Product register
32nd repetition?
Start
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -27
Motivation for Booth’s Algorithm• Example 2 x 6 = 0010 x 0110:
0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier)
+ 0010 add (1 in multiplier) + 0000 shift (0 in multiplier)
00001100• If ALU can subtract as well as add, get same result as
follows: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 +
01000• For example
0010 x 0110 0000 shift (0 in multiplier) – 0010 sub(first 1 in multiplier)
0000 shift (mid string of 1s) + 0010 add (prior step had last 1) 00001100Just add 1111110
(twos complement of 2)
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -28
Booth Multiplier: an Introduction
• Recode each 1 in multiplier as “+2-1”– Converts sequences of 1 to 10…0(-1)– Might reduce the number of 1’s
0 0 1 1 1 1 1 1 0 0
+1 -1+1 -1
+1 -1+1 -1
+1 -1+1 -1
0 1 0 0 0 0 0 -1 0 0
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -29
Recoding (Encoding) Example
• If you use the last row in multiplication, you should get exactly the same result as using the first row (after all, they represent the same number!)
0 1 1 0 1 1 1 0 0 0 1 0
(+1 -1) (+1 -1) (+1 -1) (+1 -1) (+1 -1) (+1 -1)
+1 0 -1 +1 0 0 -1 0 0 +1 -1 0
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -30
0 0 1 1 0 6x 0 1 1 1 0 14
+1 0 0 -1 0 0 0 0 0 0
1 1 0 1 0 (-6) 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 1 0 1 0 1 0 0 84
Booth Multiplication Example
1 1 1
Sign extension
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -31
Booth’s Algorithm: Implementation Approach
Current Bit Bit to the Right ExplanationExample Op1 0 Begins run of 1s 0001111000 sub1 1 Middle of run of 1s 0001111000none0 1 End of run of 1s 0001111000 add0 0 Middle of run of 0s 0001111000none
Originally for Speed (when shift is faster than add, it is advantageous to replace adds and subs with shifts)
Basic idea: replace a string of 1s in multiplier with an initial subtract for rightmost 1 in a run of 1’s, then later add back a 1 for the bit to the left of the last 1 in the run
0 1 1 1 1 0
beginning of runend of runmiddle of run
–1+ 10000
01111
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -32
Booth’s Example (2 x 7)
1a. P = P - m 1110 + 11101110 0111 0
shift P (sign ext)
1b. 0010 1111 0011 1 11 -> nop, shift
2. 0010 1111 1001 1 11 -> nop, shift
3. 0010 1111 1100 1 01 -> add
4a. 0010 + 0010
0001 1100 1 shift
4b. 0010 0000 1110 0 done
Operation Multiplicand Product next?
0. initial value 0010 0000 0111 0 10 -> sub
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -33
Booth’s Example (2 x -3)
1a. P = P - m 1110 +11101110 1101 0 shift P (sign
ext)
1b. 0010 1111 0110 1 01 -> add + 0010
2a. 0001 0110 1 shift P
2b. 0010 0000 1011 0 10 -> sub + 1110
3a. 0010 1110 1011 0 shift
3b. 0010 1111 0101 1 11 -> nop
4a 1111 0101 1 shift
4b. 0010 1111 1010 1 done
Operation Multiplicand Product next?
0. initial value 0010 0000 1101 0 10 -> sub
Contemporary Logic DesignArithmetic Circuits
© R.H. Katz Lecture #24: Arithmetic Circuits -34
Lecture ReviewWe have covered:
• BCD Adders Simple extension of binary adders
• Multipliers 4 x 4 multiplier: partial product accumulation extension to 8 x 8 case
• Sequential Multipliers
• Booth Multiply Step Recoding to speed up the calculation