CONSULTING IN ELECTRONIC DESIGN - Gary Smith€¦ · ATPG 12 ..... Scan Chain Insertion BIST 14 ......

C O N S U L T I N G I N E L E C T R O N I C D E S I G N

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RTL Market Trends 2015Opportunities in RTL

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TABLE OF CONTENTS

Page Title 1 ........... Introduction 2014 RTL and Below Market Overview2 ........... Sub-application Changes in RTL and Below for 2014 Opportunities in RTL4 ........... RTL Design5 ........... RTL Simulation Mixed-language Simulation6 ........... Mixed-signal Simulation7 ........... FormalVerification8 ........... Formal Analysis9 ........... Hardware/SoftwareCo-Verification RTL Synthesis10 ......... DFT11 ......... ATPG 12 ......... Scan Chain Insertion BIST14 ......... Fault Simulation Rapid Prototyping15 ......... Design Analysis Power Analysis 16 ......... Signal-Integrity and Timing Analysis 17 ......... Intellectual Property20 ......... The Gate Level Methodology Analog Simulation21 ......... RF Design & Simulation23 ......... Miscellaneous Enterprise Tools 24 ......... Interoperability Tools25 ......... Design Libraries

TABLE OF FIGURES

Page Title 3 ........... Figure R-1: RTL Revenue by Sub-application 20144 ........... Figure R-2: RTL Design Market Share 2014 Figure R-3: RTL Design Forecast 20155 ........... Figure R-4: Mixed-language Simulation Market Share 20146 ........... Figure R-5: Mixed-language Simulation Forecast 2015 Figure R-6: Mixed-signal Simulation Market Share 2014 7 ........... Figure R-7: Mixed-signal Simulation Forecast 2015 Figure R-8:FormalVerificationMarket Share 20148 ........... Figure R-9:FormalVerification Forecast 2015 Figure R-10: Formal Analysis Market Share 20149 ........... Figure R-11: Formal Analysis Forecast 201510 ......... Figure R-12: RTL Synthesis Market Share 2014 Figure R-13: RTL Synthesis Forecast 2015 11 ......... Figure R-14: ATPG Market Share 2014 Figure R-15: ATPG Forecast 2015 12 ......... Figure R-16: SCAN Chain Insertion Market Share 2014 Figure R-17: SCAN Chain Insertion Forecast 201513 ......... Figure R-18: BIST Market Share 2014 Figure R-19: BIST Forecast 201514 ......... Figure R-20: RTL Rapid Prototyping Market Share 2014 15 ......... Figure R-21: RTL Rapid Rapid Prototyping Forecast 2015 16 ......... Figure R-22: RTL Power Analysis Market Share 2014 Figure R-23: RTL Power Analysis Forecast 2015




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TABLE OF FIGURES (CONTINUED)

Page Title 17 ......... Figure R-24: Timing and Signal-Integrity Market Share 2014 Figure R-25: Timing and Signal-Integrity Forecast 2015 18 ......... Figure R-26: Silicon IP Market Share 2014 Figure R-27: Software IP Market Share 2014 19 ......... Figure R-28: VerificationIPMarket Share 2014 Figure R-29: Silicon IP Market Forecast 2015 Figure R-30: Software IP Market Forecast 2015 20 ......... Figure R-31:VerificationIPMarket Forecast 2015 21 ......... Figure R-32: Analog Simulation Market Share 2014 Figure R-33: Analog Simulation Forecast 2015 22 ........ Figure R-34: RF Design & Simulation Market Share 2014 Figure R-35: RF Design & Simulation Forecast 201524 ......... Figure R-36: Enterprise Tools Market Share 2014 Figure R-37: Enterprise Tools Forecast 201525 ......... Figure R-38: Interoperability Tools Market Share 2014 Figure R-39: Interoperability Tools Forecast 201526 ......... Figure R-40: Design Libraries Market Share 2014 Figure R-41: Design Libraries Forecast 2015 27 ......... Appendix A: RTL Sub-application Forecast 2015





INTRODUCTIONThis report comprises the “RTL and Below” section of the EDA 2015 Market Trends. “RTL and Below”

includes RTL (register transfer logic), gate level and transistor level design tools. These tools, along

with ESL (electronic system level) tools, make up the CAE market for EDA tools. In this report we will

discuss market share, trends, and forecasts for the “RTL and Below” sub-applications that have the

most impact on the overall EDA landscape.

2014 RTL AND BELOW MARKET OVERVIEW

CAE is comprised of 4 categories – ESL, RTL, gate level tools, and miscellaneous tools (e.g.,

interoperability tools and design libraries). We consider “RTL and Below” to include RTL tools, gate

level tools, and miscellaneous tools (e.g., libraries, and interoperability tools). Readers should note

that we classify design tools at their highest level of use. A prime example would be gate level

simulators used as RTL simulators. Verilog simulators are used for gate level simulation, but revenue

for those tools is listed under the appropriate RTL sub-application instead of the gate level sub-

applications.

The “RTL and Below” market turned in decent growth in 2014, growing slightly under 8 percent to

reach$3,976millionin2014.Readersshouldnotethatthisfigureismuchgreaterthanwhatwehave

reported in previous years. We have now added a new sub-application in RTL – intellectual property

(IP). We will discuss our coverage of IP in more depth later in this report. RTL is still the largest of

the RTL and Below categories, growing slightly under 9 percent in 2014 to reach $3,202 million. Gate

level tools grew 6 percent to reach $549 million, and miscellaneous tools grew 4 percent to reach

$225 million in 2014.

Overthepastfiveyears,theRTLandBelowmarkethasbeencontinuallygrowing,thoughalways in

the single digits. It is clear from our numbers that users have continued to put steady investment

intoRTLandgate-leveltoolsforthepastfiveyears,butnomorethanthat.

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MARY A. [email protected]


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We are expecting the RTL market to show a compound annual growth rate (CAGR) of 8 percent

overthenextfiveyears,from2014to2019.ThisgrowthrateisjustundertheoverallCAEmarket’s

projectedCAGRof9percentfrom2014-2019,withmuchofthatgrowthbeingdrivenbytherapidly

growing ESL market. The gate level market is expected to post a 6 percent CAGR from 2014-2019.

Appendix A gives our complete RTL and Below forecast by sub-application for 2014-2019.

SUB-APPLICATION CHANGES IN RTL AND BELOW FOR 2014

Other than adding coverage for IP, there were no other changes to the sub-application structure

in RTL and Below for 2014.

We will note that in 2012 we moved the Acceleration and Emulation sub-application from RTL up to

the ES level. This is because we report sub-applications at their highest level of use, and it was clear

in 2012 that Acceleration and Emulation was being used at the ES level. In 2012, we also moved

revenue from theFunctionalVerificationsub-application intoMixed-languageSimulation toavoid

double counting revenue in both places. Lastly, we moved gate level schematic capture to PCB in

2012, as these tools are mainly being used there rather than in gate level simulation.

OPPORTUNITIES IN RTL

As is typical of most years, in 2015, some RTL sub-applications fared well while others languished.

Bothmixed-signalsimulationandRTLformalverificationgrewindoubledigits,whileDFT,

synthesis, and design analysis had lackluster years.

What’scausingallofthisvariationinsub-applicationgrowth?TheRTLmarketisfacingpressure

all around. As always, users are facing increasing time-to-market pressures but are reluctant to

invest heavily in new tools and software. Meanwhile, design size and complexity are increasing.

Further,thetransitiontoESLhangsovertheRTLmarket,whereweareinyearfiveofasix-year

(or longer) transition. The upper mainstream users have started moving up into ES level design,

contributingtotheESlevel’sbottomlinewhiletakingawayfromtheRTLmarket.Ontheother

hand, lower mainstream will eventually make the move to ESL, but not in the near future.

And FPGA designers will continue to put money into key RTL sub-applications (e.g., hardware/

softwareco-verificationandsynthesis),thusensuringsteadygrowthintheRTLmarketforthe

nextfiveyears.



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One key bright spot in the future RTL market is in IP. Incorporating commercial IP cores into larger

designs has now become a common practice for design teams as they continue to search for ways

to speed up the design cycle while building ever-larger ICs. Not having to design every piece of the

circuitryfromscratchandinsteadusesomeoff-the-shelfIPforspecificportionsofthechipisa

hugebenefitfornewdesigns.TheprevalenceofcommercialIPinnewdesignshasreallyexploded

inrecentyearsandwillcontinuetobeamajorfactorinthedesignlandscape.

AnothersignificantfactorfortheRTLmarketisthesiliconvirtualprototype(SVP).SVPincludes

tools from the following sub-applications:

• RTL Design & Entry

• Formal Analysis

•FormalVerification

• Rapid Prototyping

• RTL Design and Debug

These tools are all targeted at RTL sign-off, with the goal of making sign-off easier and faster.

BecauseSVPwon’ttakeoffattheESlevelforthenextfewyears,anyneartermgrowthin

thisareawilladdtotheRTLmarket’sbottomline.WithSVP,vendorsareaddressingtraditional

bottlenecks in the design process and revamping tools to target the mainstream user rather than

the specialist. All of this points to continued growth opportunities in RTL.

In the remainder of this report, we look more closely at where the pockets of opportunity are in

RTL and where the market may be slowing down. Figure R-1 shows how RTL breaks down by

sub-application for 2014.

Figure R-1: RTL Revenue by Sub-application 2014

(Source: Gary Smith EDA, December 2015)

Design for Test6%

RTL Design4%

Formal Verification3%

Rapid Prototyping2%

Formal Analysis2%

Design Analysis6%

Synthesis9%

RTL Simulation20%

IP48%



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RTL Design

RTL design is one sub-application that continues to turn out modest growth year after year. It grew

about 4 percent in 2014 to reach $141 million. Figure R-2 shows market share for RTL design, where

Synopsys commands a sizeable chunk of this market through its acquisition of SpringSoft in 2012.

RTL design has slowed down in growth for the past few years; consequently, we are lowering our

five-yearCAGRtoslightlybelow6percent,wellundertheprojectedoverallRTLmarketgrowth(see

Figure R-3). As we get ready to move to an RTL golden netlist, we should see growth in RTL sign-off

tools,whichwillpositivelyimpactRTLdesign’sbottomline.

Figure R-2: RTL Design Market Share 2014


Mentor Graphics8%

Verific Design Automation

3%

Veritools7%

ARM 8%

Atrenta14%

Cadence Design Systems

19%

Synopsys41%


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134.8 140.7

148.6 158.3

167.1 172.1 183.6

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Figure R-3: RTL Design Forecast 2015



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RTL SimulationRTL simulation includes Verilog, VHDL, mixed-language simulation and mixed-signal simulation. Mixed-language simulation has pretty much replaced Verilog and VHDL, so we will only discuss mixed-language simulation and mixed-signal simulation in this report. However, we will add that we are predicting strong growth for Verilog over our forecast period, largely driven by FPGA designers, who continue to use standalone simulators. Fintronic is still the leading Verilog vendor with 61

percent market share, and Aldec is the only player in the VHDL market.

Mixed-language SimulationMixed-language simulation is traditionally the largest RTL sub-application. In 2014, it accounted for 20 percent of all of RTL revenue in 2014. Mixed-language simulation is essentially the territory of the big 3 vendors (Synopsys, Mentor and Cadence). Mixed-language simulation grew 5 percent in 2014 to reach $476 million (see Figure R-4).

Because of price pressure and the movement of mixed-language simulation revenue into the ESL market,weareforecastingjustunder6percentfive-yearCAGRinthemixed-languagesimulationmarketoverthenextfiveyears(seeFigure R-5). Any growth will come from the fact that simulation and emulation tools are aligning more closely, making these tools more attractive to users. At two of the three leading vendors in this sub-application, these tools are being bundled together from an application perspective and/or sales perspective, giving these vendors an advantage

over the competition.

Mixed-signal Simulation

Figure R-4: Mixed-language Simulation Market Share 2014


Mentor Graphics23%

Aldec1%


35%

Synopsys41%



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As illustrated in Figure R-6, Mentor commanded a 50 percent share of the mixed-signal simulation

marketin2014,andSynopsysheld20percent.Cadence’ssharegrewto21percentin2014,

capturing more share from both Mentor and Synopsys. Figure R-7 shows the long-term forecast for

mixed-signal simulation, with a 10 percent CAGR through 2019. Mentor offers the

Model SIM for FPGAs.

Formal Verification


454.3 475.5 498.4 533.3 565.2 585.2 624.2

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Figure R-6: Mixed-signal Simulation Market Share 2014



21%Synopsys

29%

Mentor Graphics50%



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Formalverificationgrew10percentin2014toreach$111million.Cadence,whoacquiredJasperin2014, and Synopsys, leave little room for any other players (see Figure R-8). Both vendors posted good growth, with neither one gaining an edge over the other in 2014.

WeexpectformalverificationtobeoneofthefastergrowingRTLsub-applicationsandamaindriverof the silicon virtual prototype, outperforming the overall RTL market (see Figure R-9). We have uppedourforecasttojustover18percentCAGRfrom2014to2019.Thesamefactorswecitedlastyearwillcontributetothisgrowth.Formalverificationhasbecomeamust-havetechnology,andisanimportantpieceofthesiliconvirtualprototype.Also,thesizeofthefunctionsthattoday’sformalverificationtoolscanhandlestillpreventsthetechnologyfrommovinguptotheESLmethodology.Finally,andperhapsmostimportantly,formalverificationtoolsnowhavemorewidespreadappeal,with less reliance on specialists to use the tool. Formal verification vendors are simplifying the

process, setting properties for the engineer upfront.

Formal Analysis

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74.5

100.1 115.4

132.0 141.1

148.9 161.0

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Figure R-7: Mixed-Signal Simulation Forecast 2015

Figure R-8: Formal Verification Market Share 2014


OneSpin Solutions

4%

Synopsys42%


54%



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Formal analysisdroppednearly2percent in2014 to$52million, following last year’s7percent

growthand2012’sdouble-digitgrowth.Mentorcontinuestoholdontoitsleadinthismarket,though

the competition continues to chip away at its market lead (see Figure R-10).

Weareexpectingaboutan8percentfive-yearCAGRoverourforecastperiodforformalanalysis,

onparwiththeoverallRTLmarketbutmuchlowerthanformalverification.Ourforecastreflectsa

number of things. On one hand, engineers are turning to formal analysis tools for use in

assertion-basedverification,whichhasapositiveeffectonourforecast.Ontheotherhand,formal

analysis tools are being bundled with RTL simulation at the point of sale, tempering our forecast.

Further,Synopsys’acquisitionofAtrentain2015willmeanalittlebitofturmoilforthissub-application

overthenearterm,untilthingssettleout.Ourfive-yearforecastforformalanalysisisshown

in Figure R-11.

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100.1 110.5 132.3

163.9 196.7

221.6 258.1

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Figure R-9: Formal Verification Forecast 2015

Figure R-10: Formal Analysis Market Share 2014


Real Intent16%

Averant14%

OneSpin Solutions

3%


18%Atrenta20%

Mentor Graphics29%



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Hardware/Software Co-VerificationHardware/softwareco-verificationdropped28percentin2014to$9million.Thissub-applicationisnowthe domain of Carbon Design (acquired by ARM in 2015). We predict that this sub-application will be in

astateoffluxforthenextfewyears;hence,wehaveloweredourfive-yearCAGRto6percent.

RTL SynthesisRTL synthesis, which has not posted double-digit growth for a number of years, grew only 3 percent in 2014 to reach with $291 million in revenue. Figure R-12 shows market share for RTL synthesis, which consists of both logic synthesis and FPGA synthesis. Synopsys continues to hold a commanding market lead over all the other players, with 83 percent market share, and it is the only vendor with offerings in both FPGA and logic synthesis.

For the most part, synthesizers are a utility in the RTL methodology, and the differences between theleadingtoolsaresmall.Userseitherfindthemselvesstickingwithwhattheyhave,oriftheydoupgrade, price pressures are keeping revenues down in this sub-application.

We are predicting a 6 percent CAGR from 2014 to 2019, below the overall RTL market growth rate over that same time period (see Figure R-13). Short-term growth will come from FPGA designers needing synthesis tools. Long-term growth will come from tools that are not necessarily concentrating on optimization, but instead on speed and capacity, where the synthesizer can take in much of the design at once instead of chopping it up into smaller blocks. Given the increasing size of designs,

anything that can be done to speed up synthesis will be looked on favorably by the market.

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53.2 52.3 52.9 54.5 60.0

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Figure R-11: Formal Analysis Forecast 2015



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282.7 291.3 303.0 321.7 331.3 357.6

392.5

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Figure R-13: RTL Synthesis Forecast 2015


Figure R-12: RTL Synthesis Market Share 2014



15%

Mentor Graphics2%

Synopsys83%

DFT

Thedesignfortest(DFT)marketwasfairlysluggishin2014,growingjust2.7percent.Thesubstantial

growth in the DFT market during the prior year (nearly 16 percent in 2013) likely contributed to

depressed growth in 2014 by pulling in some planned investment in test tools.

DFT is a vital component of the design process and growth in the coming years should be somewhat higher as spending patterns rebalance. Integrated device testing is key to achieving successful production yields, as is developing thorough, comprehensive testing strategies for ICs and systems. Design complexity dictates that testing be woven into the design planning process from the get-go, not merely tacked on after the design is complete. The increasing use of commercial IP also contributes to the need for well-crafted test strategies that tie IP testing into overall system testing.



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ATPGAutomatic test pattern generation (ATPG) was again the most robust of the DFT market segments in 2014, though growth was still only 3 percent, with Mentor Graphics maintaining its market leadership position of 46 percent market share (see Figure R-14).

The ATPG market is by far the largest of the DFT market segments, accounting for more than 70 percent ofDFTtoolspending.Itisforecasttohavethehighestfive-yearCAGRofanyoftheDFTsegments,at

6.7 percent (see Figure R-15). Test compression technology remains a key driver of the ATPG market.

Figure R-14: ATPG Market Share 2014



13%

Atrenta3%

Mentor Graphics46%

Synopsys36%

SynTest Technologies

2%


121.7 125.4 134.5

148.0 158.6 161.9

173.1

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Figure R-15: ATPG Forecast 2015

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Scan Chain InsertionScan chain insertion has languished as a market segment for quite a few years. Though it remains a necessary component of DFT that enables a variety of test strategies, scan chain insertion has not beenagrowthareaforDFT.Synopsyscontinuestoholdthelion’sshareofthemarket(seeFigure R-16). Market growth in 2014 was merely 1.5 percent and is forecast to achieve a 1.7 percent five-yearCAGR(seeFigure R-17). Consolidation with other EDA tools is still a strong possibility

for this market segment in the long term.

Figure R-16: SCAN Market Share 2014


Mentor Graphics18%


3%Synopsys

79%


26.6 27.0

27.5

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28.8

29.4

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30.0

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Figure R-17: SCAN Forecast 2015

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BISTBuilt-in self-test (BIST) has long held considerable promise for its potential impact on design. Embedding testability into the innermost circuitry of a design offers enormous access to internal features and greater insight into problems during the testing phase. BIST has become the industry standard method for designing-in testability. Mentor Graphics continues to maintain its dominance in

this market segment (see Figure R-18).



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Despite the importance of BIST, the market has not exhibited the explosive growth that seemed

inevitablewhenitfirstcameonthescene.Onereasonfortherelativemutedgrowthisthatitoften

possible for design engineers to create custom BIST functionality for their designs without the help

of commercial BIST tools. Proprietary BIST technology is alive and well. Another, even more crucial

problem, is that off-the-shelf BIST technology for analog and mixed-signal circuitry remains elusive.

Though this is still an active research area in academia, it has never successfully made its way

into commercial development. With analog and mixed-signal designs on the rise, commercial BIST

solutions would seem ripe for adoption. Expansion of the commercial IP market and advances in IC

and board packaging technology also hold the potential for escalating the need for creative BIST

solutions,thoughit’sunlikelythattheBISTbusinesswillseemuchimmediatebenefitfromthese

trends.Thefive-yearCAGRforBISTis2.0percent(seeFigure R-19).

Figure R-18: BIST Market Share 2014


Atrenta9%


6%Mentor Graphics

85%

22.2

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Figure R-19: BIST Forecast 2015




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Fault Simulation

Fault simulation is declining as an independent tool category; it is mostly a function contained in

othertypesofDFTtoolsatthispoint.NomajorEDAvendorsofferpure-playfaultsimulationtools

anymore and we expect this segment to become fully integrated into other DFT tools eventually.

Thismarketsegmentisprojectedtobestagnantovertheforecastperiod.

Rapid Prototyping

Rapid prototyping boxes are basically boards with FPGAs on them. Rapid prototyping is a low margin,

bare bones, quick approach to emulation. This sub-application grew 11 percent in 2014 to reach $59

million. Synopsys continues to pretty much owns this sub-application, with 84 percent market share

in 2014 (see Figure R-20).

Weare forecastinga7percentfive-yearCAGR for rapidprototyping (seeFigure R-21). In order

todoanysoftwareverification,designersneedanemulationbox,andformanydesigners,rapid

prototypingfits thebill. It is still the fastestapproach toemulation.However,we thinksomeof

those engineers who would normally be proponents of rapid prototyping will migrate up to more

sophisticatedlevelsofemulation,especiallyifweseemoreoverlapamongsimulation,verification,

and emulation tools. We expect rapid prototyping will continue to grow, but it will not make large

gainsnorundergoanymajorchanges.

Figure R-20: RTL Rapid Prototyping Market Share 2014


The Dini Group13%


3%

Synopsys84%



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Design Analysis

Design analysis consists of power, signal integrity, timing, and electromagnetic integration (EMI)

tools. Once again, revenue growth of these tools is barely keeping up with the overall RTL market.

The market size of all design analysis tools reached $194 million in 2014, growing only 7 percent

over2013.Weareloweringourfive-yearforecastfordesignanalysistools.Wearestillwaitingfor

design analysis tools to be a top performer in RTL, and we do not see that happening over the next

fiveyears.Eventhoughdesignsizecontinuestoincreaseandfootprintscontinuetodecrease--all

necessitatingtheneedforanalysistools–usersjustaren’tmakingthatjumpinbignumbers.Inthe

following sections, we look more closely at power and signal integrity/timing.

Power AnalysisPower analysis grew just under 8 percent in 2014 to reach $59 million. While Synopsys still has acommanding lead in this sub-application, Mentor Graphics is gaining a stronger foothold (see Figure R-22).

Power is the number one consideration for designers, as electronic devices become even more complex. Inpreviousyears,wewereseeingdesignspecificationsthatsetapowergoalandthenchallengedthedesign team to reach the highest speed possible within that power envelope. However, the methods usedinRTLtogetpowerconsumptiondownaren’tworkingwithtoday’sdesigns,sopoweranalysistoolswillbeoneofthefirstdesignanalysistoolstomoveuptotheESlevel.Weareforecasting7percentCAGR from 2014 to 2019, with movement to the ES level hampering our forecast (see Figure R-23).


52.8 58.6

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Figure R-21: RTL Rapid Prototyping Forecast 2015



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Signal-Integrity and Timing Analysis

We report signal integrity and timing together, largely because some tools can be categorized in

signal integrity and/or timing, making it virtually impossible to split that revenue. Market share

for the combined signal integrity and timing sub-application is shown in Figure R-24, where the

combinedsub-applicationgrewjustover6percentin2014toreach$125million.Synopsysstillhas

asignificantleadonthecompetition,butAtrentaandCLKDesignAutomationaregainingground.

Thoughpowertakescenterstage,designerscan’tignoresignalintegrityandtiming.Previously,

price wars had held down revenue growth and Synopsys had bought up most of the competition.

Eventhoughwedon’tseesignalintegrityandtiminganalysistoolsmovinguptotheESlevelinthe

near future, we are expecting only modest growth in this sub-application, and we have forecasted

only 6 percent CAGR from 2014 to 2019 (see Figure R-25).Usersdon’tfeelcompelledtoinvest

heavily in the existing signal integrity and timing analysis tools.

Figure R-22: RTL Power Analysis Market Share 2014


Atrenta18%

Mentor Graphics10%

Synopsys52%

ANSYS20%

54.9 59.1

65.2 70.4

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Figure R-23: RTL Power Analysis Forecast 2015



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Intellectual Property

Forthefirsttime,wehaveaddedintellectualproperty(IP)asanewcategorytoourEDAmarket

coverage. Though commercial IP is certainly not novel to the semiconductor design world, it has

become more closely tied to EDA. Utilizing vendor-supplied IP in a larger design is hardly unusual

these days and EDA vendors have gotten in on this opportunity, as well.

TheIPmarkethasthreecomponents—siliconIP(SIP),softwareIPandverificationIP.SIPis,byfar,

the segment with the bulk of the revenue. This is the segment most often thought of at the mention

of semiconductor IP. ARM dominates this segment, capturing 77 percent of SIP market share (see

Figure R-26). SIP is the segment also inhabited by other traditional semiconductor IP providers

licensing processor cores, including Imagination Technologies and CEVA. While EDA vendors presently

Figure R-24: Timing and Signal Integrity Market Share 2014


ANSYS15%


7%Atrenta

4%Synopsys

70%CLK Design Automation

4%

117.6 124.9

134.5 144.2

152.1 155.9 170.2

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Figure R-25: Timing and Signal Integrity Forecast 2015




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hold only a small position in SIP, we expect their role in this segment to expand in the future and IP

and EDA continue to become more intertwined.

Ontheotherhand,softwareIPandverificationIParepredominantlythedomainoftheEDAvendors

at this time. Synopsys and Mentor Graphics operate in both segments, while Cadence has staked a

positioninonlyverificationIPsofar.MentorhasasizableshareofthesoftwareIPmarket(see

Figure R-27),whileSynopsysandCadencedominate theverification IPmarket (seeFigure R-28).

Mentor’sleadershipinsoftwareIPiswellalignedwithitssubstantialembeddedsoftwaretoolsbusiness

and strategic recognition of the dependence of hardware and software integration in successful

system design.

All three IP segments are anticipated to exhibit robust growth in the coming years. The opportunities in

IP are enormous, since the industry pressures of constantly increasing design sizes coupled with short

time-to-market windows demand the use of design reuse and IP to produce successful semiconductor

products.Thefive-yearCAGRfortheSIPmarketis9percent,whiletheCAGRforsoftwareIPisnearly

17percentandverificationIPisjustover13percent(seeFigures R-29 through R-31). The IP market

is among the highest growth segments forecast for the entire EDA industry.

Figure R-26: Silicon IP Market Share 2014


Imagination Technologies

19%

Ceva4%

ARM 77%

Figure R-27: Software IP Market Share 2014


Synopsys26%

Mentor Graphics74%



19

6.2 9.0

12.5

15.8 16.7 17.6 19.4

0.0

5.0

10.0

15.0

20.0

25.0

2013 2014 2015 2016 2017 2018 2019

(In M

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f Dol

lars

)

Figure R-30: Software IP Market Forecast 2015


Figure R-28: Verification IP Market Share 2014



39%

Synopsys51% Mentor Graphics

10%

1,316.9 1,463.5

1,698.8

1,999.3 2,111.4 2,073.2

2,274.8

0.0

500.0

1,000.0

1,500.0

2,000.0

2,500.0

2013 2014 2015 2016 2017 2018 2019

(In M

illion

s of

Dol

lars

)


Figure R-29: Silicon IP Market Forecast 2015



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THE GATE LEVEL METHODOLOGY

The Gate Level Methodology consists of gate level analog simulation, analog design, and RF design and

simulation. In this section we take a closer look at analog simulation and RF design and simulation.

Analog Simulation

Traditionally, the analog simulation segment of gate level methodology is based on a usage model.

Analog simulators are all based on the SPICE simulator, but they have been optimized for analog

designers.SynopsysandCadencecapturethelion’sshareofthismarketsegment(seeFigure R-32).

ManycompaniesintegratewithSynopsys’andCadence’sanalogdesigntools.CadenceVirtuosoisan

analog design environment tool. This market grew to $196 million in 2014 and is expected to grow

to $277 million by 2019 (see Figure R-33).

Synopsys’FineSIMproductsallowdesigners to functionallyverifymixed-signalSoCsseamlessly

without the overhead of traditional solutions. In addition to enabling the designer to work with

detailed parasitic information, the designer has complete control of accuracy versus performance

tradeoffs.FineSIMwithmulticoreprocessingsignificantlyreducessimulationruntime.

With an improved architecture and better numerical solvers, Synopsys states that FineSim delivers

a 3X to 10X performance increase on a single core over existing commercial SPICE and FastSPICE

simulators. FineSim allows the designer to take advantage of multiple circuit solving techniques, such

as hierarchical simulation recognition for memory structures, or multi-rate techniques for sensitive

analog circuits and advanced RC reduction algorithms.

51.7 59.2

70.4 82.6

90.3 95.4

111.7

0.0

20.0

40.0

60.0

80.0

100.0

120.0

2013 2014 2015 2016 2017 2018 2019

Figure R-31: Verification IP Market Forecast 2015

(In M

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)




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When multiple cores are used, the simulation performance can exceed 30X performance compared

to other commercially available products that use a single core while enabling the handling of very

large designs.

According to Synopsys, FineSim enables SPICE-accurate analysis of very large, complex digital and

analog/mixed-signal designs using multiple cores, achieving silicon accuracy never before possible in

SPICE. Using multiple cores, FineSim has accurately simulated designs with multi-million transistors

in full SPICE and matched measurements taken from silicon.

Figure R-32: Analog Simulation Market Share 2014


ANSYS9%

Synopsys47%


39%National

Instruments5%

186.8 197.0 215.6

237.5 251.2 260.3

277.3

0.0

50.0

100.0

150.0

200.0

250.0

300.0

2013 2014 2015 2016 2017 2018 2019

Figure R-33: Analog Simulation Forecast 2015

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)


RF Design and Simulation

Keysight EEsof TechnologiesGoldenGate simulation, analysis and verification software solution for

large-scale RFIC circuit design offers new and enhanced capabilities designed to improve productivity



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231.0 243.5 248.9 261.4 279.7

305.1 323.4

0.0

50.0

100.0

150.0

200.0

250.0

300.0

350.0

2013 2014 2015 2016 2017 2018 2019

(In M

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Figure R-35: RF Design and Simulation Forecast 2015


Figure R-34: RF Design and Simulation Market Share 2014


ANSYS13%

Synopsys1%

Keysight EEsof68%

National Instruments

10%Cadence Design

Systems8%

andefficiencyforsiliconRFICdesigners.KeysightEEsofcontrolsnearly70percentoftheRFandESL

RF market (see Figure R-34).

CompaniescompetingwithKeysightTechnologiesincludeNationalInstruments,Ansys,Cadence,and

Synopsys.SeveralIPstart-upslikeAtaiTecwilljointhemarketinthenextfewyearstomeetgrowing

demands for RF IP and design solutions in Apple, Cisco, Intel, Qualcomm, Samsung and Skyworks

next generation systems.

Ourfive-yearforecastforRFDesignandSimulationisshowninFigure R-35.



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MISCELLANEOUS

As its name indicates, the miscellaneous tools market is a mixed bag of more general-purpose tools

usedspecificallybyengineeringteamsbutwithoutadirectdesignfunction.Withtheexceptionof

design libraries, the miscellaneous tools serve to streamline and simplify the design process, making

theworkfloweasierorcreatingsmoother interactionsamongteammembersandtheirrespective

design environments. The miscellaneous tool segments have, not surprisingly, historically been lower

priority investments for engineering teams, who tend to focus their limited budgets on investing in

the more bleeding-edge, mission-critical design tools. Growth in the miscellaneous EDA segments

often lags that of the market as a whole, since they are not perceived as mandatory to the design

process.However,withsystemdesignbeingoneofthenextmajorfrontiersfordesignteams,the

need to rely on more of these types of process improvement tools will increase. We expect to see

greater investment put towards some of the miscellaneous tools in the coming years.

Enterprise ToolsEnterprise tools are engineering data and network management software, including component information systems (CIS). Such tools facilitate information flow and collaborationwithin designteams.Mechanicaldesignersjumpedonthebandwagonlongagoforproductlifecyclemanagement(PLM) in their industries; yet similar tools for electronics engineeringprojects have takenmuchlonger to gain broad adoption.

Enterprise tools have typically been used more in the PCB design world that in IC design, though semiconductor design teams are becoming more familiar with using tools such as those from IC Manage. Expanding use of commercial—or even home-grown—IP has helped make enterprise tools morepopular,asdesigningforreuseandsimplyintegratingwithsuppliers’IPcorescanbenefitfromutilizing data management tools. Nearly all vendors in this fairly fragmented segment had greater than 9.0 percent revenue growth in 2014 (see Figure R-36).

Enterprisetoolsareforecasttoseea5.1percentfive-yearCAGR(seeFigure R-37). We believe that the time is on the horizon when enterprise tools become less of a purely discretionary investment andareseenasessentialcomponentsofacompletedesigntoolflow.Processanddatamanagementtools have had enormous impact in other engineering environments, particularly mechanical design, andtherecanbesimilarlysignificantadvantagestoelectronicdesignteamsthatadopttherightenterprise tools and accompanying best-in-class design practices.



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Interoperability Tools

Many of the most popular EDA interoperability tools are actually freeware applications for

distributed computing and software management. Of the remaining commercial applications,

Platform Computing has long maintained the leading market share spot (see Figure R-38).

The interoperability tools segment grew 3.6 percent in 2014 and is forecast to see a 5.5 percent

five-yearCAGR(seeFigure R-39). Competing in a market with numerous open source applications

can be tough for commercial vendors, but the high reliability and stability required by EDA users

of their software helps give conventional vendors a key advantage from the support they offer.

Figure R-36: Enterprise Tools Market Share 2014


Dassault Systemes (MatrixOne)

15%

ClioSoft9%

IC Manage17%

Zuken37%

Parametric Technology

12%

Oridus10%

82.0 86.2 84.7 84.7 95.7

105.3 110.6

0.0

20.0

40.0

60.0

80.0

100.0

120.0

2013 2014 2015 2016 2017 2018 2019

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Figure R-37: Enterprise Tools Forecast 2015




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Figure R-38: Interoperability Tools Market Share 2014


Synopsys17%

ATA Engineering

5%

IBM Platform Computing

66%

Sybase6%


6%

92.4 95.7 98.9 103.5 111.7

118.7 125.1

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

2013 2014 2015 2016 2017 2018 2019

Figure R-39: Interoperability Tools Forecast 2015

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)


Design Libraries

Design libraries supply basic IP building blocks to integrate protocols for datapaths, controllers,

verification,memory,test,andnetworks.Growthinthedesignlibrariesmarketwasquitemodest

in 2014 at 3.7 percent. Only two companies have notable presence in this segment—Synopsys and

KeysightEEsof(seeFigure R-40). Synopsys offers a broader suite of design libraries spanning a

widevarietyoffunctionalities,whileKeysightEEsofoffersdesignlibrariesmorealignedwithits

core business in the analog and mixed-signal arena.

Bundling of design libraries with other EDA tools has caused this segment to lose some stature as

a standalone market. However, the need for design libraries will not disappear; the exact mix of

functionalitycontainedinthoselibrariesmustcontinuallyadjusttoaccommodateusers’current



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designneeds.Designlibrarieswillremainafundamentalpartofthedesignflow,followingthe

trendofdesignteams’increasingrelianceonIPthroughouttheirdesigns.Thefive-yearCAGRfor

design libraries is 6.0 percent (see Figure R-41).

Figure R-40: Design Libraries Market Share 2014


Keysight EEsof13%

Synopsys87%

40.7 42.2 44.3 48.1

52.7 53.9 56.6

0.0

10.0

20.0

30.0

40.0

50.0

60.0

2013 2014 2015 2016 2017 2018 2019

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Figure R-41: Design Libraries Forecast 2015




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Appendix A: RTL Sub-application Forecast 2015Meth Application Sub-Application 2013 2014 2015 2016 2017 2018 2019 CAGR

RTL 2,951.3 3,202.2 3,570.8 4,044.8 4,296.4 4,372.7 4,784.8 8.4%

RTL Design 134.8 140.7 148.6 158.3 167.1 172.1 183.6 5.5%

RTL Simulation 586.5 637.3 680.3 741.0 787.4 819.2 880.2 6.7%

Mixed-Language Simulation 454.3 475.5 498.4 533.3 565.2 585.2 624.2 5.6%

Verilog 49.2 52.0 56.0 63.9 68.5 72.3 80.9 9.2%

VHDL 8.5 9.7 10.5 11.8 12.6 12.8 14.1 7.8%

Mixed-Signal Simulation 74.5 100.1 115.4 132.0 141.1 148.9 161.0 10.0%

Formal Verification 100.1 110.5 132.3 163.9 196.7 221.6 258.1 18.5%

Formal Analysis 53.2 52.3 52.9 54.5 60.0 69.0 75.9 7.7%

Synthesis 282.7 291.3 303.0 321.7 331.3 357.6 392.5 6.1%

Logic Synthesis 230.4 238.2 247.6 261.4 268.8 292.5 321.7 6.2%

FPGA Synthesis 52.3 53.1 55.4 60.3 62.5 65.1 70.8 5.9%

DFT 172.6 177.3 187.5 202.3 213.4 216.8 229.8 5.3%

ATPG 121.7 125.4 134.5 148.0 158.6 161.9 173.1 6.7%

SCAN 26.6 27.0 27.5 28.1 28.5 28.8 29.4 1.7%

BIST 22.2 22.7 23.3 24.0 24.2 24.0 25.1 2.0%

Fault Simulation 2.1 2.2 2.2 2.2 2.1 2.1 2.2 0.0%

Rapid Prototyping 52.8 58.6 64.8 69.5 72.7 75.2 82.4 7.1%

HW/SW Co-Verification 12.0 8.7 9.5 10.1 10.5.7 10.9 11.7 6.1%

Design Analysis 181.8 193.8 210.1 225.9 238.9 244.2 264.7 6.4%

Timing & Signal-Integrity 117.6 124.9 134.5 144.2 152.1 155.9 170.2 6.4%

Power Design 54.9 59.1 65.2 70.4 74.9 76.3 81.6 6.7%

EMI Design 9.3 9.8 10.4 11.3 11.9 12.0 12.9 5.7%

IP 1,374.8 1,531.7 1,781.7 2,097.7 2,218.4 2,186.2 2,405.9 9.5%

Silicon IP 1,316.9 1,463.5 1,698.8 1,999.3 2,111.4 2,073.2 2,274.8 9.2%

Software IP 6.2 9.0 12.5 15.8 16.7 17.6 19.4 16.6%

VerificationIP 51.7 59.2 70.4 82.6 90.3 95.4 111.7 13.5%

Simulation 186.8 197.0 215.6 237.5 251.2 260.3 277.3 7.1%

Analog 186.8 197.0 215.6 237.5 251.2 260.3 277.3 7.1%

Design 330.4 352.2 352.1 369.7 395.6 431.6 455.8 5.3%

RF Design & Simulation 231.0 243.5 248.9 261.4 279.7 305.1 323.4 5.8%

Analog Design 99.4 108.7 103.2 108.3 115.9 126.5 132.4 4.0%

Misc 215.4 224.5 228.2 236.6 260.5 278.2 292.6 5.4%

Enterprise & CIS Tools 82.0 86.2 84.7 84.7 95.7 105.3 110.6 5.1%

Interop Tools 92.4 95.7 98.9 103.5 111.7 118.7 125.1 5.5%

Design Libraries 40.7 42.2 44.3 48.1 52.7 53.9 56.6 6.0%

CAE Other 0.3 0.4 0.3 0.3 0.3 0.3 0.3 -5.6%

Source: Gary Smith EDA (December 2015)Note: All numbers shown are the best estimates of Gary Smith EDA analysts.

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