Configuring DDR Interface IP to Enhance Speed

and Minimize Design Footprint

Bruce Luo, VP Product Solutions

Shanghai Event September 14, 2017

© 2017

What Limits DDR

Performance?

© 2017

DDRx SDRAM SoC Package

PCB

Die

PCB traces

Application

Software

Timing Margins are Smaller

• LPDDR4 DQS

gating window

only 420 psec

• More sensitivity

to Voltage and

Temperature

changes

3 © 2017

DDR Type Data Rate

(Mbps) Shortest Round

Trip (ps) Longest Round

Trip (ps) DQS Gating

Window (ps)

LPDDR2 1066 2500 5500 1688

DDR3U 1333 255 400 1351

DDR3L 1600 225 400 1125

LPDDR3 1866 2500 5500 964

DDR3 2133 180 400 844

DDR4 3200 160 225 562

LPDDR4 4266 1500 3500 421

0 500 1000 1500 2000

LPDDR2

DDR3L

DDR3

LPDDR4

DQS Gating Window (psec)

Static & Dynamic Variations

DDRx SDRAM SoC Package

PCB

Die

PCB traces

Application

Software

Process Voltage Temperature Static Variation Dynamic Variation

4 © 2017

The Modeling Approach

© 2017

Build the Best Model You Can

• With limited engineering

samples, go through each chip

and find the timing parameter

that works

• Find the average of the timing

window

• Set registers to accommodate

most chips at production

• And WORRY!

6 © 2017

Static vs. Dynamic Timing Window

7

t1 t2 t3 t4 t5 t6 t7 t8 tn

Dat

a W

ind

ow

t0

Part #1 Part #2

Part #3

Part #4

Part #5

Real Timing

Window

Timing Window Reduction Due to Part Variation at Production

Static Timing Window

Static Parameter Setting at Production Via

Registers

© 2017

Static vs. Dynamic Timing Window

8

t1 t2 t3 t4 t5 t6 t7 t8 tn

Dat

a W

ind

ow

t0

DDR System Failure

Dynamic Timing Window

Static Timing Window

Static Parameter Setting at Production

© 2017

Dynamic Variation Between Production Parts

9

t1 t2 t3 t4 t5 t6 t7 t8 tn

Dat

a W

ind

ow

t0

DDR System Failure

Part #1 Part #2

Part #3 Part #4 Part #5

Static Timing Window

Static Parameter Setting at Production

© 2017

The Solution:

Self-Calibrating Logic

© 2017

Precise Measurement

• No guessing with

Self-Calibrating Logic (SCL)

• Accurately measure timing

in the system

• Accommodates each unique

system at production

• Relax! Your worry is over!

11 © 2017

Dynamic SCL Ensures Maximum Data Rate

12

t1 t2 t3 t4 t5 t6 t7 t8 tn

Dat

a W

ind

ow

t0

Dynamic Timing Window

© 2017

Dynamic Self Calibrating Logic

The Fastest DDR SoC Interface IP

• Get the best performance for

your system

• SCL measures system timing

parameters: SoC + PKG + PCB

• Adjusts timing for each system

at production

• Delivers fastest DDR data rate in

all silicon nodes

13 © 2017

Improving Area and Reliability

© 2017 14

DDR IOs

DDR IOs

DDR PHY

DDR PHY

DDR PHY

DDR PHY

DDR PHY

DDR PHY

DDR controller, scheduler

Block 1

Block 2 Block 3

Wasted Area

Remove Wasted Area in Floorplan

DDR IOs

DDR IOs

DDR controller, scheduler

Block 1

Block 2 Block 3

Customized PHY for any pad frame Only 2–3 weeks instead of months effort

DDR PHY

DDR PHY

DDR PHY DDR PHY DDR PHY

Saved Area

Ultra-Low Area Footprint

Optimal PHY & IO Integration

• PHY along side the IO pads

• Allows any pad ordering

• PHY height kept to a minimum

17 © 2017

DDR Controller Integration Flexibility

• Integrate memory controller and close

timing between controller and PHY

18 © 2017

PHY Chaining Saves Top-level Routing

• Training/config. signals routed between PHY edges • Most top-level connections between memory controller

and address PHY

• Tighter top level floorplan

Block 1 Memory

Controller

Byte 0 Address phy Byte 2 Byte 3 Byte 1

Block 2

Allows extremely narrow channel next to PHYs in top level

Block 3

19 © 2017

Satellite Flops Help Close Timing

Address PHY Lane 0 Lane 3 Lane 2 Lane 1

Satellite

flop regions

• Helps meet timing on critical DFI paths from MC

and address PHY to far flung data PHYs

• Ensures same clock cycle timing to all PHYs

Memory controller

Stage 1 Stage 0

Stage 0 Stage 1

Stage 0 Stage 1

Stage 0 Stage 1

20 © 2017

Satellite Flops Placed on the Top Level

• Area efficient

• Fewer signal routes, lower latency

• Convenient to close timing

21 © 2017

DDR IOs Influence ASIC Floorplan

• Why is DDR IO span is so wide?

– Need 1 VDDIO or VSSIO pad for every DDR signal

IO (SSO ratio of 2:1) for high performance

designs

– Need decap for VDDIO/VSSIO power

• Shorter DDR IO pad frame saves area

22 © 2017

Padframe Shortened by 50%

• Signal IOs on inner row

• Power/decap IOs on outer row

• Typical wirebond designs use 3 rows of bond pads

Signal Pad 1

Signal Pad 2

Signal Pad 3

Signal Pad 4

IOVDD

D E C A P

I OVS S

D E C A P

IOVDD

D E C A P

I OVS S

D E C A P

23 © 2017

Flexible DECAP Scheme for Area

PADS

DECAP CELLS STRONG VERTICAL CONNECTIVITY

• Rows of decap cells are added incrementally beyond the outer IO row

• Right place, right amount!

24 © 2017

Uniquify Combination DDR Interface IP

• Supports multiple

different SoC applications

• LPDDR 4/3

• DDR 4/3

• DDR 4/3 + LPDDR 3

• DDR 4/3 + LPDDR 3/2

25 © 2017

Foundry Proven Silicon DDR Interface

GF 55LPe, 40LP, 28SLP/HPP, 22FDX

ICF 14FF

SMIC 55LL, 40LL, 28HK

Samsung 28LPP

TSMC 40G/LP, 29HPC/HPC+/HPM

UMC 28HLP

Thank You.

For more information, please contact

Bruce Luo

BLuo@Uniquify.com

26 © 2017