Computer System Structures cz:Struktury počítačových...

Computer System Structures

cz:Struktury počítačových systémů

Lecturer: Richard Šusta

ČVUT-FEL in Prague, CR – subject A0B35SPS

SPS 2

Metastability in FSM

[image source: http://www.asic-world.com/]

2

SPS 3

Conditions for DFF Operation

Trigger on positive clock edge

Setup time – minimum time for which input must be maintained prior to

the occurrence of the clock transition.

Hold time – minimum time for which the input must not change after the

clock transition.

Propagation delay – time interval between clock transition and

stabilization of the output to a new state.

clock

input changing stable

setup hold

propagation delay output

Cyclone II speed grade 6 for DFFE

without LUT and interconnections

delayes

tsetup>-36 ps, thold>266 ps

tprop= 141ps

After adding delays of LUT and

interconnection, actual times are

much longer typically 5x, 10x or

more….

SPS 4

Minimum pulse width constraint

constraint: cz: omezující podmínka, ohraničení, omezení

eng: the quality or state of being checked, restricted, or compelled to avoid or

perform some action <the individual spirit anxious for freedom from constraint—

W.C.Brownell>, a restriction or limitation that contains a motion or other process

(as the action of a cam (cz:vačka) in machinery)

[quoted from Merriam-Webster's dictionary]

Cyclone II speed grade 6

tmin>>191 ps → tmin>=1,91 ns

ACLRN

minimum pulse width

output

Clocks

In a system design, clocks may be generated by external chips

The idea assumption is that the clock edge are synchronized at each device

A digital clock signal is ideally a 50% duty cycle square wave

A “clock domain” is comprised of the a set of signals that are referenced to the same idea clock signal.

CPUs RAM Memory & I/O control

clock

5

What happens

when constraints are violated? Two stable states and one

metastable state

Ugly characteristic:

unbounded recovery time tr

Graphic source: J. Rabaey, Digital Integrated Circuits,

© Prentice-Hall, 1996

Vi1

Vo1=Vi2

Vo2

Vi1 Vo2

Vo

1

Vi2

= V

o1

Vi2

= V

o1

Vi1 = Vo2

A

C

B

Metastable

point

Vout1

=H V

out2=L

Vout1

=L V

out2=H

Metastable

State

6

Metastability

Metastability

CLK

DIN

DOUT FF CLK

DIN DOUT

[John Brickner, FPGA Technologis, QuickLogic 2005]

Metastability Window: The

specific length of time, during

which both the data

and clock should not occur. If both

signals do occur, the output may

go metastable.

7

What happens

when constraints are violated? Three possible scenarios

1. New D value is correctly recorded

2. Circuit remains in old D value for an extra cycle

3. Metastability - “stuck” output between legal 0 and 1 until it “resolves”

CLK

D

Q1

Q2

Q3

Resolution Time tr

thold tsetup

8

Recovery time

tclk-q

Number

Of

Occurrences

Recovery Time

Measured by statistical methods, depends on chip

technology

The resolution time is a random variable with

exponentioal distribution function (τ is decay constant)

Typical” values are for old 74 flip-flops is about 70ns,

for a 0.25µm ASIC library flip-flop is around 2.3 ns

9

Setup nad Hold Times Dependency

Setup and hold times mainly depend on

the technology of flip-flops

routing of signals, i.e. delays on wires

clock distributions to flip-flops

Setup and hold times do not depend on

frequency

10

Example: Metastability Caused by Adding Circuit

VCC CLK INPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

External

Circuit

VCC CLK INPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

Q5OUTPUT

OK

Metastable due to hold time violation

11

Delay - wires + logic

t

x

datapath Logic Element

Data busses

clock

clock skew, delay in distribution

12

Metastability Caused by Clock Skew Flip flop 0

clock

Flip-flop 0

output

Flip-flip-1

output

Flip-flop 2

output

Flip-flop 2

clock

Flip-flip 0

-input

• Flip-flop2 clock signal is accidently ahead of flip-flop 0 clock signal in FPGA circuit.

• Hold time violation occurs at flip-flop 0 data input for the edge that depends on flip-flop 2

output.

• Flip-flop 0 metastability can result in wrong final state of flip-flop 0 output.

• Divider can accidently dived by 4 instead of 5.

13

Quartus Compiler Report

14

Removing Metastability

Removing metastability means removing setup

and hold time violations in circuit. Many

methods can be tested, e.g.

1. Rearranging circuits

2. Increasing delay by adding LCELL

3. Synchronizers

4. Negative/Positive edges phases

and others.....

15

1. Rearranging Circuit

VCC CLK INPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

VCC CLK INPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

External

Circuit

External

Circuit

Hold time violation was reduced, the divider operates OK under

normal conditions, under non-normal ???

Metastable

16

2. Increasing Delay by LCELLs

External

Circuit

VCC CLK INPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

LCELL

inst

LCELL

inst6

LCELL

inst7

LCELL

inst8

17

Hold time violation removed, the divider is OK

The LCELL buffer allocates a logic cell for the project and always consumes one logic cell.

It is not removed from a project during logic synthesis. When you turn on the "Ignore

LCELL Buffers logic option", the Compiler automatically converts all LCELL buffers

to WIRE primitives. [Source: Quartus Guide]

3. Synchronizer

VCC CLK INPUT

Q5 OUTPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

VCC

VCC

CLRN

D PRN

Q

DFF

inst5

External

Circuit

Synchronizers isolate metastable signals

and datapaths, they are preferred solutions of metastability.

D Q

>C

D Q

>C

clk

unknown input

potentially metastable

signal “probably safe” signal

18

The divider is OK, but its

output is delayed by 1 clock.

4. Negative/Positive Edge Phases

VCC CLK INPUT

Q5 OUTPUT

VCC VCC

VCC

VCC VCC

VCC

CLRN

D PRN

Q

DFF

inst1

CLRN

D PRN

Q

DFF

inst2

CLRN

D PRN

Q

DFF

inst3

NOR2

inst11

XOR

inst12

AND2

inst13

VCC

VCC

CLRN

D PRN

Q

DFF

inst6

NO

T

inst

External

Circuit

19

Hold time violation was removed, the divider operates OK

without delay, but its maximum frequency is limited to 1/2

analogy of master slave

VHDL

VHSIC (Very High Speed Integrated

Circuit) Hardware Description

Language for formal description and

design of electronic circuits

SPS 21

What is VHDL?

A design entry language

A design simulation and modeling

language

A netlist language for expressing circuit

connectivity between a hierarchy of

blocks

A standard language

SPS 22

VHDL history

1981: Initiated in 1981 by US DoD ( U.S Department of Defense )

to address the hardware life-cycle crisis (note: Ada was also

initiated by DoD in 1970)

1983-85: Development of baseline language by Intermetrics, IBM

and Texas Instruments

1986: All rights transferred to IEEE (read I-Triple-E) - Institute of

Electrical and Electronics Engineers

* 1987: IEEE Standard VHDL 1987

DoD requires comprehensive VHDL descriptions supplied with every

ASIC delivered to the DoD.

1994: Revised standard (named VHDL 1076-1993)

2009: Revised Standard (named VHDL 1076-2008)

SPS 23

Verilog versus VHDL

World market divided between VHDL & Verilog Verilog - introduced in 1983 as simulation language,

afterwards extended with support for synthesis added.

VHDL mostly in Europe

Verilog dominant in US

VHDL More general language

More high-level constructs

Better extendibility by packages

Verilog: Not as general as VHDL

Better for low-level circuits

Simpler than VHDL, especially for C and Java programmers, but it can also confuse them by illusion on similarity to C

SPS 24

VHDL / Verilog Google searches

ECE 545 – Introduction to VHDL

Describing

Combinational Logic

Using

Dataflow Design Style

SPS 26

Register Transfer Level (RTL)

Design Description

Combinational

Logic Combinational

Logic

Registers

…

Today’s Topic

SPS 27

VHDL Design Styles

Components and

interconnects

structural

VHDL Design

Styles

dataflow

Concurrent

statements

behavioral

• Registers

• State machines

• Test benches

Sequential statements

Register Transfer

Level (RTL) stype

SPS 28

VHDL data types

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

types derived from

std_logic type

pro

ble

ma

tic o

r im

po

ssib

le

imp

lem

en

tatio

n in

ha

rdw

are

file I/O

float 3.1415

integer 1234

boolean

bit 0, 1

string "1234"

character 'a'

SPS 29

Multi-Valued Logic Representations MVL - 9

more states of signals

MVL - 9

Unitialized ‘U’ Weak 1 ‘H’

Don’t Care ‘-’ Weak 0 ‘L’

Forcing 1 ‘1’ Weak Unknown ‘W’

Forcing 0 ‘0’ High Impedance ‘Z’

Forcing Unknown ‘X’

Wired

Or/And

Impossible implement in

Cyclone II

SPS 30 SPS 30

Bit versus std_logic

• Bit – values '0'and '1' • Boolean - values TRUE a FALSE

only conditions • std_logic MVL-9: enumarated type with

values defined by literals '1', '0', 'X', 'Z','U', '-', 'L', 'H', 'W'

• Warning: std_logic and bit are mutually unconvertible

SPS 31

Basic rules for source code

1. VHDL is not case sensitive,

2. VHDL does not understand diacritics, not even in

comments.

3. Identifier must start with a letter, last character cannot be an underscore, two connected underscores are not allowed

4. All statements end with a semi-colon

5. Comments precede with (--) The rest of line is treated as a comment. Carriage return terminates a comment.

6. No method for commenting a block

SPS 32

The most important rules

Keep things simple, simple programs are the best

Partition the design (Divide et Impera)

Prefer known safe-constructions; VHDL is strongly type

language, many times stricter than Java or Pascal

Keep in mind that synthesizable VHDL code is not

classic program but it describes circuits. To keep circuits

simple, check results of your work

(in Quartus II: Locate->Locate in RTL View, Locate in

Technology Map View...)

SPS 33

Basic structure

of VHDL code

each module contains at least one entity design unit and one or more

architecture design units. Entity describes I/O ports in port section,

architectures describe desired implementations.

comp2bit - an arbitrary label for our entity, invented by the user.

dataflow - an arbitrary label for our architecture, recommended

names should be derived from words "dataflow", "structural",

"behavioral" ("rtl") to suggest types of architecture descriptions.

entity comp2bit

architecture dataflow an implementation of Y is '1' whenever

A1 A0 is greater or equal than B1 B0

Y A1 A0

B1

B0

port

a1

a0

b1

b0

y

comp2bit

inst1

SPS 34

VHDL code of 2 bit comparator

library ieee;

use ieee.std_logic_1164.all;

architecture dataflow of comp2bit is

begin

-- (B1'+A1).(B0'+A0)+A1.B1' - see slide 27 from 2nd lecture

y <= ((not b1 or a1) and (not b0 or a0)) or (a1 and not b1);

end dataflow;

entity comp2bit is

port ( a1, a0 : in std_logic; -- input A

b1, b0 : in std_logic; -- input B

y : out std_logic -- A>=B );

end entity;

library and included package of standard logic

entity describes input

and output pins of module to

which is possible connect

from outside, i,e. design

interface

architecture describes internal implementation of module

1

2

3

4 5

6

To-do list for explanations of

comp2bit

Libraries

Logical operators

Modes of ports

<= Concurrent assignment

A1A0>=B1B0 comparison

More architecture design units

1

2

3

4

5

6

SPS 36

Basic libraries

library ieee;


access to all the names declared within

package STD_LOGIC_1164 in the library IEEE

The package defines the basic standard logic data

types and a few functions. It should probably be

included in every VHDL file you create.


comp2bit

Libraries

Logical operators

Modes of ports




1

2

3

4

5

6

SPS 38

Entity

closing parenthesis terminates list of

parameters, adding ; separator before

closing ) is frequent error

SPS 39

4 IO modes in port declaration

IO Signal

Modes

in port

in out inout buffer

preferred

SPS 40

BUFFER and INOUT mode usually have more difficult

implementations, thus IN and OUT. modes are preferred.

IN, OUT, INOUT, BUFFER modes

IN: data flows in, like an input pin

OUT: data flows out, just like an output. The output

cannot be read back by the entity

INOUT: bi-directional, used for data lines of a CPU etc.

BUFFER: similar to OUT but it can be read back by

the entity. Used for control/address pins of a CPU etc.,

VHDL for programmable logic,

Skahill, Addison Wesley

SPS 41

Miniotázky: IN, OUT, INOUT, BUFFER

• Draw the schematics of the four types

• Based on the following schematic, identify the modes of the IO pins.

VHDL for programmable logic,



comp2bit

Libraries

Logical operators

Modes of ports




1

2

3

4

5

6

Structure of VHDL file

Entity

Library

declaration

Entity

declaration

Architecture

body 1

Architecture

body …

Architecture

body n

Config A config section is only

optional reserved for cases

of more architectures,

More architectures

allow switching among

implementations for

design, simulation,

testing purposes... etc.

43

SPS 44

Example of Configuration library ieee; use ieee.std_logic_1164.all;

entity comp2bit is port ( a1, a0 : in std_logic; -- input A



end entity;


begin y <= ((not b1 or a1) and (not b0 or a0)) or (a1 and not b1);

end dataflow;

architecture dataflow_disable of comp2bit is

begin y <= '0';

end dataflow_disable;

configuration cfg of comp2bit is -- Configuration Declaration

for dataflow -- Block Configuration

end for;

end cfg; All configuration blocks for all entities must be

be placed n one file.


comp2bit

Libraries

Logical operators

Modes of ports




1

2

3

4

5

6

SPS 46

Logical operators defined for types: boolean and many types derived from

std_logic and bit

Logic operators precedence

and or nand nor xor not xnor

not

and or nand nor xor xnor

Highest

Lowest

only in VHDL-93

SPS 47

Incorrect y <= a and b or c and d ;

equivalent to

y <= ((a and b) or c) and d ;

equivalent to y = (ab + c)d

No Implied Precedence

Correct y <= (a and b) or (c and d) ;

y = ab + cd


comp2bit

Libraries

Logical operators

Modes of ports




1

2

3

4

5

6

SPS 49

Concurrent Assignments

a

b s

c

s <= a xor b;

c <= a and b;

Which concurrent statement will be executed first<?

•In hardware, the both run concurrently!

•In simulation, they are executed

sequentially but in unspecified order

SPS 50

Signals can be assigned only one times

architecture dataflow of comp2bits is


end dataflow;

architecture dataflow1 of comp2bits is

begin

y <= ((not b1 or a1) and (not b0 or a0));

y <= y or (a1 and not b1); end dataflow1;

2 errors

double assignment

+ reading out port y

((not b1 or a1)

and (not b0 or a0))

y

or (a1 and not b1)

A1 A0

B1

B0

port A1

B1 y

port

y

SPS 51

Can the outputs be connected together?

C1

C2

?? Signal c1,c2, b1: std_logic;

b1<=c1;

b1<=c2;

Cyclon II and also majority of other FPGA families allow only

one concurrent assignment of each signal in section.

Sometimes somewhere

Once upon a time

SPS 52

Signal as internal wire

architecture dataflow of comp2bits is


end dataflow;

architecture dataflow1 of comp2bit is

signal y1: std_logic; -- y1 is our internal wire

begin

y1 <= ((not b1 or a1) and (not b0 or a0));

y<= y1 or (a1 and not b1);

end dataflow1;

OK

((not b1 or a1)

and (not b0 or a0))

y1

or (a1 and not b1)

y1 A1 A0

B1

B0

port A1

B1 y

port


comp2bit

Libraries

Logical operators

Modes of ports




1

2

3

4

5

6

SPS 54

Original VHDL of 2 bit comparator

library ieee;



begin

-- (B1'+A1).(B0'+A0)+A1.B1' - see slide 27 from 2nd lecture

y <= ((not b1 or a1) and (not b0 or a0)) or (a1 and not b1);

end dataflow;

entity comp2bit is




end entity;

SPS 55

Improved VHDL of 2 bit comparator

library ieee; use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity comp2bit_a is




end entity;

architecture dataflow of comp2bit_a is

signal a,b: std_logic_vector (1 downto 0);

begin

a<=a1 & a0; b<=b1 & b0;

y <= '1' when unsigned(a)>=unsigned(b) else '0';

end dataflow;

A

B

unsigned : D

>= : E

'1' : C

more bits : F

when : G

TO-DO LIST FOR EXPLAINATIONS OF

COMP2BIT_A

Library numeric_std

Numeric conversions

Grouping wires in buses

Relational operators

Comparator for more bits

Numeric literals

A

B

C

D

E

F

Concurrent assignments G

SPS 57

Standard numeric library



package from IEEE library recommended for new synthesis

The package contains definitions types signed and unsigned

together with arithmetic operations for them.

Note: On web, you can find sources with older package

"use IEEE.STD_LOGIC_ARITH.ALL;" that contains different

conversions. For new designs, it is generally recommended to use only


In your own VHDL files, IEEE.STD_LOGIC_ARITH will be forbidden

- you will write new designs and a usage of IEEE.STD_LOGIC_ARITH

suggests that you have copied VHDL from an older file. If you have

copied any code you have to reference its source. Such file is certainly

not counted for your credits.


COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 59

Numbers and buses

Std_logic is a scalar - one wire

Group of wires is created as an array, or bus in digital hardware terms.

A bus is just a group of wires.

Group can represent signed or unsigned number

SPS 60

Vector Declarations

port ( A, B: in std_logic_vector (7 downto 0);

Z: out std_logic_vector (1 to 16)

);

A and B:

Z: 1 2 3 4 5 6 7 8 9

7 6 5 4 3 2 1 0

10 11 12 13 14 15 16

downto order

is preferred

SPS 61

Concatenation - grouping wires

architecture dataflow of example_concatenation is

signal a: std_logic_vector (3 DOWNTO 0);

signal b: std_logic_vector (2 DOWNTO 0);

signal c, d, e, f: std_logic_vector(7 DOWNTO 0);

signal x, y:std_logic;

begin

a <= "0000"; b <= "111"; x<='0'; y<='1';

c <= a & b & x; -- c = "00001110"

d <= y & "0001111"; -- d <= "10001111"

e <= X"0F"; -- e <= "00001111"

f <= (others=>'0') ; -- f <= "00000000"

-- next commands of architecture.....

end dataflow;

SPS 62

Concatenation example

library ieee;


entity wire4bus is

port( x0, x1, x2, x3 : in std_logic;

y : out std_logic_vector(3 downto 0) );

end;

architecture dataflow of wire4bus is

begin

--y(3)<=x3; y(2)<=x2; y(1)<=x1; y(0)<=x0; -- element alternative

y<=x3&x2&x1&x0;

end dataflow;

Notice that VHDL uses ( ) for indexes, e.g. y(3)<=x3;

but Quartus symbolic editor [ ]

SPS 63

Some of array attributes

SIGNAL x : std_logic_vector(31 downto 0);

SIGNAL y : std_logic_vector(0 to 31);

SIGNAL z1 : std_logic_vector(y'RANGE); --(0 to 31)

SIGNAL z2 : std_logic_vector(0 to y'LENGTH-1); --(0 to 31)

SIGNAL z3 : std_logic_vector(y'LOW to y'HIGH); --(0 to 31)

--Note: Arrays with different directions to or downto

are mutually inconvertible!

'RANGE 'LENGTH 'LOW 'HIGH are read only attributes

- similar to Java or C# read-only properties

SPS 64 SPS 64

Vector Attributes • Attributes allow access to signal

definition information – useful when designing generic VHDL

– tells use range, index, length of a signal

• General form is signal_name’attr_name

SPS 65 SPS 65

Pre-defined Attributes Name:

‘left

‘right

‘high

‘low

‘range

‘reverse_range

‘length

Definition

index value on left of range

index value on right of range

greatest index value of range

least index value of range

range expression if signal

reversed signal range expression

number of bits in range

SPS 66 SPS 66

Pre-defined Attributes

Attribute

ex‘left

ex‘right

ex‘high

ex‘low

ex‘range

ex‘reverse_range

ex‘length

Value

11

8

11

8

(11 downto 8)

(8 to 11)

4

signal ex: std_logic_vector(11 downto 8);


COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 68

Bit and vector literal

Single bit binary literals are '0' and '1'

Vector binary literals are "0101", "10_01"

literal values may have an underscore embedded to improve readability

For bit_vectors only, we can also specify values using octal, decimal, or hexadecimal: O”1234”, D”1999”, X”ABCD”

For signed, unsigned and std_logic_vector, you can use only hexadecimal, i.e. X"ABCD".

In case of unsuccesful compilation, you can try use type-tick qulification type'(...) to qualify return type, e.g. e <= signed'(X"0F");

Qualified expressions are commonly used for disambiguating the meaning of strings and

aggregates. They are "hints" to the compiler and legal only if expressions can be legally

interpreted as a value of the qualifying type.

On contrast, signed(X"0F") without apostrophe (tick) is type cast request. In case of signed,

type casting from string literal X"0F" is undefined.

Example of qualifications library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity example_qualification is port ( x, y:in std_logic;

e, e2, e3: out STD_LOGIC_VECTOR(7 DOWNTO 0);

se, se2:out signed(7 DOWNTO 0); ue, ue2:out unsigned(7 DOWNTO 0)

); end entity;

architecture dataflow of example_qualification is

begin

e <= std_logic_vector'(X"0F"); -- e <= "00001111"

se<=signed'(X"0F"); ue<=unsigned'(X"0F");

e2 <= X"0F"; se2<=X"0F"; ue2<=X"0F"; --here, qualifications are possible but not required

-- but typecasts -- se<=signed(X"0F"); ue<=unsigned'(X"0F"); -- are !errors!

-- In the next statement, the qualification is required to determine type on concatenation x & y

with std_logic_vector'(x & y) select e3 <= X"00" when "01",

X"FF" when others;

end dataflow;

69

Numbers in

VHDL

Representation of positive numbers same in most systems, with exception Little/Big Endian storage Major differences are in how negative numbers are represented three major schemes:

• sign and magnitude • ones complement • twos complement

SPS

Unsigned 4-bit numbers

Number Systems

[Seungryoul Maeng:Digital Systems]

Cumbersome subtraction

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7 +8

+9

+10

+11

+12

+13

+14

+15

0 100 = + 4

1 100 = 12

MSB

MSB

Assumptions:we'll assume a 4 bit machine word

71

SPS

Sign and Magnitude Representation

Number Systems

[Seungryoul Maeng:Digital Systems]

Cumbersome addition/subtraction

Sign+Magnitude usually used only

for float point numbers

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7 -0

-1

-2

-3

-4

-5

-6

-7

0 100 = + 4

1 100 = - 4

+

-

72

SPS

Ones Complement (In Czech: První doplněk)

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7-7

-6

-5

-4

-3

-2

-1

-0

0 100 = + 4

1 011 = - 4

+

-

Number Systems

Still two representations of 0! This causes some problems

Some complexities in addition

73

SPS

Twos Complement (In Czech: Druhý doplněk)

0000

0111

0011

1011

1111

1110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0 100 = + 4

1 100 = - 4

+

-

Number Representations

Only one representation for 0

One more negative number than positive number

74


COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 76

Singed unsigned

type STD_LOGIC_VECTOR

is array ( NATURAL range <>) of STD_LOGIC;

type UNSIGNED

is array (NATURAL range <>) of STD_LOGIC;

type SIGNED is array (NATURAL range <>) of STD_LOGIC;

NATURAL specifies numbers from 0 to n,

where n depends on VHDL implementation

<> means that the range of the type is unspecified (unconstrained)

In strong type VHDL, array above are mutually different types

even if they have same internal structure.

SPS 77

SIGNED

STD_LOGIC_VECTOR

Std_logic_vector()

Unsigned()

Signed()

Std_logic_vector()

ieee.Numeric_std

ieee.Numeric_std

ieee.s

td_lo

gic

_1164

INTEGER

To_integer()

To_integer()

To_signed( , length)

To_unsigned( , length)

VH

DL s

tandard

Numeric Conversions

Unsigned() Signed()

UNSIGNED

Type casts

conversion

functions

Resize( , length)

Resize( , length)

SPS 78

architecture dataflow of conversions is

signal slv, slv2, slv3: std_logic_vector (3 DOWNTO 0);

signal uv, uv2: unsigned (3 DOWNTO 0);

signal sv, sv2: signed (3 DOWNTO 0);

signal ui: integer range 0 to 15;

signal si: integer range -8 to 7;

begin

slv<="1111"; uv<=unsigned (slv); sv<=signed (slv); --uv=15, sv=-1

ui<=to_integer (uv); si<=to_integer (sv);

uv2<=to_unsigned (ui,4); sv2<=to_signed (si,4);

slv2<=std_logic_vector (uv2); slv3<=std_logic_vector (sv2);

end dataflow;

Numeric Conversions - example

SPS

Numeric_std versus std_logic_arith

From: http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html

79


COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 81

Relational Operators

= Equal /= Not equal

< Less than <= Less than or equal to

> Greater than >= Greater than or equal to

they have no relative precedence

their results have always type Boolean (TRUE ,FALSE) and

can be used only in conditions

operators = and /= are predefined for all types.

the other operators are defined only for some types, but not

for basic std_logic and std_logic_vector we must first

converted inputs pairs A1 A0 and B1B0 to numbers.

SPS 82

Precedence to logic operators


Logic and relational operators precedence

= /= < <= > >=

not

= /= < <= > >=

and or nand nor xor xnor

Highest

Lowest

In VHDL, there is no relative precedence of relational operators

SPS 83

Operators signed, unsigned

+ - * / rem mod

< <= > >= = /=

result operand operand

unsigned unsigned unsigned

unsigned unsigned natural

unsigned natural unsigned

signed signed signed

signed signed integer

signed integer signed

not and or nand

nor xor xnor

result operand operand

unsigned unsigned unsigned

signed signed signed

SPS 84

Vector Operations

Logic and relation operators and defined for arrays

Z(7)

Z(6)

Z(5)

Z(4)

Z(3)

Z(2)

Z(1)

Z(0)

and A(7)

A(6)

A(5)

A(4)

A(3)

A(2)

A(1)

A(0)

B(7)

B(6)

B(5)

B(4)

B(3)

B(2)

B(1)

B(0)

and

and

and

and

and

and

and

<=

<=

<=

<=

<=

<=

<=

<=

Z <= A and B;

If we have "Signal A, B, Z: std_logic_vector(7 downto 0)" then


COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 86

(1/3): 2 bit comparator with 4 inputs



entity comp2bit_a is




end entity;

architecture dataflow of comp2bit_a is

signal a,b: std_logic_vector (1 downto 0);

begin

a<=a1 & a0; b<=b1 & b0;


end dataflow;

a1

a0

b1

b0

y

comp2bit

inst1

SPS 87

(2/3): 2 bit comparator with vector inputs



entity comp2bitv is

port (a, b: in std_logic_vector (1 downto 0);

y : out std_logic -- A>=B

);

end entity;

architecture dataflow of comp2bitv is

begin


end dataflow;

a[1..0]

b[1..0]

y

comp2bitv

inst

SPS 88

(3/3): Universal comparator



entity compgeq is

generic (

LENGTH : natural := 8

);

port (a, b: in std_logic_vector (LENGTH-1 downto 0);

y : out std_logic -- A>=B

);

end entity;

architecture dataflow of compgeq is

begin


end dataflow;

a[length-1..0]

b[length-1..0]

y

compgeq

inst2

LENGTH 8 Signed Integer

Parameter Value Type

GENERICS

Motivation: Oftentimes we want to be able to specify a property

separately for each instance of a component instead of making specific models for many different configurations of inputs, outputs, and timing information.

VHDL allows models to be parameterized with generics; to make general models.

A generic declares a constant object (read only) its value can be specified as a static expression globally.

Generic information is static - it can not be changed during the simulation.

Generic value is instance-specific -different instances of the same

component can have different values Source: Guangfa Lu, Advanced Topics on VHDL, 2003

89

SPS 90

8 bit comparator implementation

<

CIN

A[7..0]

B[7..0]

LESS_THAN

1

LessThan0

a[7..0]

b[7..0] y

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT

1

CIN

DATAA

DATAB

DATAD

COUT CIN

DATAA

DATAD

COMBOUT

LOGIC_CELL_COMB

1

LessThan0~1

LessThan0~3

LessThan0~5

LessThan0~7

LessThan0~9

LessThan0~11

y

a[0..7]

b[0..7]

LessThan0~14

LessThan0~13

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COMP2BIT_A

Library numeric_std

Numeric conversions




Numeric literals

A

B

C

D

E

F


SPS 92

Concurrent Statements

Three types of concurrent statements

used in dataflow descriptions

<= when-else with-select-when

Concurrent

assignments

Selective

assignments

Conditional

assignments

logic circuit Multiplexors Cascades of

multiplexors

implemented by

used

for

SPS 93

Conditional assigment

general form

x <=

v1 when condition1 else



... else

vN -- all remaining cases

x <=

(condition1 and v1) or

(not condition1 and

condition2 and v2) or

(not condition1 and

not condition2 and

condition3 and v3) or

...

Requred: x-result must be always specified for all possible cases

SPS 94

Implementation conditional concurrent assignment

target_signal <= value1 when condition1 else

value2 when condition2 else

. . .

valueN-1 when conditionN-1 else

valueN;

When - Else

.… Value N

Value N-1

Condition N-1

Condition 2

Condition 1

Value 2

Value 1

Target Signal

…

0

1

0

1

0

1

SPS 95

Conditional Signal Assignment

c <= "0" when a /= b else

"1" when a = '1' else

b;

means a b

"0"

c "1"

SPS 96

entity decoder is port ( A : in std_logic_vector(1 downto 0); Z : out std_logic_vector(3 downto 0) ); end entity decoder; architecture when_else of decoder is begin Z <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000"; end architecture when_else;

Dekodér

Example: One hot

Z(0)

Z(1)

Z(2)

Z(3)

A(1)

A(0)

Inte

rfa

ce

Fun

ction

alit

y A(1..0) Z(3..0)

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

VHDL for programmable logic, Skahill, Addison Wesley

SPS 97

Selected concurrent signal assignment

with choice_expression select

target_signal <= expression1 when choices_1,

expression2 when choices_2,

. . .

expressionN when choices_N;

With –Select-When

choices_1

choices_2

choices_N

expression1

target_signal

choice expression

expression2

expressionN

SPS 98

Selected Signal Assignment

with x select

c <= "0" when "00" ,

"1" when "01" | "10" ,

“b" when others;

x

"0"

c 4

/ “1"

b

0

1

2

3

• Resulting circuit is more compact and faster than circuit produced by conditional assignment.

SPS 99


Allowed formats of choices_k

WHEN value

WHEN value_1 to value_2

WHEN value_1 | value_2 | .... | value N

SPS 100


Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",

b WHEN "011" to "110",

c WHEN "001" | "111",

d WHEN OTHERS;

SPS 101 SPS 101

Decoder for 7-segment hex display

SPS 102

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- 7segment driver hex display of a number

ENTITY SevenSegment IS

PORT( D, C, B, A :IN STD_LOGIC;

segmentsOut: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)

);

END SevenSegment;

Hex 7segment Entity

SPS 103

architecture Behavioral of SevenSegment IS

Signal dataIn:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN dataIn <= D & C & B & A; -- concatenate operator (&)

with dataIn SELECT-- LSB is A

segmentsOut <="1000000" WHEN "0000",-- 0

"1111001" WHEN "0001",-- 1

"0100100" WHEN "0010", -- 2

"0110000" WHEN "0011", -- 3

"0011001" WHEN "0100",-- 4

--

--

"0000011" WHEN "1011",-- b

"0100111" WHEN "1100",-- c

"0100001" WHEN "1101",-- d

"0000110" WHEN "1110",-- E

"0001110" WHEN others;-- for F

END Behavioral;

7segment ARCHITECTURE

SPS 104

7segment with ripple blanIn / blankOut

ENTITY SevenSegment IS

PORT( D, C, B, A :IN STD_LOGIC; blankIn :IN STD_LOGIC; blankOut :OUT STD_logic;

segmentsOut: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );

END SevenSegment;

architecture Behavioral of SevenSegment IS

Signal dataIn:STD_LOGIC_VECTOR(3 DOWNTO 0);

Signal segments: STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

dataIn <= D & C & B & A;

with dataIn SELECT-- LSB is A

segments <="1000000" WHEN "0000",-- 0 "1111001" WHEN "0001",-- 1

"0100100" WHEN "0010", -- 2

--

--

"0000110" WHEN "1110",-- E

"0001110" WHEN others;-- for F "111"

blankOut <= '1' when dataIn="0000" and blankIn='1' else '0';

segmentsOut <= segments when dataIn /= "0000" or blankIn='0' else "1111111

END Behavioral;

Assignment Statements

(summary) SIGNAL x, y, z :STD_LOGIC; SIGNAL a, b, c :STD_LOGIC_VECTOR( 7 DOWNTO 0); SIGNAL sel :STD_LOGIC_VECTOR( 2 DOWNTO 0); 0); -- Conditional Assignment Statement with conditional expressions x <='0' WHEN sel = "000" ELSE y WHEN sel = "011" ELSE z WHEN x = '1' ELSE '1'; -- Selected Signal Assignment Statement -- NOTE: values after "when" keyword must be always constants! WITH sel SELECT x <= '0' WHEN "000", y WHEN "011", z WHEN "100", '1' WHEN OTHERS; -- Selected signal assignments also work with vectors WITH x SELECT a <= "01010101"WHEN '1', b WHEN OTHERS;

105

SPS 106

entity test is

port (in1 : in std_logic_vector (2 downto 0);

out1 : out std_logic_vector (3 downto 0));

end test;

architecture test_arch of test is

begin

out1(0)<=in1(1);

out1(1)<=in1(2);

out1(2)<=in1(0) and in1(1);

out1(3)<=‘1’;

end test_arch ;

From VHDL for programmable logic,


Question: Draw schematic of circuit

SPS 107

Questiom: Write VHDL code

• Vyplňte pravdivostní tabulku a napiště VHDL kód

In1

in2 out00

out10

out11

out01

From VHDL for programmable logic,


…The End… see you the next week

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