Computer Science Exclusive OR/Exclusive NOR...

Erik Jonsson School of Engineering and Th U i it f T t D ll g gComputer ScienceThe University of Texas at Dallas

Exclusive OR/Exclusive NOR (XOR/XNOR)Exclusive OR/Exclusive NOR (XOR/XNOR)• XOR and XNOR are useful logic functions.• Both have two or more inputs. The truth

table for two inputs is shown at right.

XOR/XNOR Truth Tablea b a XOR b a XNOR b0 0 0 1

• a XOR b = 1 if and only if (iff) a ≠ b. • a XNOR b = 1 if and only if (iff) a = b.• Both may also have many inputs. For >2

0 1 1 01 0 1 01 1 0 1

inputs, the XOR output is 1 for an odd number of 1 inputs; XNOR has a 1 output for an even number of 1 inputs.

• Symbols are shown below and to the right

1 1 0 1

XNOR = ab ab

• Symbols are shown below and to the right. Like NAND and NOR, XOR and XNOR are notbasic Boolean functions,

ab

a

XOR a b

© N. B. Dodge 09/121 Lecture #6: More Complex Combinational Logic Circuits

basic Boolean functions, but can be made fromAND, OR and NOT.

XOR = ab aba b

XNOR a b


Quick Simplification ReviewQuick Simplification Review• The first technique we studied to simplify a

Boolean expression used algebraic techniques. • For instance, consider the truth table at right.

a b c f0 0 0 0

0 0 1 0For instance, consider the truth table at right. • The minterms shown represent the SOP

expression: • The Boolean expression is easily simplifiable

i th B l id titi

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 1

f abc abc abc

using the Boolean identities: 1 0 0 11 0 1 0

1 1 0 1

1 1 1 1f abc abc abc abc 1 1

f abc abc abc

• The simplified circuit is shown below the truth table

( ) ( )f ab c c ac b b 1 1

f ab ac


truth table.


Quick Simplification Review (2)Quick Simplification Review (2)W l l t th i t K• We can also plot the minterms on a K-map and graphically simplify the expression (and the circuit).

• On the K-map below the three minterms

a b c f0 0 0 0

0 0 1 0On the K map below, the three minterms ( ) are plotted.

• The simplified expression derived from the two prime implicants is the same as that

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 1

, , abc abc abc

using algebraic simplification. 1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1c b bc bc bc

0 1 3 2

000 001 011 010

100 101 111 110

aa 1 1 1

Identical circuit solution using K-map method:


4 5 7 6a 1 1 1 f ab ac


Exercise 1Exercise 1L t’ d th i lifi ti i b f i• Let’s do another simplification exercise before moving on. Consider this “spec:” The function f of three variables, x, y, and z, is 1 when x and y are both 1 or when x and z are both 1. Find the SOP expression, the simplified expression, and the simplified p , p p , pcircuit. Use the K-map on the next slide to perform the same simplification.

x y z f0 0 0

0 0 1

0 1 0

000

0 1 1

1 0 0

1 0 1

1 1 0

0011


1 1 0

1 1 111


K-Map SolutionK-Map Solution

000 001 011 010

z y yz yz yz

0 1 3 2

000 00 0 0 0

100 101 111 110

xx

4 5 7 6



DecodersDecoders• An n-to-2n decoder is a combinational logic circuit that has n inputs and

up to 2n outputs. That is, it can have 2n outputs, but it may have less. • Each output of a decoder will normally be true (i e go to logic 1) for only• Each output of a decoder will normally be true (i.e., go to logic 1) for only

one combination of the n inputs. • Consider the case of an n = 2 decoder. The decoder will have 2 inputs and

up to 2n = 22 = 4 outputs. p p• Assume that the decoder has the maximum possible number of outputs

(4). Then the truth table for the 2-input decoder will show that for each combination of y and x (00, 01, 10, 11), one of the outputs will go high (l i 1)(logic 1).

• Let us call the inputs y and x and the outputs a, b, c, and d (here, x is the more significant bit). Then let us define a = 1 for x = 0, y = 0; b = 1 for x = 0 and y = 1; c = 1 for x = 1 and y = 0 and d = 1 for x = 1 and y = 1


0 and y 1; c 1 for x 1 and y 0, and d 1 for x 1 and y 1.


Decoders (2)Decoders (2)• The truth tables for a-d in our 2-to-4 decoder are:

x y * a b c d 0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 11 1 0 0 0 1

• Using the truth tables above, we can define a-d in terms of x and y. a x y

Boolean expressions for a, b, c, and d in terms of x and y.

b x y

c x yd

© N. B. Dodge 09/127 Lecture #6: More Complex Combinational Logic Circuits• Note that we put x first because we regard the xy pair as a number, with x the more significant bit.

d x y


Decoders (3)Decoders (3)

• Remembering that• If we consider xy a binary number with x

th MSB d th LSB th d t

, , , :a x y b xy c x y and xy

the MSB and y the LSB, then a-d represent a true condition for each of the four possible binary numbers that x and y can represent.

• Thus we say that each output a-d has an

xy a

bThus we say that each output a-d has an address, which is a unique combination of the two bits in the binary number yx:

b

cFor 00, 1; for 01, 1;xy a xy b

• Based on the logic expressions above, we can d h d d i i h i h

d

For 00, 1; for 01, 1;for 10, 1; for 11, 1.

xy a xy bxy c xy d


draw the decoder circuit as shown at right.


Decoders (4)Decoders (4)I th d d ith 3 i t• In the same way, a decoder with 3 inputs may have up to 23 = 8 outputs, and each output will have a unique “address” that represents one of the eight possible 3 input

abcxp g pcombinations of the three inputs.

• Such a circuit is shown to the right.• In the same way, a 4-input decoder could

have up to 24 = 16 outputs each of which

3-input,eight-output

cdef

y

have up to 24 = 16 outputs, each of which is a unique combination of the inputs.

• Etc., for 5, 6, 7… • Two Notes:

decoder fgh

z

– Any n-input decoder can have up to 2noutputs, but it may have less.

– In general, each output for an n-input decoder is created by a single n-input gxy


AND gate. Its inputs are the n decoder inputs, some of which may be inverted.

gyz


Definition of a MultiplexerDefinition of a Multiplexer

• A multiplexer is a combinational logic circuit that has up to 2ninputs, an n-bit address, and one output.

• The multiplexer connects one of the inputs to the output, depending on the value of the n-bit address.

• The n-bit address is decoded, just as we have studied in the lastThe n bit address is decoded, just as we have studied in the last five slides.

• Thus the multiplexer uses a decoder and a selector circuit (which we will see in a subsequent slide) to tie one of its inputs to its we w see subseque s de) o e o e o s pu s o soutput.

• The multiplexer is usually symbolized by the abbreviation MUX as the symbol for its function.


y


Multiplexer: An “Input to Output” SelectorMultiplexer: An “Input to Output” Selector

• The truth table for a multiplexer is shown below. • Assume a 4-input MUX, with inputs labeled a, b, c, d.Assume a 4 input MUX, with inputs labeled a, b, c, d.• Then there must be two address lines, x (MSB) and y (LSB). • The output is denoted as f.

x y f0 0 a 0 1 b1 0 c


1 1 d


Components of a MultiplexerComponents of a Multiplexer

a

b

Output*

b

c

d

f

Selectory

x

Decoder

* Note that the multiplexer hasa 1-bit output.


• The multiplexer is shown above, with the various parts of the circuit labeled.


Differences in Decoder and MultiplexerDifferences in Decoder and Multiplexer• Decoder:

– A decoder has n inputs, which are called the address. – A decoder has up to 2n outputs (it can have that many, maximum; but it decode as up to outputs ( t ca ave t at a y, a u ; but t

might have less). Each output line is true (or 1) for a specific combinations of the input lines, called the address.

• Multiplexer:– A multiplexer has two sets of inputs: n address lines (just like the

decoder) and as many as 2n inputs, one of which is selected by each address for output (it may have less inputs).

– A multiplexer has only one output. The output is the value of the input selected by the address.

• Thus we see that a decoder makes up a part of a multiplexer.



Exercise 2Exercise 2• Let’s design a simple decoder

and multiplexer. A decoder has a three-inputA decoder has a three input address, x-z, with x = MSB, but although it may have up to 23, or 8 outputs, in this case, it has only three Output 1 is true onthree. Output 1 is true on address 3, 2 on address 6, and 3 on address 7. Design the decoder.

Now using the decoder and adding a selector circuit, design a MUX to output the inputs a-c on addresses 3, 6,


p , ,and 7, respectively.


Binary Arithmetic CircuitsBinary Arithmetic Circuits• A binary adder is a large part of a computer central processor unit

(CPU). The CPU “figuring” unit is sometimes called the ALU, or arithmetic/logic unit, (Patterson and Hennessey call it the “datapath”).

• The ALU or datapath is a combinational logic unit that can add, subtract, or do logical operations such as AND, OR, NOT, etc.

• Consider the “rules of addition” (adding two numbers only*):• Consider the rules of addition (adding two numbers only ):– Numbers are added on a columnar basis, starting on the right.– If the sum of one column is a 2-digit number, the right number goes in

current column and the left number (always a 1) becomes a “carry” to thecurrent column, and the left number (always a 1) becomes a carry to the next column to the left.

– Column addition always includes the carry from the column to the right. – The resulting sum in any column will be only a single digit.


g y y g g* A computer never adds but two numbers together at one time.


Principles of AdditionPrinciples of Addition• Decimal addition example:

“Carries” → 1 15 8 76 4 36 4 3

1 2 3 0 • Binary numbers are added in exactly the same way:

“Carries” → 1 1 1 1 1 1 1 1

1 0 1 0 1 0 0 0 1 1 1+ 0 1 1 1 1 1 1 0 1 0 1

(1) 0 0 1 0 0 1 1 1 1 0 0• Basic principles for an n-column addition:

– Add column i plus carry from column i–1 (ci–1). – If a one-digit result, that number is the sum of column i, si.


– If a 2-digit result, the right digit is si. The left digit is carry i, or ci. – The column i carry, ci, will be added to column (i+1).


A “Half-Adder” CircuitA “Half-Adder” Circuit• We would now like to design a digital

adder for two binary numbers. • Since addition is done on a columnar

basis all that is necessary to add two n

a b S co S Exp co Exp0 0 0 0

basis, all that is necessary to add two n-bit numbers, is to use one binary “column adder” for each of the n bits.

• Thus, to add two 8-bit numbers, we i l i ht l dd

0 1 1 01 0 1 01 1 0 1 ab

aba b

simply use eight column adders.• First we consider a 2-bit “half-adder.”

The truth table on the right shows sum and carry bits for the 2 input bits a & b.

a

bS

y p• Thus, “sum” is the simple SOP

expression: . Likewise, carry out is defined as: The SOP representation of the 2-bit half Half-Adder Circuit

CoS ab ab oC ab


The SOP representation of the 2 bit half adder is at the right.


Alternate Construction of a Half-AdderAlternate Construction of a Half-Adder• We note that in a half-adder, the sum s

is expressed as:

s ab ab • As noted on the first slide today, this is

the expression for the XOR gate.• Thus an alternate expression for s is:

s ab ab

• Note that carry out is still: . • We can then construct the logic gate

s a b oC abg g

equivalent of the half-adder as shown on the right.

• Note that this is no longer a “standard” SOP t ti b t it i i t


SOP representation, but it is easier to build!


“Half-Adder” in Action“Half-Adder” in Action


= 0, =1


The “Full Adder”The “Full Adder”• The half-adder circuit is an important step in

building a digital adder, but it is not the total solution to the binary addition problem.

• When adding binary numbers on a columnar (ci 1)(ci)

Col (i+1) Col (i) Col (i–1)

(ci 2)• When adding binary numbers on a columnar basis, in addition to the column bits, ai and bi, there is also the possibility of a carry bit, ci-1from the column to the right. Thus the 2-bit column adder must be a 3 bit adder

(ci–1)+ai

(ci)+

ai+1

(ci–2)+

ai–1column adder must be a 3-bit adder.• This 3-bit adder is called a “full adder.” • In adding two n-bit binary numbers, the right-

most bits of the two numbers of two numbers

+bi

+bi+1

+bi–1

could be added with a half-adder (no carry in). • However, most adder circuits use all full-

adders, since carry-in for the least significant bit can be useful; we will see that use later in

sisi+1 si–1

Columnar Addition


bit can be useful; we will see that use later in this lecture.

Columnar Addition


Full Adder Boolean EquationsFull Adder Boolean Equations• The full column adder

truth table is shown, along with SOP terms for the 1’s

a b ci S co S Exp co Exp0 0 0 0 01 0 0 1 0 *in the S and co columns.

• For the sum SOP function:*

1 0 0 1 0 *0 1 0 1 01 1 0 0 1

abcabc

abc

• For the carry out SOP function:

0 0 1 1 01 0 1 0 10 1 1 0 1

abcabcabc

S abc abc abc abc

u c o :

• The SOP circuit for the full adder is shown on the

0 1 1 0 11 1 1 1 1

* For simplicity we represent “carry in”

abc abcabc

oC abc abc abc abc


full adder is shown on the next slide.

For simplicity, we represent carry in above simply as c.


SOP Circuit for a Full AdderSOP Circuit for a Full Adder

• Above is the SOP equivalent circuit for a full adder Note


• Above is the SOP equivalent circuit for a full adder. Note that sum and carry have a common term.


Alternate Construction of Full AdderAlternate Construction of Full Adder• We note that since we can construct

a full-adder similarly to a half-adder, then we should be able to use the alternate half-adder (XOR logic) to construct a full adder.

• That is, for the full adder, – ( )S a b c –– Where c = cin

• The equivalent logic construction is i i i i

( )S a b c ( )oC ab a b c

shown in the circuit on the right. • The exact proof is left to the student. • Although this is an easier circuit to

build (XOR’s simplify the circuit), it


build (XOR s simplify the circuit), it is NOT in correct SOP or POS form.


32-Bit Adder32-Bit Adder

1 digit (2 bit) 32 digit (2 bit) adder

• A 32-bit adder would be made up like this: The 32 1-digit full dd ld b i d th t h ld dd l f

1-digit (2-bit) full adder

32-digit (2-bit) adder May be ahalf-adder


adders would be wired up so that each would add one column of two 32-bit numbers (a half-adder could be used in column 1).


SubtractionSubtraction• In the past, digital subtractors were constructed as well as digital adders.

However, it quickly became apparent that the subtraction function could be added very easily to a digital adder.

• Consider the following:Consider the following: – A 1-bit full adder produces carry out (cO) and sum (s) outputs from carry in

(ci) and numerical (a and b) inputs. • We note that , so that we can

subtract using an adder if we:2's complement( ) ( ) 1a b a b a b

subtract using an adder if we:– Invert b (can obtain via an XOR).– Set the carry in input (ci) of bit 0 to 1 (which is why we would need a full adder

even in column 1 of the binary adder circuit). T l t bt ti d t t l i l• To select subtraction, we need two control signals:

• “Invert b” – which selects instead of b.• Carry in, column 1 – which sets ci = 1 for bit 0. • We can combine these into one control signal Add /Sub+

b


• We can combine these into one control signal, Add–/Sub+


Four-Bit Binary Add/Subtract CircuitFour-Bit Binary Add/Subtract CircuitCi

C i 1A

B

C0A0A1

1-Bit Full Adder(Used 4 Times)

Carry in = 1 for subtract.

Ci

A

C1

S0

A2A3

B0B1B2Inputs

CiB

A C3

S0S1S2S3

C2

B3

Outputs

If the Add−/Sub+ input is high, the

Note that the Add−/Sub+ line

Add-/Sub+CiB

A

p g ,XOR’s invert the B input, while if it is low, the B input is not changed

Add /Sub+ line must be XOR’ed with the C3 line to be correct for the subtract case.


B 4-Bit Adder SectionAdd/Subtract Selector

changed.


The ALU or “Datapath”The ALU or “Datapath”

• We have already noted that the arithmetic/logical unit (ALU, or what P&H call the “datapath”) is the “calculating” unit of the computer central processor.

• The amazing thing about the ALU is that it is mostly combinational logic composed of the very logic functions that we have studied so far!

• Patterson & Hennessy discuss a simple version ALU in Chapter 4 of their book that only functions as an AND/OR/add/subtract/compare unit.

• This ALU takes the “columnar” approach we have discussed for a binary adder.

• Their 32-bit ALU (the prototype for the MIPS R2000 computer we


( p yp pwill learn to program later on) is composed of 32 of the 1-bit ALUs.


A 1-Bit ALUA 1-Bit ALU2-Bit MUX Select Address

ORa

AND

1 Bi R l Ob

1-bit Full Adder/Subtractor 4-to-1 MUX

Sum

Carry/Borrow

1-Bit Result Out

Carry In

The 1-bit ALU provides all the possible results of logic/arithmetical analysis to the 4-1 MUX. The 2-bit select address (derived from decoding a part of the

t i t ti ) l t th d i d lt d t t it F i t


computer instruction) selects the desired result and outputs it. For instance, outputting the borrow signal provides a comparison of a and b.


“Bit Slicing:” N 1-bit ALU’s = N-Bit Processor“Bit Slicing:” N 1-bit ALU’s = N-Bit Processor• Thirty-two of the one-bit ALU’s shown on the previous page may be

combined to form a 32-bit MIPS CPU (which we will study later). • In the 32-bit ALU, an operation is performed on all bits at once usingIn the 32 bit ALU, an operation is performed on all bits at once using

the 32 separate 1-bit ALU’s. This “slices” the data into 32 bits, which is where the name “bit slicing” comes from.

• This approach works well for AND and OR functions.This approach works well for AND and OR functions. • For add and subtract, we have to propagate carries from each lower

column to the next higher column. This means that in a 32-bit computer, we have 32 carries (the 32nd carry would be “overflow”). co pu e , we ve 3 c es ( e 3 c y wou d be ove ow ).

• All these carries/borrows are VERY time-consuming, and so some special digital “fast carry” circuits have been developed to accelerate the carry/borrow action (they are not shown on the 1-bit ALU diagram).


y ( y g )• These accelerators are not covered in EE 2310.


Exercise 3Exercise 3• As a special exercise in reviewing the

digital adder plus some of the principles we learned earlierprinciples we learned earlier, consider the following: The SOP Boolean expression for a full adder carry out is:adder carry out is:

This expression can be simplified to

, where o iC abc abc abc abc c c

three terms. Do so. Then show the circuit design.


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