Computer Science 37 Lecture 20

8/4/2019 Computer Science 37 Lecture 20

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1

Lecture20

ControllingaPipelinedDatapath



2

Instructionmemory

Address

4

32

0

Add Add

result

Shiftleft 2

Instruction

Mux

0

1

Add

PC

0Writedata

Mux

1

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

Address

Data

memory1

ALUresult

Mux

ALU

Zero

IF: Instruction fetch ID: Instruction decode/

register file read

EX: Execute/

address calculation

MEM: Memory access WB: Write back



3

Pipelineregisters: Intermediatestorage

Question: howdowedeterminethewidthoftheregisters?



4

Step-by-stepExecutionoflw

InstructionFetch



5


InstructionDecode

InstructionDecode



6


InstructionExecution

Instruction

memory

Address

4

32

0

AddAdd

result

Shift

left 2

I n s t r u c t i o n

IF/ID EX/MEM

Mux

0

1

Add

PC

0Writedata

Mux

1

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

1

ALUresult

Mux

ALU

Zero

ID/EX MEM/WB

Execution

lw

Address

Data

memory



7


MemoryAccess



8


WriteBacktoRegister



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AlternativeGraphicalRepresentationofPipelines

IM Reg DM Reg

IM Reg DM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

lw $10, 20($1)

Programexecutionorder(in instructions)

sub $11, $2, $3

ALU

ALU

lw $10,$20($1)

sub $11,$2,$3

Question: Arethereanyhazardsinthecodeabove?



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ControllingaPipelinedDatapath

PC

Instructionmemory

Address


Instruction

[20–16]

MemtoReg

ALUOp

Branch

RegDst

ALUSrc

4

16 32

Instruction[15–0]

0

0Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1Write

data

Read

data Mux

1

ALU

control

RegWrite

MemRead

Instruction[15–11]

6

IF/ID ID/EX EX/MEM MEM/WB

MemWrite

Address

Datamemory

PCSrc

Zero

AddAdd

result

Shift

left 2

ALUresult

ALU

Zero

Add

0

1

Mux

0

1

Mux



11

KeyAspectstoNoticeinThisDesign:

1) There’snoneedtohavewritecontrolstothePCortothepipeline

registers.

2) Fetch:nothingtocontrol.Samethingdoneeveryclockcycle.

3) Decode:nothingtocontrol.Samethingdoneeveryclockcycle.

4) Execution:decidehowtousetheALU(operands,operation,result)–

RegDst,ALUOp,ALUSrc.

5) Memoryaccess:branch,loadandstoreinstructionshavedifferent

requirements,soonemustspecifyBranch,MemRead,MemWrite

6) Writeback:choosewhatgetswrittenbacktotheregisterfile(theALUresultoramemoryvalue);thecontrolsareMemToReg andRegWrite.

Weusethesamecontrollinesasbefore,butgroupthembypipelinestage.



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So,whathasreallychanged?

Remember: Eachinstructiondefineswhatcontrolvaluesareapplied.

Question: WhathappensnowthatIcanhaveupto5instructionsexecuting

atthesametimeinthedatapath?

Control

EX

M

WB

M

WB

WB

IF/ID ID/EX EX/MEM MEM/WB

Instruction

Allcontroldecisionsaremadeduringtheinstructiondecodingandarecarried

forwardacrossstagesinthepipeline.



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PC

Instructionmemory


Add

Instruction ¡ ¢ £ ¥ ¤ ¦ §

M e m t o R e g

ALUOp

Branch

RegDst

ALUSrc

4

16 32Instruction

¤ ¨ £ ¢ §

0

0

Mux

0

1

AddAdd

result

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux1

ALUresult

Zero

Writedata

Readdata

Mux

1

ALUcontrol

Shiftleft 2

R e g W r i t e

MemRead

Control

ALU

Instruction ¤ ¨ £ ¥ ¤ ¤ §

6

EX

M

WB

M

WB

WBIF/ID

PCSrc

ID/EX

EX/MEM

MEM/WB

Mux

0

1

M e m W r i t e

Address

Datamemory

Address



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Workthroughtheexampleoftheexecutionof

fiveinstructionsstartinginpage471!



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DataHazardsandForwarding

Question: Whatisadata hazard?

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)



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IM Reg

IM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

sub $2, $1, $3

Program

executionorder(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10 ¡ £ ¥ ¦ ¡ ¥ ¦ ¡ ¥ ¦ ¡ ¥ ¦ ¡ ¥ ¦ ¡

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2:

DM Reg

Reg

Reg

Reg

DM



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sub $2, $1, $3

nop

nop

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2sw $15, 100($2)

Possiblesolution: Letthecompilerresolvethehazard

bubble

bubble

Hardwaredesign:

Registerwritesalways

happenatthefirsthalf

oftheclockcycle.

Registerreadsalways

happenatthesecondhalf

theclockcycle.

Nohazardfordatathat

iswrittenandreadinthe

sameclockcycle.

Question: Whatisthedrawbackofthissolution?

Computer Science 37 Lecture 20

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