Computer Organization

CSC 405

Bus Structure

System Bus Functions and Features

A bus is a common pathway across which data can travel within a computer. The main buses in a modern PC are:

The Processor Bus - highest speed bus used primarily by the processor to pass information to and from cache or main memory, and the processor.

The AGP (Accelerated Graphics Port) Bus - A high-speed 66MHz 32-bit bus specifically for a video card. There is a single AGP slot in systems that support it.

The PCI (Peripheral Component Interconnect) Bus - A 33MHz 32-bit bus found in PCs 486 or higher. At one end the PCI is connected to the North Bridge chipset supporting SCSI adapter, network cards, and video cards. At the other end (South Bridge) the PCI bus supports the IDE and USB ports.

The ISA (Industry Standard Architecture) Bus - This is an 8MHz, 16-bit bus that has appeared in PCs since the original 8-bit systems. It is still used for modems, sound cards and other slow I/O peripherals.

Bus/Slot Features

8-bit ISA 8 4.77 2.39

16-bit ISA 16 8.33 8.33

PCI 32 33.33 133.33

PCI-2x 32 66.66 266.66

PCI 64-bit 64 66.66 266.66

PCI-2x 64-bit 64 66.66 533.33

AGP 32 66.66 266.66

AGP-2x 32 66.66 533.33

AGP-4x 32 66.66 1,066.66

Bus/Slot Width (bits) Speed (MHz) Bandwidth (Mbyte/sec)

Pentium II Bus Structure

This architecture consists of two distinct buses emanating from the Pentium II processor:

The L2 cache bus speed scales with processor frequency. For the Pentium II processor at 266 MHz, the L2 cache bus operates at 133 MHz.

Versions of the Pentium II are the Celeron, a low-end Pentium without the L2 cache, and the Xeon, a high-end Pentium that replaces the Pentium Pro for enterprise server and workstation computers.

The system bus for both processors runs at 66 MHz. The Pentium II processor's system bus supports up to 8 outstanding bus requests (4 per processor).

Ref: www.whatis.com

ISA 16 Bus Connection

ISA (Industry Standard Architecture) is a standard bus (computer interconnection) architecture that is associated with the IBM AT motherboard. It allows 16 bits at a time to flow between the motherboard circuitry and an expansion slot card and its associated device(s).

The layout for the ISA card slot is shown on the right. This connector accommodates both a 62 tab ISA-8 card and a 98 tab ISA-16 card.

The ISA-8 and ISA-16 bus connectors reveal the early evolution of the IBM-PC AT computer from an 8 bit bus to a 16 bit bus as well as an increase in the number of IRQs and addressable memory.

Ref: www.whatis.com

EISA Bus Connection

EISA (Extended Industry Standard Architecture) is a standard bus (computer interconnection) architecture that extends the ISA standard to a 32-bit interface. It was developed in part as an open alternative to the proprietary Micro Channel Architecture (MCA) that IBM introduced in its PS/2 computers. EISA data transfer can reach a peak of 33 megabytes per second.

This connector is configured with two double rows of tabs. Notice that the upper signal tab layout is the same as the ISA-16 layout. The EISA doubles the number of possible connections in the expansion slot.

Ref: www.whatis.com

Peripheral Component Interconnect (PCI)

PCI is an interconnection system between a microprocessor and attached devices in which expansion slots are spaced closely for high speed operation. Using PCI, a computer can support both new PCI cards while continuing to support ISA expansion cards. The original PCI was designed by Intel as a local bus. However, PCI 2.0 is no longer a local bus and is designed to be independent of microprocessor design. The PCI interface hardware is synchronized with the clock speed of the microprocessor, in the range of 20 to 33 Mhz.

PCI transmits 32 bits at a time in a 124-pin connection (the extra pins are for power supply and grounding) and 64 bits in a 188-pin connection in an expanded implementation. PCI uses all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next. Burst data can be sent starting with an address on the first cycle and a sequence of data transmissions on a certain number of successive cycles.

Pinout on Next Page

Rear of Computer :------:------: -12V |- B1 A1 -| Test Reset Test Clock |- B2 A2 -| +12V Ground |- B3 A3 -| Test Mode Select Test Data Output |- B4 A4 -| Test Data Input +5V |- B5 A5 -| +5V +5V |- B6 A6 -| Interrupt A Interrupt B |- B7 A7 -| Interrupt C Interrupt D |- B8 A8 -| +5V PRSNT1# |- B9 A9 -| Reserved Reserved |- B10 A10 -| +V I/O PRSNT2# |- B11 A11 -| Reserved :------:------: :------:------: Reserved |- B14 A14 -| Reserved Ground |- B15 A15 -| Reset Clock |- B16 A16 -| +V I/O Ground |- B17 A17 -| Grant Request |- B18 A18 -| Ground +V I/O |- B19 A19 -| Reserved Address 31 |- B20 A20 -| Address 30 Address 29 |- B21 A21 -| +3.3V Ground |- B22 A22 -| Address 28 Address 27 |- B23 A23 -| Address 26 Address 25 |- B24 A24 -| Ground +3.3V |- B25 A25 -| Address 24 C/BE 3 |- B26 A26 -| Init Device Select Address 23 |- B27 A27 -| +3.3V Ground |- B28 A28 -| Address 22 Address 21 |- B29 A29 -| Address 20 Address 19 |- B30 A30 -| Ground +3.3V |- B31 A31 -| Address 18 Address 17 |- B32 A32 -| Address 16 C/BE 2 |- B33 A33 -| +3.3V Ground |- B34 A34 -| Cycle Frame Initiator Ready |- B35 A35 -| Ground +3.3V |- B36 A36 -| Target Ready Device Select |- B37 A37 -| Ground Ground |- B38 A38 -| Stop Lock |- B39 A39 -| +3.3V Parity Error |- B40 A40 -| Snoop Done +3.3V |- B41 A41 -| Snoop Backoff System Error |- B42 A42 -| Ground +3.3V |- B43 A43 -| PAR C/BE 1 |- B44 A44 -| Address 15 Address 14 |- B45 A45 -| +3.3V Ground |- B46 A46 -| Address 13 Address 12 |- B47 A47 -| Address 11 Address 10 |- B48 A48 -| Ground Ground |- B49 A49 -| Address 9 :------:------:

:------:------: Address 8 |- B52 A52 -| C/BE 0 Address 7 |- B53 A53 -| +3.3V +3.3V |- B54 A54 -| Address 6 Address 5 |- B55 A55 -| Address 4 Address 3 |- B56 A56 -| Ground Ground |- B57 A57 -| Address 2 Address 1 |- B58 A58 -| Address 0 +5 I/O |- B59 A59 -| +V I/O Acknowledge 64-bit |- B60 A60 -| Request 64-bit +5V |- B61 A61 -| +5V +5V |- B62 A62 -| +5V :------:------: :------:------: Reserved |- B63 A63 -| Ground Ground |- B64 A64 -| C/BE 7 C/BE 6 |- B65 A65 -| C/BE 5 C/BE 4 |- B66 A66 -| +V I/O Ground |- B67 A67 -| Parity 64-bit Address 63 |- B68 A68 -| Address 62 Address 61|- B69 A69 -| Ground +V I/O |- B70 A70 -| Address 60 Address 59 |- B71 A71 -| Address 58 Address 57 |- B72 A72 -| Ground Ground |- B73 A73 -| Address 56 Address 55 |- B74 A74 -| Address 54 Address 53 |- B75 A75 -| +V I/O Ground |- B76 A76 -| Address 52 Address 51 |- B77 A77 -| Address 50 Address 49 |- B78 A78 -| Ground +V I/O |- B79 A79 -| Address 48 Address 47 |- B80 A80 -| Address 46 Address 45 |- B81 A81 -| Ground Ground |- B82 A82 -| Address 44 Address 43 |- B83 A83 -| Address 42 Address 41 |- B84 A84 -| +V I/O Ground |- B85 A85 -| Address 40 Address 39 |- B86 A86 -| Address 38 Address 37 |- B87 A87 -| Ground +V I/O |- B88 A88 -| Address 36 Address 35 |- B89 A89 -| Address 34 Address 33 |- B90 A90 -| Ground Ground |- B91 A91 -| Address 32 Reserved |- B92 A92 -| Reserved Reserved |- B93 A93 -| Ground Ground |- B94 A94 -| Reserved :------:------:

AGP (Accelerated Graphics Port)

AGP (Accelerated Graphics Port) is a bus specification that enables 3-D graphics to display quickly on ordinary personal computers. AGP is a special interface designed to convey 3-D images (for example, from Web sites or CD-ROMs) much more quickly and smoothly than is possible today on any computer other than an expensive graphics workstation. The interface uses your computer's main storage (RAM) for refreshing the monitor image and to support the texture mapping, z-buffering, and alpha blending required for 3-D image display. The AGP main memory use is dynamic, meaning that when not being used for accelerated graphics, main memory is restored to use by the operating system or other applications.

Ref: www.whatis.com

Serial Interface

Serial communication between your PC and the modem and other serial devices adheres to the RS-232C standard. The serial port supports sequential, one bit-at-a-time transmission to peripheral devices such as scanners and the parallel port supports multiple-bit-at-a-time transmission to devices such as printers. Ref: www.whatis.com