Computer Organization and Architecture-1

1.Convert the following decimal numbers to binary:

a. 1231=1,0,0,1,1,0,0,1,1,1,1

b. 673=1,0,1,0,1,0,0,0,0,1

c.1998=1,1,1,1,1,0,0,1,1,1,0

2.Give and explain one stage of logic circuit.

In many computers only four: AND, OR, XOR (exclusive OR) and complement

micro-operations are implemented. Other 12 micro- operations can be derived from these

four micro-operations. Figure 8 shows one bit, that is the ih bit stage of the four logic

operations. Please note that the circuit consist of 4 gates and a 4 x 1 MUX. The ih bits of

Register R1 and Rz are passed through the circuit. On the basis of selection inputs Soand S1

the desired micro-operation is oblained.

3.Explain Von Neumann Architecture.

von Neumann Architecture. John von Neumann elucidated the first practical stored-program computer architecture (scheme for connecting computer components) in the mid-1940s. It is comprised of the five classical components (input, output, processor, memory, and datapath). The processor is divided into an arithmetic logic unit (ALU) and control unit, a method of organization that persists to the present. Within the processor, the ALU datapath mediates data transfer for computation. The registers are fast memory modules from/to which data can be read/written to support streaming computation, as shown in Figure 1.8. Within the ALU, an accumulator supports efficient addition or incrementation of values corresponding to variables such as loop indices.

Figure 1.8. Schematic diagram of von Neumann architecture, adapted from [Maf01].

The von Neumann architecture has a significant disadvantage - its speed is dependent on the bandiwdht or throughput of the datapath between the processor and memory. This is called the von Neumann bottleneck.

A von Neumann architecture computer performs or emulates the following sequence of steps:

1. Fetch the next instruction from memory at the

address in the program counter. 2. Add the length of the instruction to the program counter.

3. Decode the instruction using the control unit. The control unit commands the rest of the computer to perform some operation. The instruction may change the address in the program counter, permitting repetitive operations. The instruction may also change the program counter only if some arithmetic condition is true, giving the effect of a decision, which can be calculated to any degree of complexity by the preceding arithmetic and logic.

4. Go back to step 1.

4.Compare the register organizations of 8085, Z8000 and MC68000.

The 8085 Architecture follows the "von Neumann architecture", with a 16-bit address bus, and a 8-bit data bus.The 8085 used a multiplexed Data Bus i.e.the address was split between the 8-bit address bus and 8-bit data bus. (For saving Number of Pins)

Registers:

The 8085 can access 216 (= 65,536) individual 8-bit memory locations, or in other words, its address space is 64 KB. Unlike some other microprocessors of its era, it has a separate address space for up to 28 (=256) I/O ports. It also has a built in register array which are usually labeled A (Accumulator), B, C, D, E, H, and L. Further special-purpose registers are the 16-bit Program Counter (PC), Stack Pointer (SP), and 8-bit flag register F. The microprocessor has three maskable interrupts (RST 7.5, RST 6.5 and RST 5.5), one Non-Maskable interrupt (TRAP), and one externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on the processor-a feature which permitted simple systems to avoid the cost of a separate interrupt controller chip.

Buses

* Address bus - 16 line bus accessing 216 memory locations (64 KB) of memory.

* Data bus - 8 line bus accessing one (8-bit) byte of data in one operation. Data bus width is the traditional measure of processor bit designations, as opposed to address bus width, resulting in the 8-bit microprocessor designation.* Control buses - Carries the essential signals for various operations.

The Z8000 is a 16-bit microprocessor introduced by Zilog in 1979The register set consisted of sixteen 16-bit registers, and there were instructions that could use them as 8-bit, 16-bit, 32-bit, and 64-bit registers. The register set was completely orthogonal, with register 15 conventionally designated as stack pointer, and register 14 for stack segment.

There was both a user mode and a supervisor mode.

Like the Z80, the Z8000 included built-in DRAM refresh circuitry. Although an attractive feature for designers of the time, overall the Z8000 was not especially fast and had some bugs, and in the end it was overshadowed by the x86 family.

The most significant of the 32-bit designs is the MC68000, introduced in 1979. The 68K, as it was widely known, had 32-bit registers but used 16-bit internal data paths and a 16-bit external data bus to reduce pin count, and supported only 24-bit addresses. Motorola generally described it as a 16-bit processor, though it clearly has 32-bit architecture. The combination of high performance,

large (16 megabytes or 224 bytes) memory space and fairly low cost made it the most popular CPU design of its class.

5.Give the advantages and disadvantages of physical and functional buses.

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