Computer ArchitectureComputer Architecture

Important PoliciesImportant Policies1. No make-up quizzes and all exams

are close-book unless specified otherwise.

2. Make-up exam is given only when special extenuating situation happens and under the discretion of the instructor

3. You are required to attend every class. Exception is given only if you notify the instructor with a legitimate reason in advance.

Other Important Other Important PoliciesPoliciesDon’t arrive late to the class.All handouts are available on the

instructor's website.You are required to check the

instructor's website periodically (at least once a day before the class time) for important announcement.

Other Important Other Important PoliciesPoliciesAll assignments are due at the

beginning of the class time on the due day unless specified otherwise. No late turn-in will be accepted – no exceptions!!

No copying is allowed on any assignment. No credit will be given to both copier's and copiee's work.

All assignments should include your work, or else no credit will be given.

The Big PictureThe Big PictureWhat is inside a computer?How does it execute my program?

?

The Big PictureThe Big PictureThe Five Classic Components of a Computer

Control

Datapath

Memory

Processor/CPU

Input

Output

I/O Bus

Memory Bus

Processor

Cache

MainMemory

DiskController

Disk Disk

GraphicsController

NetworkInterface

Graphics Network

interrupts

System System OrganizationOrganization

I/O Bridge Core Chip Set

What is Computer What is Computer Architecture?Architecture?

• Coordination of levels of abstraction

I/O systemCPU

Compiler

OperatingSystem

Application

Digital Design

Circuit Design

• Under a set of rapidly changing Forces

Instruction SetArchitecture, Memory, I/O

Firmware

Memory

Software

Hardware

Interface BetweenHW and SW

Computer Computer ArchitectureArchitectureArchitecture: System attributes that have

a direct impact on the logical execution of a program

Architecture is visible to a programmer:◦Instruction set◦Data representation◦I/O mechanisms◦Memory addressing

Levels of Levels of RepresentatioRepresentationn

lw$15, 0($2)lw$16, 4($2)sw $16, 0($2)sw $15, 4($2)

High Level Language Program

Assembly Language Program

Machine Language Program

Control Signal Specification

Compiler

Assembler

Machine Interpretation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs

Rt

Don’t Care(Rt)

Rd

RegDst

Extender

Mux

Mux

3216

imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32

Adr

DataMemory

32

AL

U

MemWr

instruction set

software

hardware

Instruction Set Instruction Set InterfaceInterface

Interfaceimp 1

imp 2

imp 3

use

use

use

time

MIPS I Instruction Set MIPS I Instruction Set ArchitectureArchitecture Instruction

Categories◦ Load/Store◦ Computational◦ Jump and Branch◦ Floating Point◦ Memory

Management◦ Special

R0 - R31

PCHILO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

OrganizatiOrganizationon

-- Capabilities & Performance Characteristics of Principal Functional Units(e.g., Registers, ALU, Shifters, Logic

Units, ...)

-- Ways in which these components are interconnected

-- nature of information flows between components

-- logic and means by which such information flow is controlled.Choreography of FUs to realize the ISARegister Transfer Level Description

Logic Designer's View

ISA Level

FUs & Interconnect

ExecutioExecution Cyclen Cycle

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Obtain instruction from program storage

Determine required actions and instruction size

Locate and obtain operand data

Compute result value or status

Deposit results in storage for later use

Determine successor instruction

Processor Processor PerformancePerformance

HP 9000/750

SUN-4/260

MIPS M2000

MIPS M/120

IBMRS6000100

200

300

400

500

600

700

800

900

1100

DEC Alpha 5/500

DEC Alpha 21264/600

DEC Alpha 5/300

DEC Alpha 4/266

DEC AXP/500IBM POWER 100

Year

Per

form

anc e

0

1000

1200

19971996199519941993199219911990198919881987

Copyright 1998 Morgan Kaufmann Publishers, Inc. All Rights Reserved

Performance TrendsPerformance Trends

Year

Perf

orm

an

ce

0.1

1

10

100

1000

1965 1970 1975 1980 1985 1990 1995 2000

Microprocessors

Minicomputers

Mainframes

Supercomputers

Processor Module

External Cache

DatapathRegisters

InternalCache

Control

Processor

Processor and CachesProcessor and Caches

To main memory

MemoryController

Memory Bus

SIM

M S

lot

0

SIM

M S

lot

1

SIM

M S

lot

2

SIM

M S

lot

3

SIM

M S

lot

4

SIM

M S

lot

5

SIM

M S

lot

6

SIM

M S

lot

7

DRAM SIMM

DRAM

DRAM

DRAM

DRAMDRAMDRAMDRAM

DRAMDRAMDRAM

MemoryMemory

SummarySummaryGoalUnderstand basic operation of a

computerWhy?Software performance is

affected/determined by HW capabilitiesFuture Computer Architects (Processor or

System)

Summary (Continued)Summary (Continued)

AgendaMap “high-level” software to instructionsInstructions are composed of hardware

primitives ◦how to use them◦how to implement them◦why a particular primitive

Memory for storing instructions and data◦Main memory◦Caches◦ interaction with operating system

Input/Output

Summary Summary (Continued)(Continued)

All computers consist of five components◦ Processor: (1) datapath and (2) control◦ (3) Memory◦ (4) Input devices and (5) Output devices

Not all “memory” created equally◦ Cache: fast (expensive, small) memory close to the

processor◦ Main memory: slower, cheaper, larger memory farther

from processor Input and output (I/O) devices has the messiest

organization◦ Wide range of speed: graphics vs. keyboard◦ Wide range of requirements: speed, standard, cost ... etc.