Compu&ng)Systems)) R&DLabeic20anos/wp-content/... · Compu&ng)Systems)R&D)Lab Organized)in)three)...

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Compu&ng Systems R&D Lab Department of Informa-cs Engineering (DEI) Presented by: João M.P Cardoso Email: [email protected] November 7, 2014 20 Years of Informa-cs Engineering at FEUP

Transcript of Compu&ng)Systems)) R&DLabeic20anos/wp-content/... · Compu&ng)Systems)R&D)Lab Organized)in)three)...

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Compu&ng  Systems    R&D  Lab

Department  of  Informa-cs  Engineering  (DEI)    

Presented  by:  João  M.P  Cardoso  

E-­‐mail:  [email protected]  

November  7,  2014  20  Years  of  Informa-cs  Engineering  at  FEUP  

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Compu&ng  Systems  R&D  Lab

Organized  in  three  main  research  groups:  

•  SPECS:  Special-­‐Purpose  Compu-ng  Systems,  Languages  and  Tools  

•  DECS:  Distributed  and  Embedded  Compu-ng  Systems  

• Mobile  and  Distributed  Compu-ng  

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On  addressing  complex  problems  with  Informa-cs  

Engineering  tools    

On  Researching  and  Developing  new  technology  

and  new  techniques    

Close  contact  with  Industry  

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Current  Lab  Members João  M.P.  Cardoso  

PhD,  Prof.  Ali  Azarian  PhD  student  

Pedro  Pinto  PhD  student  

Ricardo  Nobre  PhD  student  

Adriano  Sanches  PhD  student  

Tiago  Carvalho  PhD  student  

João  Bispo  Pos-­‐Doc   Luís  Reis  

PhD  student  

3  We  are  ex-­‐MIEIC  students!  

Pedro  Souto  PhD,  Prof.  

Miguel  P.  Monteiro  PhD,  Prof.  

André  Fernandes,  Researcher  

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Work  Topics  of  Members I  am  working  on  task-­‐level  pipelining  techniques  

I  am  working  on  run-me-­‐aware  

compiler  techniques  

I  am  working  on  techniques  to  iden-fy  

sequences  of  compiler  

op-miza-ons  

I  am  working  on  techniques  to  map  more  efficiently  

computa-ons  to  FPGAs  

I  am  working  on  run-me  Java  improvements  

I  am  working  on  a  

MATLAB  to  C  compiler  

I  am  star-ng  my  PhD  on  

mul-target  OpenCL  

genera-on  

4  We  are  ex-­‐MIEIC  students!  

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Team  ac&vi&es

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Programming…  

Presen-ng…  

Relaxing…  

Par-cipa-ng  in  panels…  

Preparing  Conferences…  

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USP   KIT  

PhD  Exchange   REFLECT  

Cris-ano   Ali  Luiz   André  Tiago  Pedro  

Members  

Projects  

Companies  /Universi-es  

TUDelg   Imperial  

RL8  

UMinho  

João   Ricardo  

INESC-­‐ID  

HiPEAC  

Projects/Collabora&ons  (2012-­‐2014)

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Accelerate!

• Development  cycles  (tools,  domain-­‐specific  languages)  

•  Execu-on  of  applica-ons  (compiler  techniques,  hardware  accelera-on)  

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to  accelerate  changes  to  accelerate  achievements  to  accelerate  innova-on  

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Now  (aNer  20  Years…)

• We  no  more  rely  on  clock  frequency  scaling…  

• Mul-core  and  manycore  architectures  are  to  stay  

•  GPGPUs  and  FPGAs  accelerate  complex  applica-ons    

•  Back  to  experts  of  the  underlying  compu-ng  resources  

•  New  programming  models  are  Now  very  much  needed!  

•  Almost  everything  we  do  depends  on  compu-ng  (compu-ng  is  everywhere!)  

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Our  Lab  is  commiled  to  expose  students  to  those  challenges,  to  expose  them  to  complex  real-­‐life  problems  and  to  problems  from  predic-ons  (trends)  

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FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Rua Dr. Roberto Frias s/n 4200-465 Porto PORTUGAL Phone: +351 22508 1400 Fax: +351 22508 1440 URL: www.fe.up.pt Email: [email protected]

http://www.fe.up.pt/~specs/

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Compu&ng  Systems  R&D  Lab

Scien7fic  Areas  involved  (ACM):  !  Computer   systems   organiza-on,   including   Architectures,   Embedded   and  

Cyber-­‐physical   systems,   Real-­‐-me   Systems,   Dependable   and   Fault-­‐tolerant  Systems  and  Networks  

!  Sogware  nota-on  and  tools  

This  Lab  hosts  projects  in  the  following  areas:    !  Domain-­‐Specific  Languages  (DSLs)  !  Compilers  !  Reconfigurable  Compu-ng  (including  FPGAs)  !  Embedded  Compu-ng  (including  high-­‐performance  embedded  compu-ng)  !  Distributed  Compu-ng,  and  Mobile  Compu-ng  

Contact  person:  Prof.  João  M.P.  Cardoso;  E-­‐mail:  [email protected]  

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Compila&on  to  Hardware

•  From  sogware  to  hardware  •  Genera-ng  hardware  specific  to  the  input  sogware  •  Achieving  performance  benefits  (accelera-on),  energy  savings,  reduc-on  of  power  dissipa-on  peaks  

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Memory Centric High Performance Compu=ng Panel · © 2018 Arm Limited Memory Centric High Performance Compu=ng Panel Jonathan Beard 11 November 2018

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