comp.org Chapter 2

Chapter 2. Machine Instructions and

Programs

Computer Organization

Lecture 6

Objectives Machine instructions and program execution,

including branching and subroutine call and return operations.

Number representation and addition/subtraction in the 2’s-complement system.

Addressing methods for accessing register and memory operands.

Assembly language for representing machine instructions, data, and programs.

Program-controlled Input/Output operations. Operations on stack, queue, list, linked-list, and

array data structures.

Number, Arithmetic Operations, and

Characters

Unsigned Integer

Consider a n-bit vector of the form:

where ai=0 or 1 for i in [0, n-1]. This vector can represent positive integer values V =

A in the range 0 to 2n-1, where

0321 aaaaA nnn

00

11

22

11 2222 aaaaA n

nn

n

Signed Integer

3 major representations: Sign and magnitude

One’s complement

Two’s complement Assumptions: 4-bit machine word

16 different values can be represented

Roughly half are positive, half are negative

Sign and Magnitude Representation

0000

0111

0011

1011

11111110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-0

-1

-2

-3

-4

-5

-6

-7

0 100 = + 4 1 100 = - 4

+

-

High order bit is sign: 0 = positive (or zero), 1 = negativeThree low order bits is the magnitude: 0 (000) thru 7 (111)Number range for n bits = +/-2n-1 -1Two representations for 0

One’s Complement Representation

Subtraction implemented by addition & 1's complement Still two representations of 0! This causes some problems Some complexities in addition

0000

0111

0011

1011

11111110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-7

-6

-5

-4

-3

-2

-1

-0

0 100 = + 4 1 011 = - 4

+

-

Two’s Complement Representation

0000

0111

0011

1011

11111110

1101

1100

1010

1001

1000

0110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0 100 = + 4 1 100 = - 4

+

-

Only one representation for 0 One more negative number than positive

number

like 1's compexcept shiftedone positionclockwise

Binary, Signed-Integer Representations

0000000011111111

00000000

1111

1111

1100110000110011

1010101001010101

1+

1-

2+3+4+5+6+7+

2-3-4-5-6-7-

8-0+0-

1+2+3+4+5+6+7+

0+7-6-5-4-3-2-1-0-

1+2+3+4+5+6+7+

0+

7-6-5-4-3-2-1-

b3 b2b1b0

Sign andmagnitude 1' s complement 2' s complement

B V alues represented

Figure 2.1. Binary, signed-integer representations.

Comparison

Sign and Magnitude Cumbersome addition/subtraction Must compare magnitudes to determine sign of

result One’s Complement Simply bit-wise complement Two’s Complement Simply bit-wise complement + 1

Addition of Positive Numbers

Figure 2.2. Addition of 1-bit numbers.

Carry-out

1

1

+

011

0

1+

0

0

0

+

1

0

1

+

Addition and Subtraction – Sign Magnitude

4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1100

1011

1001

result sign bit is thesame as the operands'sign

4

- 3

1

0100

1011

0001

-4

+ 3

-1

1100

0011

1111 `

when signs differ,operation is subtract,sign of result dependson sign of number withthe larger magnitude

Addition and Subtraction – 1’s Complement

4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1011

1100

10111

1

1000

4

- 3

1

0100

1100

10000

1

0001

-4

+ 3

-1

1011

0011

1110

End around carry

End around carry


Why does end-around carry work?

Its equivalent to subtracting 2 and adding 1n

M - N = M + N = M + (2 - 1 - N) = (M - N) + 2 - 1n n

(M > N)

-M + (-N) = M + N = (2 - M - 1) + (2 - N - 1)

= 2 + [2 - 1 - (M + N)] - 1

n n

n nM + N < 2

n-1

after end around carry:

= 2 - 1 - (M + N)n

this is the correct form for representing -(M + N) in 1's comp!


4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1100

1101

11001

4

- 3

1

0100

1101

10001

-4

+ 3

-1

1100

0011

1111

If carry-in to the high order bit =carry-out then ignorecarry

if carry-in differs fromcarry-out then overflow

Simpler addition scheme makes twos complement the most commonchoice for integer number systems within digital systems


Why can the carry-out be ignored?

-M + N when N > M:

M* + N = (2 - M) + N = 2 + (N - M)n n

Ignoring carry-out is just like subtracting 2n

-M + -N where N + M < = 2n-1

-M + (-N) = M* + N* = (2 - M) + (2 - N)

= 2 - (M + N) + 2n n

After ignoring the carry, this is just the right two’s complementrepresentation for -(M + N)!

n n

2’s-Complement Add and Subtract Operations

1 1 0 10 1 1 1

0 1 0 0

0 0 1 01 1 0 0

1 1 1 0

0 1 1 01 1 0 1

0 0 1 1

1 0 0 10 1 0 1

1 1 1 0

1 0 0 11 1 1 1

1 0 0 0

0 0 1 00 0 1 1

0 1 0 1

4+( )

2-

3+( )

2-

8-

5+( )

+

+

+

+

+

+

1 1 1 0

0 1 0 01 0 1 0

0 1 1 11 1 0 1

0 1 0 0

6- 2-

4+( )

3- 4+( )

7+( )+

+(b)

(d)1 0 1 11 1 1 0

1 0 0 1

1 1 0 11 0 0 1

0 0 1 00 1 0 0

0 1 1 00 0 1 1

1 0 0 11 0 1 1

1 0 0 10 0 0 1

0 0 1 01 1 0 1

0 1 0 1

0 0 1 00 0 1 1

5-

2+( )3+( )

5+( )

2+( )4+( )

2- 7-

3- 7-

6+( )3+( )

1+( )

7- 5-

7-

2+( )3-

+

+

-

-

-

-

-

-

(a)

(c)

(e)

(f)

(g)

(h)

(i)

(j)

Figure 2.4. 2's-complement Add and Subtract operations.

Overflow - Add two positive numbers to get a negative number or two negative numbers to get a positive number

5 + 3 = -8 -7 - 2 = +7

0000

0001

0010

0011

1000

0101

0110

0100

1001

1010

1011

1100

1101

0111

1110

1111

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0000

0001

0010

0011

1000

0101

0110

0100

1001

1010

1011

1100

1101

0111

1110

1111

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

Overflow Conditions

5

3

-8

0 1 1 1 0 1 0 1

0 0 1 1

1 0 0 0

-7

-2

7

1 0 0 0 1 0 0 1

1 1 0 0

1 0 1 1 1

5

2

7

0 0 0 0 0 1 0 1

0 0 1 0

0 1 1 1

-3

-5

-8

1 1 1 1 1 1 0 1

1 0 1 1

1 1 0 0 0

Overflow Overflow

No overflow No overflow

Overflow when carry-in to the high-order bit does not equal carry out

Sign Extension Task:

Given w-bit signed integer x Convert it to w+k-bit integer with same value

Rule: Make k copies of sign bit: X = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0

k copies of MSB

• • •X

X • • • • • •

• • •

w

wk

Sign Extension Example

short int x = 15213; int ix = (int) x; short int y = -15213; int iy = (int) y;

Decimal Hex Binaryx 15213 3B 6D 00111011 01101101ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101y -15213 C4 93 11000100 10010011iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011

Memory Locations, Addresses, and

Operations

Memory Location, Addresses, and Operation

Memory consists of many millions of storage cells, each of which can store 1 bit.

Data is usually accessed in n-bit groups. n is called word length.

second word

first word

Figure 2.5. Memory words.

n bits

last word

i th word

•••

•••


32-bit word length example

(b) Four characters

charactercharactercharacter character

(a) A signed integer

Sign bit: for positive numbers for negative numbers

ASCIIASCIIASCIIASCII

32 bits

8 bits 8 bits 8 bits 8 bits

b31 b30 b1 b0

b31 0=

b31 1=

•••


To retrieve information from memory, either for one word or one byte (8-bit), addresses for each location are needed.

A k-bit address memory has 2k memory locations, namely 0 – 2k-1, called memory space.

24-bit memory: 224 = 16,777,216 = 16M (1M=220) 32-bit memory: 232 = 4G (1G=230) 1K=210

1T=240


It is impractical to assign distinct addresses to individual bit locations in the memory.

The most practical assignment is to have successive addresses refer to successive byte locations in the memory – byte-addressable memory.

Byte locations have addresses 0, 1, 2, … If word length is 32 bits, they successive words are located at addresses 0, 4, 8,…

Big-Endian and Little-Endian Assignments

2k

4- 2k

3- 2k

2- 2k

1- 2k

4-2k

4-

0 1 2 3

4 5 6 7

0 0

4

2k

1- 2k

2- 2k

3- 2k

4-

3 2 1 0

7 6 5 4

Byte addressByte address

(a) Big-endian assignment (b) Little-endian assignment

4

Wordaddress

•••

•••

Figure 2.7. Byte and word addressing.


Address ordering of bytes Word alignment Access numbers, characters, and character

strings

Memory Operation

Load (or Read or Fetch) Copy the content. The memory content doesn’t change. Address – Load Registers can be used

Store (or Write) Overwrite the content in memory Address and Data – Store Registers can be used

Instruction and Instruction Sequencing

“Must-Perform” Operations

Data transfers between the memory and the processor registers

Arithmetic and logic operations on data Program sequencing and control I/O transfers

Register Transfer Notation

Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,…)

Contents of a location are denoted by placing square brackets around the name of the location (R1←[LOC], R3 ←[R1]+[R2])

Register Transfer Notation (RTN)

Assembly Language Notation

Represent machine instructions and programs.

Move LOC, R1 = R1←[LOC] Add R1, R2, R3 = R3 ←[R1]+[R2]

Basic Instruction Types

High-level language: C = A + B Action: C ← [A] + [B] Assembly: Add A, B, C Three-address instruction:

Operation Source1, Source2, Destination Two-address instruction:

Operation Source, Destination Add A, B = B ←[A] + [B]

Basic Instruction Types

Need to add something to the above two-address instruction to finish:Move B, C = C ← [B]

One-address instruction (to fit in one word length) Accumulator: Add A Load A Add B Store C Zero-address instructions (stack operation)

Using Registers

Registers are faster The number of registers is smaller Shorter instructions Potential speedup Minimize the frequency with which data is

moved back and forth between the memory and processor registers.

Using Registers

Load A, Ri

Store Ri, A

Add A, Ri

Add Ri, Rj

Add Ri, Rj, Rk

Move Source, Destination Move A, Ri = Load A, Ri

Move Ri, A = Store Ri, A

Using Registers

In the processors where arithmetic operations are allowed only on operands in registerMove A, Ri

Move B, Rj

Add Ri, Rj

Move Rj, C In the processors where one operand may be in the

memory but the other one must be in registersMove A, Ri

Add B, Ri

Move Ri, C

Instruction Execution and Straight-Line Sequencing

R0,C

B,R0

A,R0

Movei + 8

Begin execution here Movei

ContentsAddress

C

B

A

the programData for

segmentprogram3-instruction

Addi + 4

Figure 2.8. A program for C +

Assumptions:- One memory operand per instruction- 32-bit word length- Memory is byte addressable- Full memory address can be directly specified in a single-word instruction

Two-phase procedure

Branching

NUMn

NUM2

NUM1

R0,SUM

NUMn ,R0

NUM3,R0

NUM2,R0

NUM1,R0

Figure 2.9. A straight-line program for adding n numbers.

Add

Add

Move

SUM

i

Move

Add

i 4n+

i 4n 4-+

i 8+

i 4+

•••

•••

•••

Branching

N,R1Move

NUMn

NUM2

NUM1

R0,SUM

R1

"Next" number to R0

Figure 2.10. Using a loop to add n numbers.

LOOP

Decrement

Move

LOOP

loopProgram

Determine address of"Next" number and add

N

SUM

n

R0Clear

Branch>0

•••

•••

Branch target

Conditional branch

Condition Codes

Condition code flags Condition code register / status register N (negative) Z (zero) V (overflow) C (carry) Different instructions affect different flags

Generating Memory Addresses

How to specify the address of branch target? Can we give the memory operand address

directly in a single Add instruction in the loop?

Use a register to hold the address of NUM1; then increment by 4 on each pass through the loop.

Stacks and Queues

Stacks

A list of data elements, usually words or bytes, with the accessing restriction that elements can be added or removed at one end of the list only.

Top / Bottom / Pushdown Stack Last-In-First-Out (LIFO) Push / Pop

Stacks

Figure 2.21. A stack of words in the memory.

register

Stackpointer

17

BOTTOM

0

SP Currenttop element

elementBottom

Stack

2k

1-

•••

•••

•••

739

43

28-

Stacks Stack Pointer (SP) Push

Subtract #4, SPMove NEWITEM, (SP)

Move NEWITEM, -(SP)

Pop

Move (SP), ITEMAdd #4, SP

Move (SP)+, ITEM

Stacks

Figure 2.22. Effect of stack operations on the stack in Figure 2.21.

(b) After pop into ITEM(a) After push from NEWITEM

17

739

43

ITEM

SP

Stack

SP

NEWITEM

19

17

739

19

43

28-

28-28-

•••

•••

Stacks

The size of stack in a program is fixed in memory.

Need to avoid pushing if the maximum size is reached

Need to avoid popping if stack is empty Compare instruction

Compare src, dst[dst] – [src]Will not change the values of src and dst.

StacksSAFEPOP Compare #2000,SP Check to seeif thestack pointercontains

Branch>0 EMPTYERROR anaddressvaluegreaterthan2000.If itdoes,thestack isempty. Branch to theroutineEMPTYERRORforappropriateaction.

Move (SP)+,ITEM Otherwise,popthetopof thestack intomemorylocationITEM.

SAFEPUSH Compare #1500,SP Check toseeif thestack pointerBranch 0 FULLERROR containsanaddressvalueequal

to or lessthan1500.If it does,thestack isfull. Branch to theroutineFULLERRORforappropriateaction.

Move NEWITEM, (SP) Otherwise,pushtheelement inmemorylocationNEWITEM ontothestack.

–

Figure 2.23. Checking for empty and full errors in pop and push operations.

(b) Routine for a safe push operation

(a) Routine for a safe pop operation

Queues

Data are stored in and retrieved from a queue on a First-In-First-Out (FIFO) basis.

New data are added at the back (high-address end) and retrieved from the front (low-address end).

How many pointers are needed for stack and queue, respectively?

Circular buffer

Subroutines

Subroutines

It is often necessary to perform a particular subtask (subroutine) many times on different data values.

To save space, only one copy of the instructions that constitute the subroutine is placed in the memory.

Any program that requires the use of the subroutine simply branches to its starting location (Call).

After a subroutine has been executed, it is said to return to the program that called the subroutine, and the program resumes execution. (Return)

Subroutines

Since the subroutine may be called from different places in a calling program, provision must be made for returning to the appropriate location.

Subroutine Linkage method: use link register to store the PC.

Call instruction Store the contents of the PC in the link register Branch to the target address specified by the instruction Return instruction Branch to the address contained in the link register

Subroutines

ReturnCall

Figure 2.24. Subroutine linkage using a link register.

1000

204

204

Link

PC

Return

1000

locationMemory

Calling programMemorylocation

200204

Call SUBnext instruction

Subroutine SUB

first instruction

Subroutine Nesting and The Processor Stack

If a subroutine calls another subroutine, the contents in the link register will be destroyed.

If subroutine A calls B, B calls C, after C has been executed, the PC should return to B, then A

LIFO – Stack Automatic process by the Call instruction Processor stack

Parameter Passing

Exchange of information between a calling program and a subroutine.

Several ways: Through registers Through memory locations Through stack

Passing Parameters through Processor Registers

Callingprogram

Move N,R1 R1 servesasacounter.Move #NUM1,R2 R2 pointstothelist.Call LISTADD Callsubroutine.Move R0,SUM Saveresult....

Subroutine

LISTADD Clear R0 Initializesumto 0.LOOP Add (R2)+,R0 Add entryfromlist.

Decrement R1Branch>0 LOOPReturn Returntocallingprogram.

Figure 2.25. Program of Figure 2.16 written as a subroutine; parameters passed through registers.

Passing Parameters through Stack

Assumetopof stack isatlevel1 below.

Move #NUM1, (SP) Pushparametersontostack.Move N, (SP)Call LISTADD Callsubroutine

(topof stackat level2).Move 4(SP),SUM Saveresult.Add #8,SP Restoretopofstack

(topof stackat level1)....

LISTADD MoveMultiple R0 R2, (SP) Saveregisters(top ofstackatlevel 3).

Move 16(SP),R1 Initializecounter to n.Move 20(SP),R2 Initializepointer tothelist.Clear R0 Initializesumto 0.

LOOP Add (R2)+,R0 Add entry fromlist.Decrement R1Branch>0 LOOPMove R0,20(SP) Put resultonthestack.MoveMultiple (SP)+,R0 R2 Restoreregisters.Return Returntocallingprogram.

––

– –

(a) Calling program and subroutine

–

[R2]

[R1]

[R0]

Returnaddress

n

NUM1

Level3

Level2

Level1

Figure 2.26. Program of Figure 2.16 written as a subroutine; parameters passed on the stack.

(b) Top of stack at various times

- Passing by reference- Passing by value

The Stack Frame

Some stack locations constitute a private work space for a subroutine, created at the time the subroutine is entered and freed up when the subroutine returns control to the calling program. Such space is called a stack frame.

Frame pointer (FP) Index addressing to access data inside frame

-4(FP), 8(FP), …

The Stack Frame

Figure 2.27. A subroutine stack frame example.

SP(stack pointer)

FP(frame pointer)

saved [R1]

saved [R0]

Stackframefor

calledsubroutineReturn address

localvar3

localvar2

localvar1

saved [FP]

Old TOS

param2

param1

param3

param4

(top-of-stack)

SP and FP

Move FP, -(SP) Move SP, FP Subtract #12, SP Push R0 and R1 … Pop R0 and R1 Add #12, SP Pop FP Return

Stack Frames for Nested Subroutines

Memorylocation Instructions Comments

Mainprogram...

2000 Move PARAM2, (SP) Placeparametersonstack.2004 Move PARAM1, (SP)2008 Call SUB12012 Move (SP),RESULT Storeresult.2016 Add #8,SP Restorestacklevel.2020 nextinstruction

...

Firstsubroutine

2100 SUB1 Move FP, (SP) Saveframepointerregister.2104 Move SP,FP Loadtheframepointer.2108 MoveMultiple R0 R3, (SP) Saveregisters.2112 Move 8(FP),R0 Getfirstparameter.

Move 12(FP),R1 Getsecondparameter....Move PARAM3, (SP) Placeaparameteronstack.

2160 Call SUB22164 Move (SP)+,R2 PopSUB2resultinto R2.

...Move R3,8(FP) Placeansweronstack.MoveMultiple (SP)+,R0 R3 Restoreregisters.Move (SP)+,FP Restoreframepointerregister.Return ReturntoMainprogram.

Secondsubroutine

3000 SUB2 Move FP, (SP) Saveframepointerregister.Move SP,FP Loadtheframepointer.MoveMultiple R0 R1, (SP) SaveregistersR0and R1.Move 8(FP),R0 Get theparameter....Move R1,8(FP) PlaceSUB2resultonstack.MoveMultiple (SP)+,R0 R1 RestoreregistersR0and R1.Move (SP)+,FP Restoreframepointerregister.Return ReturntoSubroutine1.

––

–

– –

–

–

–

– –

–

Figure 2.28. Nested subroutines.

Stack Frames for Nested Subroutines

Figure 2.29. Stack frames for Figure 2.28.

FP

FP

[FP] from SUB1

2164

Stackframe

forfirst

subroutine

[R0] from Main

param3

[R3] from Main

[R2] from Main

[R1] from Main

Old TOS

2012

[FP] from Main

param1

param2

[R0] from SUB1

[R1] from SUB1

Stackframefor

secondsubroutine

Additional Instructions

Logic Instructions

AND OR NOT (what’s the purpose of the following)

Not R0Add #1, R0

Determine if the leftmost character of the four ASCII characters stored in the 32-bit register R0 is Z (01011010)And #$FF000000, R0Compare #$5A000000, R0Branch=0 YES

Logical Shifts Logical shift – shifting left (LShiftL) and shifting right

(LShiftR)

CR00

before:

after:

0

1

0 0 01 1 1 . . . 11

0 0 1 1 1 000

(b) Logical shift right LShiftR #2,R0

(a) Logical shift left LShiftL #2,R0

C R0 0

before:

after:

0

1

0 0 01 1 1 . . . 11

1 10 . . . 00101

. . .

Logical Shifts Two decimal digits represented in ASCII code are

located at LOC and LOC+1. Pack these two digits in a single byte location PACKED.

Move #LOC,R0 R0pointstodata.MoveByte (R0)+,R1 Loadfirstbyte into R1.LShiftL #4,R1 Shiftleftby 4bit positions.MoveByte (R0),R2 Loadsecondbyte into R2.And #$F,R2 Eliminatehigh-orderbits.Or R1,R2 ConcatenatetheBCDdigits.MoveByte R2,PACKED Storetheresult.

Figure 2.31. A routine that packs two BCD digits.

Arithmetic Shifts

C

before:

after:

0

1

1 1 00 0 1 . . . 01

1 1 0 0 1 011

(c) Arithmetic shift right AShiftR #2,R0

R0

. . .

Rotate

Figure 2.32. Rotate instructions.

CR0

before:

after:

0

1

0 0 01 1 1 . . . 11

1 0 1 1 1 001

(c) Rotate right without carry RotateR #2,R0

(a) Rotate left without carry RotateL #2,R0

C R0

before:

after:

0

1

0 0 01 1 1 . . . 11

1 10 . . . 10101

C

before:

after:

0

1

0 0 01 1 1 . . . 11

1 0 1 1 1 000

(d) Rotate right with carry RotateRC #2,R0

R0

. . .

. . .

(b) Rotate left with carry RotateLC #2,R0

C R0

before:

after:

0

1

0 0 01 1 1 . . . 11

1 10 . . . 00101

Multiplication and Division

Not very popular (especially division) Multiply Ri, Rj

Rj ← [Ri] х [Rj] Any problem? Divide Ri, Rj

Rj ← [Ri] / [Rj]

Example Programs

Vector Dot Product Program

Move #AVEC,R1 R1 pointstovectorA.Move #BVEC,R2 R2 pointstovectorB.Move N,R3 R3 servesasacounter.Clear R0 R0accumulatesthedotproduct.

LOOP Move (R1)+,R4 ComputetheproductofMultiply (R2)+,R4 nextcomponents.Add R4,R0 Add toprevioussum.Decrement R3 Decrementthecounter.Branch>0 LOOP Loopagainif notdone.Move R0,DOTPROD Storedotproductinmemory.

Figure 2.33. A program for computing the dot product of two vectors.

1

0

)()(ProductDot n

i

iBiA

Byte-Sorting Program

Sort a list of bytes stored in memory into ascending alphabetic order.

The list consists of n bytes, not necessarily distinct, stored from memory location LIST to LIST+n-1. Each byte contains the ASCII code for a character from A to Z. The first bit is 0.

Straight-selection algorithm (compare and swap)

Byte-Sorting Programfor (j = n 1; j > 0; j = j 1)

{ for ( k = j 1; k>= 0;k = k 1 ){ if (LIST[k]> LIST[ j])

{ TEMP = LIST[k];LIST[k]= LIST[j];LIST[ j]= TEMP;

}}

}

––––

(a) C-language program for sorting

Move #LIST,R0 LoadLIST intobaseregisterR0.Move N,R1 InitializeouterloopindexSubtract #1,R1 registerR1to j = n 1.

OUTER Move R1,R2 InitializeinnerloopindexSubtract #1,R1 registerR2to k= j 1.MoveByte (R0,R1),R3 LoadLIST(j) into R3,whichholds

currentmaximuminsublist.INNER CompareByte R3,(R0,R2) If LIST(k) [R3],

Branch 0 NEXT donotexhange.MoveByte (R0,R2),R4 Otherwise,exchangeLIST(k)MoveByte R3,(R0,R2) with LIST(j ) andloadMoveByte R4,(R0,R1) newmaximuminto R3.MoveByte R4,R3 RegisterR4servesasTEMP.

NEXT Decrement R2 Decrement indexregistersR2andBranch 0 INNER R1,which alsoserveDecrement R1 asloopcounters,andbranchBranch>0 OUTER back if loopsnotfinished.

(b) Assembly language program for sorting

–

–

Byte-Sorting Program

The list must have at least two elements because the check for loop termination is done at the end of each loop.

If the machine instruction set allows a move operation from one memory location directly to another memory location:MoveByte (R0, R2), (R0, R1)MoveByte R3, (R0, R2)MoveByte (R0, R1), R3

Linked List

Many nonnumeric application programs require that an ordered list of information items be represented and stored in memory in such a way that it is easy to add items to the list or to delete items from the list at ANY position while maintaining the desired order of items.

Different from Stacks or Queues.

Problem Illustration Maintain this list of

records in consecutive memory locations in some contiguous block of memory in increasing order of student ID numbers.

What if a student withdraws from the course so that an empty record slot is created?

What if another student registers in the course?

Student 1

Student 2

Test 3

Test 2

Test 1

Student ID

Test 3

Test 2

Student ID

nN

LIST

Test 1LIST + 4

LIST + 8

LIST + 12

LIST + 16

•••

Linked List Each record still occupies a consecutive four-word block in the memory. But successive records in the order do not necessarily occupy

consecutive blocks in the memory address space. Each record contains an address value in a one-word link field that

specifies the location of the next record in order to enable connecting the blocks together to form the ordered list.

Record 1

(a) Linking structure

Record 2 Record k

Link address

Head Tail

0

Record 2Record 1

New record(b) Inserting a new record between Record 1 and Record 2

List in Memory

Figure 2.36. A list of student test scores organized as a linked list in memory.

First

28106 12001040

1 word 1 word 3 words

Head

(ID) (Test scores)

Memoryaddress

Keyfield

Linkfield

Datafield

record 27243 10402320

40632 12802720

28370 28801200

47871 01280

Secondrecord

Thirdrecord

Second last

Lastrecord

record

Tail

•••

Head pointer

Insertion of a New Record Suppose that the

ID number of the new record is 28241, and the next available free record block is at address 2960.

What are the possibilities of the new record’s position in the list.

INSERTION Compare

Branch>0Move RNEWREC, RHEAD

Return

Compare (RHEAD), (RNEWREC)

Branch>0 SEARCH

Move RHEAD, 4(RNEWREC)

Move RNEWREC, RHEAD

Return

Move RHEAD, RCURRENT

Move 4(RCURRENT), RNEXT

Compare

Branch=0 TAIL

(RNEXT), (RNEWREC)

Branch<0

#0, RNEXT

Compare

HEAD

not empty

#0, RHEAD

HEAD

INSERTMove RNEXT, RCURRENT

Move

Branch

RNEXT, 4(RNEWREC)Move RNEWREC, 4(RCURRENT)

Return

SEARCH

insert new recordsomewhere aftercurrent head

LOOP

insert new record inan interior position

ne w record becomes new tail

INSERT

TAIL

LOOP

new recordbecomes aone-entry list

new recordbecomesnew head

Deletion of a Record

DELETION Compare (RHEAD), RIDNUMBranch>0 SEARCH

Move 4(RHEAD), RHEADReturnMove RHEAD, RCURRENT

Move 4(RCURRENT), RNEXTCompare (RNEXT), RIDNUMBranch=0 DELETE

Move RNEXT , RCURRENTBranchMove 4(RNEXT), RTEMP

RTEMP , 4(RCURRENT)

Return

LOOP

Move

not the head record

SEARCH

LOOP

DELETE

Figure 2.38. A subroutine for deleting a record from a linked list. Any problem?

Encoding of Machine Instructions

Encoding of Machine Instructions Assembly language program needs to be converted into machine

instructions. (ADD = 0100 in ARM instruction set) In the previous section, an assumption was made that all

instructions are one word in length. Suppose 32-bit word length, 8-bit OP code (how many

instructions can we have?), 16 registers in total (how many bits?), 3-bit addressing mode indicator.

Add R1, R2 Move 24(R0), R5 LshiftR #2, R0 Move #$3A, R1 Branch>0 LOOP

OP code Source Dest Other info

8 7 7 10

(a) One-word instruction


What happens if we want to specify a memory operand using the Absolute addressing mode?

Move R2, LOC 14-bit for LOC – insufficient Solution – use two words

(b) Two-word instruction

Memory address/Immediate operand

OP code Source Dest Other info


Then what if an instruction in which two operands can be specified using the Absolute addressing mode?

Move LOC1, LOC2 Solution – use two additional words This approach results in instructions of variable

length. Complex instructions can be implemented, closely resembling operations in high-level programming languages – Complex Instruction Set Computer (CISC)


If we insist that all instructions must fit into a single 32-bit word, it is not possible to provide a 32-bit address or a 32-bit immediate operand within the instruction.

It is still possible to define a highly functional instruction set, which makes extensive use of the processor registers.

Add R1, R2 ----- yes Add LOC, R2 ----- no Add (R3), R2 ----- yes


How to load a 32-bit address into a register that serves as a pointer to memory locations?

Solution #1 – direct the assembler to place the desired address in a word location in a data area close to the program, so that the Relative addressing mode can be used to load the address.

Solution #2 – use logical and shift instructions to construct the desired 32-bit address by giving it in parts that are small enough to be specifiable using the Immediate addressing mode.


An instruction must occupy only one word – Reduced Instruction Set Computer (RISC)

Other restrictions

OP code

(c) Three-operand instruction

Ri Rj Other infoRk

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