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Jan. 16, 2007 RCL - CSM Findings 1
Competitive Semiconductor
Manufacturing
Prof. Robert C. Leachman
Director, Competitive Semiconductor Manufacturing
Program
University of California at Berkeley
Jan 16, 2007
Jan. 16, 2007 RCL - CSM Findings 2
Agenda
Introduction to CSM Program
Technical metrics of fab performance
Economic interpretation
Key practices underlying leading performance
Jan. 16, 2007 RCL - CSM Findings 3
CSM Program
During 1991-2003, one of the largest
interdisciplinary research programs at
Berkeley (8 faculty, 15 students from
Business, Economics and Engineering)
Fab performance benchmarking
Focus studies (MS and PhD projects)
53 CSM research reports generated and made
publicly available
Jan. 16, 2007 RCL - CSM Findings 4
Benchmarking fab performance
1991: Pilot phase with Intel, NEC and HP
1992-96: Studied 29 fabs in USA, Japan,
Korea, Taiwan and Europe under sponsorship
of Alfred P. Sloan Foundation
Mostly 6-inch wafer fabs (six 5-inch, two 4-inch
fabs) operating process technologies ranging from
10 micron down to 0.4 micron line widths
Jan. 16, 2007 RCL - CSM Findings 5
Benchmarking fab performance (cont.)
1997- 2001: Studied 10 fab lines running 8-
inch wafers in 350nm and below CMOS
technologies
Sponsored by Sematech, SIRIJ/EAIJ, TSMC,
UMC, Winbond, Samsung, Micrus, Cypress, ST
Microelectronics
Final report on this phase issued Mar., 2002
2002 - 2003: Study “systematic mechanisms”
yield loss at 5 Sematech member-companies
Jan. 16, 2007 RCL - CSM Findings 6
Factory data collection
Mail-Out Questionnaire (MOQ)
2-3 years of fab history (plus updates)
process technologies, production volumes, yields,
cycle times
equipment and facilities
headcount and HR data
We computed technical metrics from these
data. Identities of fabs were kept confidential.
Jan. 16, 2007 RCL - CSM Findings 7
Studying practices: the site visit
Team of 8 faculty and graduate students for
a 2 or 3 day visit
Tour fab (focus on evidence of self-
measurement, communication, problem-
solving activity
Interview cross-section of organization
(managers, engineers, technicians, operators)
Jan. 16, 2007 RCL - CSM Findings 8
Site visit (cont.)
Sessions to review approaches to problem
areas (yield improvement, equipment
efficiency improvement, cycle time reduction,
on-time delivery improvement, new process
introductions)
Sessions to review problem-solving
resources (CIM and information systems,
process control, work teams, human resource
development)
Jan. 16, 2007 RCL - CSM Findings 9
Technical metrics
Jan. 16, 2007 RCL - CSM Findings 10
Yield metrics Line yield of a fabrication process accounts for all wafer
losses occurring up through “E-Test” (wafer acceptance
test)
Die yield of a device accounts for all wafer and die losses
occurring after E-Test. DY is reported by the participants
for the highest-volume device in each process flow.
Defect density D of a device is the equivalent Murphy-model defect
density that would account for all die yield losses:
21
AD
eDY
AD
where A is the device area and DY is the reported die yield.
The integrated yield of a fab process accounts for all line
yield and die yield losses
Jan. 16, 2007 RCL - CSM Findings 11
The “Berkeley metrics”
Line yield per 20 mask layers (LY20)
Defect density (die yield plugged into Murphy Model) (D)
Integrated yield (line yield times die yield) (IY)
Throughput of photolithography equipment (wafers processed
per “stepper” per day) (STP)
Integrated stepper throughput (ISTP = IY*STP)
Direct labor productivity (wafer layers per operator per day)
(DLP) and total labor productivity (wafer layers per headcount
per day) (TLP)
Cycle time per mask layer (CTPL)
Process development and qualification time (VT)
Time to ramp to mature die yield (RT)
Jan. 16, 2007 RCL - CSM Findings 12
Line Yield
70
75
80
85
90
95
100
95 96 97 98 99 00 01Time
Lin
e y
ield
pe
r 2
0 la
ye
rs (
pe
rce
nt)
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
5
Jan. 16, 2007 RCL - CSM Findings 13
CMOS Logic Device Defect Density0.45 - 0.6 micron CMOS process flows
0.01
0.10
1.00
10.00
95 96 97 98 99 00
Time
De
fec
t D
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
)
M2
M3
M6
M7
Jan. 16, 2007 RCL - CSM Findings 14
CMOS Logic Device Defect Density 0.35 - 0.4 micron CMOS process flows
0.1
1
10
96 97 98 99 00 01
Time
De
fec
t d
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
)
M2
M3
M4
M7
M10
Jan. 16, 2007 RCL - CSM Findings 15
CMOS Logic Device Defect Density 0.25 micron CMOS process flows
0.1
1
10
98 99 00 01
Time
De
fec
t D
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
) M3
M9
M10
Jan. 16, 2007 RCL - CSM Findings 16
Memory Device Defect Density (after repair)0.45 - 0.5 micron CMOS process flows
0.1
1
10
95 96 97 98 99 00Time
De
fec
t D
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
) M2
M3
M5
M8
Jan. 16, 2007 RCL - CSM Findings 17
Memory Device Defect Density (after repair)0.33 - 0.4 micron CMOS process flows
0.01
0.1
1
10
95 96 97 98 99 00 01Time
De
fec
t d
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
)
M1
M2
M3
M4
M5
M8
Jan. 16, 2007 RCL - CSM Findings 18
Memory Device Defect Density (after repair)0.25 - 0.29 micron CMOS process flows
0.01
0.1
1
10
97 98 99 00 01Time
De
fec
t d
en
sit
y (
fata
l d
efe
cts
pe
r s
qu
are
cm
)
M1
M3
M5
M8
Jan. 16, 2007 RCL - CSM Findings 19
CMOS Logic Device integrated Yield0.45 - 0.6 micronCMOS process flows
30
40
50
60
70
80
90
100
95 96 97 98 99 00Time
Inte
gra
ted
Yie
ld
M2
M3
M6
M7
Jan. 16, 2007 RCL - CSM Findings 20
CMOS Logic Device Integrated Yield0.35 - 0.4 micron CMOS process flows
20
30
40
50
60
70
80
90
100
97 98 99 00 01Time
Inte
gra
ted
Yie
ld
M2
M3
M4
M7
M10
Jan. 16, 2007 RCL - CSM Findings 21
CMOS Logic Device Integrated Yield0.25 micron CMOS process flows
20
30
40
50
60
70
80
90
100
98 99 00 01Time
Inte
gra
ted
Yie
ld
M3
M9
M10
Jan. 16, 2007 RCL - CSM Findings 22
Memory Device Integrated Yield 0.45 - 0.5 micron CMOS process flows
20
30
40
50
60
70
80
90
100
95 96 97 98 99 00
Time
Inte
gra
ted
Yie
ld (
aft
er
rep
air
)
M2
M3
M5
M8
Jan. 16, 2007 RCL - CSM Findings 23
Memory Device Integrated Yield0.33 - 0.4 micron CMOS process flows
20
30
40
50
60
70
80
90
100
96 97 98 99 00 01
Time
Inte
gra
ted
Yie
ld (
aft
er
rep
air
)
M1
M2
M3
M4
M5
M8
Jan. 16, 2007 RCL - CSM Findings 24
Memory Device Integrated Yield0.25 - 0.29 micron CMOS process flows
20
30
40
50
60
70
80
90
100
97 98 99 00 01
Time
Inte
gra
ted
Yie
ld (
aft
er
rep
air
)
M1
M3
M5
M8
Jan. 16, 2007 RCL - CSM Findings 25
I-Line 5X Stepper Productivity
0
100
200
300
400
500
600
700
800
900
1000
1100
94 95 96 97 98 99 00 01
Time
Wa
fer
op
era
tio
ns
pe
r s
tep
pe
r p
er
da
y
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 26
DUV Stepper Productivity
0
100
200
300
400
500
600
700
800
900
1000
1100
97 98 99 00 01
Time
Wa
fer
op
era
tio
ns
pe
r s
tep
pe
r p
er
da
y
M3
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 27
Stepper Productivity (all types of steppers)
0
100
200
300
400
500
600
700
800
900
1000
1100
95 96 97 98 99 00 01
Time
Wa
fer
op
era
tio
ns
pe
r s
tep
pe
r p
er
da
y
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 28
Integrated Stepper Throughput
0
100
200
300
400
500
600
700
800
900
95 96 97 98 99 00 01
Time
Eq
uiv
. fu
ll w
afe
r o
pe
rati
on
s p
er
ste
pp
er
pe
r d
ay
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 29
Space Productivity
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
95 96 97 98 99 00 01Time
Ma
sk
la
ye
rs p
er
sq
ft
pe
r d
ay
M1
M2
M3
M4
M5
M6
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 30
Direct Labor Productivity
0
10
20
30
40
50
60
70
80
90
95 96 97 98 99 00 01Time
Ma
sk
la
ye
rs p
er
dir
ec
t la
bo
r p
er
da
y
M1
M2
M3M4
M5
M6
M7M8
M9
M105
Jan. 16, 2007 RCL - CSM Findings 31
Total Labor Productivity
0
5
10
15
20
25
30
35
40
45
50
95 96 97 98 99 00 01
Time
Ma
sk
la
ye
rs p
er
tota
l la
bo
r p
er
da
y
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 32
Cycle Time Per Layer
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
95 96 97 98 99 00 01Time
Cy
cle
tim
e p
er
lay
er
(da
ys
)
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Jan. 16, 2007 RCL - CSM Findings 33
Benchmark vs. average scores
for speed metrics
Process development time = 4 months vs. 7 months for
similar process, 7 months vs. 12 months for very new
process
Yield ramp time = 7 months vs. 12 months (for
technology introduced 1 year after leader introduced it)
Manufacturing cycle time per mask layer (CTPL) = 1.4
days vs. 2.3 days for both logic and memory (at high
volume)
Jan. 16, 2007 RCL - CSM Findings 34
Yield trends
Contamination (defects) is a major yield
limiter for multi-level metal products
Losses from systematic mechanisms are larger
than defect losses for many products,
especially memory devices
Ill-formed structures (leakage, overlay, etc.)
Edge losses
Jan. 16, 2007 RCL - CSM Findings 35
Example Die Loss Pareto (SRAM)
P+ S/D
into N+
base
Core
leakage
M2
defects
60
43
30
P+ S/D
Mask
rounding
11 10
M2
fuses
Exposure
energy change
Mask
changes
Jan. 16, 2007 RCL - CSM Findings 36
Performance trends
With some important exceptions, we find more
closure in mature yields achieved by the
participants than in previous phases of CSM
The speed-related metrics, i.e., process
development time, yield ramp time, cycle time, are
major discriminators of performance
Equipment and labor productivity also are major
discriminators
Jan. 16, 2007 RCL - CSM Findings 37
Trade-offs between metrics
It seems increasingly difficult to sustain a
stable process in advanced digital
technologies
Process engineers face many trade-offs
between yield, wafer throughput and cycle
time
Jan. 16, 2007 RCL - CSM Findings 38
Trade-offs (cont.)
Case-study example: photo-limited yields
for advanced memory devices
Multiple poly layers for which perfect
alignment is quite difficult
Constrained use of steppers is a common
strategy
Jan. 16, 2007 RCL - CSM Findings 39
Alternative photo strategies
Fab M4: must use exactly same stepper at all three
critical layers
Fab M2: no restriction on stepper selection
Fab M1: given the selection of stepper at first
layer, restrict choice of stepper at layers 5 and 9 to
three particular machines
Jan. 16, 2007 RCL - CSM Findings 40
3-D performance plots
Yield axis: we plot integrated yield, IYD =
(LY20)(Murphy die yield for 0.5 sq cm device)
Wafer throughput axis: we plot a normalized
stepper throughput, STP = (daily t-put)/1000
Cycle time axis: we plot a normalized reciprocal
of cycle time, CT = 1.2/(CTPL)
Jan. 16, 2007 RCL - CSM Findings 41
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
CT
IYDSTP
M4
M1
M2
2Q98 performance
Jan. 16, 2007 RCL - CSM Findings 42
Economic interpretation
The CSM program developed spreadsheet models to
compute changes in wafer cost and revenue per wafer
as a function of changes in manufacturing speed or
efficiency
Jan. 16, 2007 RCL - CSM Findings 43
Economic interpretation (cont.)
Analyze performance differences in the speed metrics
(process development time, yield ramp time,
manufacturing cycle time) and equipment productivity
Apply average and benchmark scores to greenfield fab
running the Sematech 250nm 5-metal logic process at
25,000 wafers per month over 5 years
Assume revenue per 100%-yielding wafer is $10,000
at time 0 and going down 25% per year
Jan. 16, 2007 RCL - CSM Findings 44
Economic interpretation (cont.)
Metric Average Benchmark
Development time 360 days 210 days
Yield ramp time 360 days 210 days
Cycle time per layer 2.2 days 1.5 days
DUV OEE 42% 58%
I Line OEE 67% 85%
Dry etch OEE 43% 80%
HE Implant OEE 48% 69%
Jan. 16, 2007 RCL - CSM Findings 45
Economic comparison
Average Benchmark Diff.
performance performance
Cost per wafer $1,479 $1,214 $265 (19%)
Revenue per wafer $3,753 $4,317 $564 (15%)
Differences in manufacturing speed seem twice as
significant economically as differences in
manufacturing efficiency
Jan. 16, 2007 RCL - CSM Findings 46
Six basic themes for best practices
Automate information handling and make
manufacturing mistake-proof
Collect detailed process, equipment and test
data, integrate the data and analyze it
statistically
Wisely manage development and
introduction of new process technology
Jan. 16, 2007 RCL - CSM Findings 47
Six key practices (cont.)
Reduce lost time and process time on
steppers and other bottleneck equipment
Implement intelligent scheduling and WIP
management
Reduce division of labor, up-skill the
workforce, develop a problem-solving
organization
Jan. 16, 2007 RCL - CSM Findings 48
Automation of information
handling
100% auto-recipe download
100% auto-WIP tracking
100% auto-metrology upload
Fully automated and interlocked statistical
process control (SPC)
Automated process control
Jan. 16, 2007 RCL - CSM Findings 49
Automated process control
Examples of feedback control:
Auto-adjust photo alignment offsets based on CD
measurement
Example of feed-forward control:
Adjust etch recipe or choose etcher based on
photo CDs
Jan. 16, 2007 RCL - CSM Findings 50
Data integration and analysis
Integrated yield analysis database fitted
with convenient and powerful statistical tools
Complete audit trail of product, process and
equipment in one database
Analysis carried through to identify root cause
and prove out the fix
Extensive in-line defect monitoring
correlate with die yield, classify signatures
Jan. 16, 2007 RCL - CSM Findings 51
Managing process development
and transfer
Control the number of simultaneous
engineering variables:
Staggered introductions of new processes, devices
and wafer sizes
Steady rate of introduction of new process
modules in each generation
Jan. 16, 2007 RCL - CSM Findings 52
Managing process development
and transfer (cont.)
Minimize complexity of hand-off
“Copy exactly” policy:
identical equipment sets and recipes (ideally, same fab)
identical CIM systems
Concurrent engineering in same fab line:
regular manufacturing system handles all processing
for development
Jan. 16, 2007 RCL - CSM Findings 53
Equipment efficiency improvement
Software permitting different recipes to be
“cascaded” through equipment
Auto-feedback control to eliminate test wafers
and send-aheads
Review machine event logs to discover hidden
losses in machine cycles
SPC-type alarms for inferior equipment speed
TPM teams for improved machine design,
operation and maintenance
Jan. 16, 2007 RCL - CSM Findings 54
Scheduling and WIP management
Fab-out targets established and fab-ins
scheduled according to current capacity and
current WIP
Intelligent detailed, on-line scheduling based
on analysis of downstream WIP situation and
intelligent production targets
Jan. 16, 2007 RCL - CSM Findings 55
WIP
EtchThin
Films
Diffusion Photo
Fab In Fab Out
Input control
•Control fab
in according
to out schedule,
WIP and capy
Non-bottleneck
schedulers
•Schedule equip-
ment to complete
targets and prevent
steppers from starving
Bottleneck
scheduler
•Schedule steppers
to complete targets and
to maximize utilization
Output planner
•Identify
bottlenecks
and schedule
target fab out
according to
WIP level and
stepper capacity
Planning and Scheduling Target setting
• Target cycle times,
target WIP, target
production
Jan. 16, 2007 RCL - CSM Findings 56
Up-skilling the work force
TQM or TPM teams of operators and
technicians supported by engineers
Upgrade operator into “Self-sustaining
technician” or “Self-help lady”
Upgrade technician into “Equipment owner”
or “Key man”
Jan. 16, 2007 RCL - CSM Findings 57
Reduced division of labor
Merging of manufacturing and equipment
maintenance groups
Reduced division of labor between
engineering groups
Joint equipment and process engineering
Yield analysis carried out by process engineers, or
root-cause determination by yield engineers
Jan. 16, 2007 RCL - CSM Findings 58
Some conclusions
We found major differences in technical
performance.
Trade-offs between various metrics were
optimized differently among the participants.
Nonetheless, fast ramp-up of production
processes to high yield and high throughput
while driving down cycle time were basic
aims for everyone.
Jan. 16, 2007 RCL - CSM Findings 59
Some conclusions (cont.)
Fast improvement depends on rapid
problem identification, characterization and
solution by a large, diverse organization
Common themes of successful approaches:
Leadership and development of personnel
Organizational participation, communication,
accountability and responsibility for improvement
Information strategy and analytical techniques that
accelerate improvement