COMPASS - Solutions to Multiple Probing Challenges for Test...

© imec/2019 – Erik Jan Marinissen et al. – COMPASS’19, Munich, Germany – Nov 14, 2019 – PUBLIC 1

Solutions to Multiple Probing Challengesfor Test Access to Multi-Die Stacked ICs

Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchiimec – Leuven, Belgium

Yu-Rong Jian, Cheng-Wen WuNTHU – Hsinchu, Taiwan

Jörg Kiesewetter, Ken SmithFormFactor – Thiendorf, Germany; Beaverton, OR, USA


CMOS Scaling...

CMOS Scaling ContinuesBut requires increasing investmentsOnly few companies can afford this... And one day, it will stop!

1. INTRODUCTION

22

First EUV stepperworld-wide in use at imec


Baton Pick-Up by Innovations inMulti-Die Stack-Assembly

Package-on-Package / Die-on-DieSide-by-side and vertical stackingMicro-bumps, TSVs; wafer thinning

Advanced PackagingFlip-chip, Through-Package Via (TPV)Redistribution layersIntegrated passives and interposersWafer-level fan-out and packaging

1. INTRODUCTION

CMOS Scaling... ...Assembly & Packaging


1. INTRODUCTION

Testing of Multi-Die Stacks

Test Stages1. Pre-Bond Test : prior to stacking2. Mid-Bond Test : incomplete, partial stacks3. Post-Bond Test : complete stacks, prior to packaging4. Final Test : complete, packaged stack

Test Flow OptimizationToo much vs. too late testingOptimization with 3D-COSTAR: http://www.ce.ewi.tudelft.nl/3dcostar

Test AccessInternal: 3D-DfT (e.g. IEEE Std 1838™-2019)

probe technology

test socket

External Test Access

and External: probing + socket


1. INTRODUCTION

‘Vortex-2’: FormFactor CM300 Dual Config Station

ManipulatorDocking interface

Adapted CM300 probe station with thermal control

Parametric & functional

Micro-bump probingwith ultra-wide switch STS T2


Presentation Outline

1. Introduction2. Probing on Large Tape Frames3. Probing on Ultra-Thin Wafers on Tape4. Probing Singulated Die (Stacks) on Tape5. Probing Dense Arrays of Micro-Bumps6. PTPA Accuracy Assessment7. Case Study8. Conclusion

SOLUTIONS TO MULTIPLE PROBING CHALLENGES FOR TEST ACCESS TO MULTI-DIE STACKED ICs

Challenges and Solutions


Multi-Die Stack-Assembly Flows use Tape FramesTape Frame Serve as Temporary Carrier for

Diced wafersUltra-thin wafersPick-n-placed dies and die stacks [Marinissen et al. – ITC’15]

Tape Frame SpecificationsLarger than the wafer it must holdSEMI Standard G74-0669:

Inner diameter : 350mmOuter diameter : 400mmWidth across flat : 380mm

2. PROBING ON LARGE TAPE FRAMES


FormFactor CM300 Handles Large Tape Frames2. PROBING ON LARGE TAPE FRAMES

Adapted chuck for manual loading through front-port of SEMI Std G74-0699 tape frames

Extra maneuver space for chuckChuck camera away from chuckExtra support bars for large frames


Multi-Die Stacks use (Ultra-)Thin WafersWafer Thinning down to

200µm: to fit stack in package cavity50µm: to expose TSVs

Ultra-Thin Wafers Sag, Bend, and CurlRequire mechanical support

Carrier wafer: silicon, glassFrame with UV-curable dicing tape

Temporary bonding debondingProbing Challenge

Probing on flexible ultra-thin wafer on flexible/stretchable dicing tape

3. PROBING ON ULTRA-THIN WAFERS ON TAPE

Micro-bumps

Flip-chip bumps

Package balls

TSVs

Top die

Bottom die

Packagesubstrate

TSV50µm


Probing Requires Probe Force on Probe TargetObjective 1: good electrical contact

Measure: contact resistance RC

Wafer chuck over-travelConsequence: probe mark

Probe Mark Determined byMetallurgy of probe target Probe concept: cantilever, vertical, MEMSProbe tip: metallurgy, shapeChuck over-travel


Objective 2: minimal impact probe markon other function(s) of probe target

Measure: probe mark areaas percentage of probe target area


Cantilever probe card (right)Bulldozer trace ≥25µm

Vertical probe card (left)Smaller probe mark

Probe Technologies and their Probe Marks

12


Cant

ileve

rPy

ram

id®

RBI

Al pad

Al pad

16µm

Cu µbump

25µm

Pyra

mid

®


Singulated Die (Stacks) on Tape: ApplicationsDiced (and Thinned) Wafers

Pre-bond test of D2D or D2W stacksTest after dicing also covers dicing defects

Singulated D2W/W2W StacksMid-bond test of partial stacksPost-bond test before packaging

4. PROBING SINGULATED DIE (STACKS) ON TAPE






Center of wafer chuckRim of wafer chuck






Pick-n-Placed D2D StacksPnP in matrix on carrier, e.g. tape frameAllow automated testing through index stepping







Θ=1.8°







⇒ Tape Stretch

⇒ Tape Stretch

⇒ PnP Inaccuracy

Challenges


Automated Misalignment Correction by Prober

Probe Station’s Job: Land Probes on Probe TargetsRegular wafers: stepping with fixed index sizesSingulated die (stacks) on tape: misalignments in x, y, z, and θ

FormFactor CM300 Prober Can Auto-Correct MisalignmentsAlignChip: per die correction of x, y, z, and θ

Requires alignment marks in FoVθ compensation limited to ~2°

PreMapWafer: record all misalignments onsingle trip to Platen Camera; saves 13s/trip


PlatenCamera

ProbePosition

Platen Camera


Direct Micro-Bump ProbingFunctional interconnects between 3D-stacked dies areimplemented by large arrays of fine-pitch micro-bumps

5. PROBING DENSE ARRAYS OF MICRO-BUMPS

Impossible to probe with conventional probe technologyCantilever probes : cannot form arbitrary arrays

probe mark too largeVertical probes : cannot handle the fine pitch

Options for pre-bond test1. Skip pre-bond test: poor compound stack yield; higher cost2. Dedicated pre-bond probe pads: extra design, area, test time,

post-bond load; and micro-bumps remain untested3. Use advanced probe technology to probe micro-bumps

[Sam

sung

, ISS

CC’1

1][X

ilinx

, 3D-

TEST

’12]micro-bumps

CantileverProbe

VerticalProbe


What Do We Want To Probe?Micro-Bump Probe Targets

imec’s PoR @40µm pitchToday’s advanced industry practice

Wide-I/O Micro-Bump ArraysWIO1: 1,200 micro-bumps @50/40µm pitch

WIO2: 1,752 micro-bumps @40µm pitch

HBM2: 4,258 micro-bumps @55µm pitch

5. PROBING DENSE ARRAYS OF MICRO-BUMPS

Ø15µm Cu/Ni/SnØ25µm Cu/NiB

5300µm

560µ

m

2 rows

6 cols

6800µm

560µ

m

2 rows

24 columns

HBM2


FormFactor Pyramid® Probes RBI5. PROBING DENSE ARRAYS OF MICRO-BUMPS

Modular: card + core + tip couponCore: frame with two thin-film membranes:(1) tip layer; (2) routing layer

Tip coupon is replaceableVertical MEMS-Type Probes

Tips: 6×6µm2, 6×1µm2 probe markFull-arrays down to 20µm pitchLitho-defined: perfect pitch(but membrane can stretch)

R&D, not (yet) a catalogue product@imec: WIO1 and WIO2

Core-I/Os

Probe tips

[Marinissen et al. – ITC Asia’17]


Probe-To-Pad Alignment (PTPA) Accuracy

PTPA Accuracy Assessment Procedure1. Train probe card on station

Define home die; main alignment BL2. Probe all micro-bump arrays on wafer3. SEM images of corners of probed arrays4. Measure for each micro-bump:

Bump : center (𝑥𝑥𝑚𝑚𝑚𝑚,𝑦𝑦𝑚𝑚𝑚𝑚), area 𝑎𝑎𝑚𝑚𝑚𝑚Mark : center (𝑥𝑥𝑝𝑝𝑚𝑚, 𝑦𝑦𝑝𝑝𝑚𝑚), area 𝑎𝑎𝑝𝑝𝑚𝑚

5. Calculate misalignment 𝑚𝑚 = (𝑥𝑥𝑝𝑝𝑝𝑝 −𝑥𝑥𝑝𝑝𝑚𝑚,𝑦𝑦𝑝𝑝𝑝𝑝 −𝑦𝑦𝑝𝑝𝑚𝑚)and relative probe-mark area 𝑎𝑎 = ⁄𝑎𝑎𝑝𝑝𝑝𝑝 𝑎𝑎𝑝𝑝𝑚𝑚

6. PTPA ACCURACY ASSESSMENT

Misalignment vector 𝑚𝑚 (µm)Relative probe-mark area 𝑎𝑎 (%)


Automatic Probe-Mark Analysis

One SEM Shot: Three ImagesImage sharpeningEdge detection

Micro-Bump Contour: Image 1⇒ center + areaProbe Mark Contour: Images 2+3⇒ center + areaSoftware Tool Also Handles

Top-view vs. tilted viewNo or multiple probe marks

6. PTPA ACCURACY ASSESSMENT

[Rong et al. – SWTW’18]SEM Image 1 SEM Image 2 SEM Image 3


Regular Calibration of the ‘Compensation Matrix’ is requiredSoftware compensation for small mechanical misalignments between(1) probe and (2) platen positions

Thermal Control to avoid radial wafer expansion

1. Probe-Station AccuracyMisalignment of BL corner per die d:

𝑚𝑚𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑 = 𝑚𝑚(𝐵𝐵𝐵𝐵𝑑𝑑)Chuck-position dependent Alignment error wafer map

Separating PTPA Accuracy Contributions: Station6. PTPA ACCURACY ASSESSMENT

PTPA @T=32ºCAfter calibration

PTPA @T=22ºCAfter calibration

PTPA @T=22ºCBefore calibration

BL

TLTL

BRBR

TR

TR


2. Probe-Card AccuracyErrors on other corners due to cardTranslate misalignments for die d,corner c ∈ {𝐵𝐵𝐵𝐵,𝐵𝐵𝐵𝐵,𝑇𝑇𝐵𝐵,𝑇𝑇𝐵𝐵}:

𝑚𝑚𝑐𝑐𝑠𝑠𝑐𝑐𝑑𝑑 𝑐𝑐 = 𝑚𝑚 𝑐𝑐𝑑𝑑 −𝑚𝑚(𝐵𝐵𝐵𝐵𝑑𝑑)

Separating PTPA Accuracy Contributions: Card6. PTPA ACCURACY ASSESSMENT

Cornerc

Ideal (µm) Actual (µm) Error (µm) Relative Error

( xmb , ymb) ( xpm , ypm) m(c) x y

BL ( 0, 0) ( 0.00, 0.00) ( 0.00, 0.00) 0.00% 0.00%

BR (2880, 0) (2879.47, -0.12) (-0.53, -0.12) -0.02% +0.06%

TR (2880, 200) (2879.61, 200.88) (-0.39, 0.88) -0.01% +0.44%

TL ( 0, 200) ( 1.33, 200.71) (1.33, 0.71) -0.05% +0.35%

TLTL

BRBR

TR

TR

BL

WIO2-1Bank


Example: TPV Die Design: 2.0×8.0mm2

Dense low-cost vertical interconnectWide-I/O2: 1,752× bumps @40μm pitch

Technology:TSVs: Cu, ∅5μm×50μm highFront-side RDL: Cu, micro-bumps ∅25μm×5μm Back-side RDL: Cu, interconnects 5μm×5μm

Manufacturing at imecReticle with 10 diesØ300mm wafers, 3260 dies

7. CASE STUDY


TPV Pre-Bond Test Involves All Challenges

Probing Challenges Addressed in Conjunction1. Probing on large tape frames SEMI Std G74-06692. Probing on ultra-thin wafers on tape 50μm thickness (due to TSV)3. Probing dense arrays of micro-bumps WIO2; 1,752 bumps @40μm4. PTPA accuracy assessment Used automatic analysis software5. Probing singulated dies on tape 3,260 diced dies, ∅300mm wafer

Reported ResultsAutomated misalignment corrections in θ and x, yProbe marks and electrical results

7. CASE STUDY


Automated Misalignment Correction by Prober

Rotation θMost die: θ = -0.497° (manual loading)6.4% outliers: θ∈[-0.637°...-0.361°]

Translation x,yLarge deviations (>500μm) from index position

Most dies follow stretch forces of dicing tapeSame outlier dies require large translationsin opposite directions

Significant Chuck Travel Time Reduction‘PreMapWafer’ saved 3260× 13s ≈ 700 min.

7. CASE STUDY

MisalignmentAvg. Max.

θ -0.497º -0.637ºx 116µm 351µmy 232µm 576µm

-0.497

-0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497

-0.611 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.605 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.604 -0.599 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.604 -0.597 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.603 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.607 -0.602 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.606 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.597 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.637

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.361

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.599

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.598

-0.396 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.387 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.375 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.392 -0.497 -0.497 -0.497 -0.497 -0.497

-0.375 -0.497 -0.497 -0.497 -0.497 -0.497 -0.497

-0.497 -0.497 -0.497 -0.497 -0.497

-0.396 -0.497 -0.497 -0.497 -0.497

-0.497

notch


Electrical Results and Probe Marks7. CASE STUDY

Die

17_6

MAX=

261.8

MAX=

160.4

Bank

B

MIN=

31.2

Bank

C

MIN=

29.8

31.2

37.6

073

35.1

29.8

073

37.6

42.7

40.9

40.9

42.9

42.7

44.1

44.1

44.2

44.2

43.4

070

160.4

40.6

40.6

070

124.0

124.0

43.4

160.4

44.8

44.8

44.8

44.8

44.4

44.5

41.8

41.8

56.8

56.8

44.4

44.5

44.4

44.4

183.5

183.5

44.6

39.6

42.0

42.0

44.6

39.6

42.4

42.4

43.8

39.1

51.4

51.4

43.5

43.5

44.6

37.3

46.1

46.1

44.5

44.5

44.6

37.3

39.1

39.1

59.7

59.7

44.7

39.7

46.8

46.8

158.5

158.5

44.7

060

39.7

37.8

37.8

060

52.1

52.1

45.6

39.3

46.8

46.8

127.2

127.2

45.6

39.3

38.6

38.6

139.1

139.1

45.3

38.4

46.6

46.6

45.3

38.4

87.7

87.7

44.9

39.4

46.9

46.9

261.8

261.8

49.8

39.7

37.9

37.9

45.5

45.5

49.8

39.7

53.3

53.3

104.8

104.8

47.4

41.7

40.3

40.3

45.1

45.1

47.4

41.7

42.7

42.7

44.2

44.2

46.7

050

40.7

66.6

66.6

050

46.7

211.1

42.8

40.7

040

040

030

030

020

020

010

010

001

001

366

293

220

147

074

001

366

293

220

147

074

001

MAX=

96.2

MAX=

209.8

Bank

A

MIN=

31.8

Bank

D

MIN=

29.7

31.8

38.9

073

34.3

29.7

073

38.9

42.1

39.0

39.0

43.1

42.1

43.8

43.8

73.1

73.1

44.3

070

42.7

39.6

39.6

070

42.2

42.2

44.3

42.7

45.0

45.0

44.5

44.5

44.6

44.6

42.6

42.6

43.3

43.3

44.6

44.6

44.7

44.7

96.2

96.2

44.8

39.5

42.6

42.6

44.8

39.5

43.5

43.5

44.5

38.3

70.7

70.7

42.9

42.9

45.4

36.3

45.8

45.8

43.5

43.5

45.4

36.3

55.3

55.3

43.6

43.6

45.3

40.2

157.8

157.8

43.4

43.4

45.3

060

40.2

106.5

106.5

060

44.8

44.8

45.8

39.2

46.4

46.4

42.5

42.5

45.8

39.2

43.9

43.9

44.6

44.6

44.4

39.4

62.9

62.9

44.4

39.4

45.9

45.9

45.2

39.9

47.2

47.2

45.3

45.3

43.9

39.7

209.8

209.8

45.8

45.8

43.9

39.7

43.9

43.9

43.3

43.3

48.0

41.6

40.1

40.1

44.3

44.3

48.0

41.6

43.5

43.5

43.1

43.1

45.7

050

49.5

120.6

120.6

050

45.7

90.3

43.9

49.5

040

040

030

030

020

020

010

010

001

001

366

293

220

147

074

001

366

293

220

147

074

001

205

183 171 107 1242 115

221 195 112 98 567

1510 154 186 140 86 834 123

54 171 203 121 140 141 119

1619 165 194 167 233 117 145 350 106

1293 115 244 188 164 137 188 279 109

43 171 230 183 168 162 178 127 124

230 53 155 216 231 193 135 174 88 130

263 119 204 164 210 125 188 164 144 147 113

369 137 124 203 189 240 140 2000 82 106 162

176 149 158 205 152 190 158 197 93 171 173

167 164 213 184 174 157 167 192 114 111 194

184 171 150 148 96 184 124 242 80 138 172

1325 152 128 142 137 142 156 107 180 116 157 193 68

1189 118 155 135 197 204 104 102 174 127 142 199 172

762 132 111 154 185 185 103 73 156 112 147 150 204

791 169 117 158 169 204 47 97 189 124 101 149 154

1068 188 165 149 185 214 153 127 152 123 183 138 108

75 169 126 192 158 221 145 128 229 157 193 163 114

167 129 182 168 180 224 180 173 127 111 139 62

187 95 192 157 206 180 151 118 137 211 160

138 182 174 187 213 184 179 143 127 142 153

111 130 158 136 191 198 174 121 119 218 130

124 111 116 144 208 157 177 229 187 213 300

154 131 161 169 205 117 162 162 147 168 171

1056 97 126 147 170 177 114 164 151 193 127

881 128 170 192 180 190 159 143 170

1463 138 133 221 164 195 125 277 352

189 227 155 202 161 131 158 264 125

688 86 163 142 206 138 234

185 322 991 194 138 213 118

189 523 197 426 286

217 682 176 304 132

119

notch

NaN

NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN

15.7 NaN NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN NaN NaN

18.5 NaN NaN NaN NaN NaN NaN NaN NaN

130.7 NaN NaN NaN NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN NaN NaN 27.2 NaN NaN NaN




NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN






NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN












NaN NaN NaN NaN NaN

NaN NaN NaN NaN NaN

NaN

notch

Wafer Map:FS-Short Test on Bank A

Wafer Map:NC-Open Tests

Probe Map for an Individual Die: FS-Short

TPV Front-Side: Ø25µm Cu

Probe Marks:Arbitrary (probed) array


A ‘Toolbox’ for Probing Challenges in (3D-)TestChallenges Solutions1. Probing on large tape frames Adapted probe station2. Probing on ultra-thin wafers on tape Low-force probe cards3. Probing dense arrays of micro-bumps Advanced probe cards + stations4. PTPA accuracy assessment Automatic analysis software5. Probing singulated die (stacks) on tape Auto-correction by prober software

These solutions can be used stand-alone or in conjunction with each otherTPV case study demonstrated successful results with all solutions together

Contribution to productization of multi-die stacksFull paper: Marinissen et al. – ITC’18 – DOI: 10.1109/TEST.2018.8624731

8. CONCLUSION


Acknowledgments

Part of the work of Erik Jan Marinissen, Ferenc Fodor and Jörg Kiesewetter was performed in the project SEA4KET,Semiconductor Equipment Assessment for Key-Enabling Technologies (http://www.sea4ket.eu), sub-project 3DIMS,3D Integrated Measurement System;this project received funding from the European Union’s Seventh Programme forresearch, technological development, and demonstration under grant agreement No. IST-611332

Yu-Rong Jian’s internship at imec in Leuven, Belgium was financially supported by the Ministry of Education of Taiwan

We also acknowledge the EMPIR 14IND07-3D Stack project

Gerald Beyer, Eric Beyne, Miroslav Cupak, Deepak Dahiya,Bart De Wachter, Kristof Croes, Luc Halipre, Veerle Simons,John Slabbekoorn, Geert Van der Plas, and Tomas Webers

Mario Berg, Jens Fiedler, and Eric Hill

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