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Comparator Power Minimization Analysis for SAR 

ADC Using Multiple ComparatorsMuhammad Ahmadi , Member, IEEE , and Won Namgoong , Senior Member, IEEE 

 Abstract— Comparator power consumption is a major bot-tleneck to the power efficiency of a high resolution successiveapproximation register (SAR) analog-to-digital converter (ADC)used in low-power applications. This paper analyzes theoreticallythe optimal comparators that need to be used to achieve a desiredoverall performance at minimum power levels. A simple andaccurate mathematical model of the SAR ADC that is amenable toanalysis is first presented. The mathematical formulation suggeststhat the comparison power allocated to each bit step need not bethe same. The optimization problem, therefore, is solved so thatthe comparator power budget is optimally distributed amongall bit steps. Simulation results show that up to 50% and 60%power savings can be achieved when 10 and 12 comparators areemployed for 10 b and 12 b SAR ADCs, respectively. To reduce the

implementation complexity, comparator noise allocation problemis also solved when fewer than comparators are employed in an-bit SAR ADC. Simulation results suggest that two comparators

is sufficient to achieve near ideal performance in 10 b and 12 bSAR ADCs.

 Index Terms— Comparator noise analysis, comparator power,

low power ADC, successive approximation register analog-to-dig-ital converter (SAR ADC).

I. I NTRODUCTION

W IRELESS sensor nodes require analog-to-digital con-verters (ADC) to digitize environmental conditions

such as temperature, pressure, and/or sound. Low power op-eration is vital for wireless sensor nodes that are powered by

 batteries or energy harvesting sources   [1]. Energy harvester usually provides low output voltage with limited power which

 places an energy constraint on the sensor node. The sensor front-end, therefore, requires ultra low power ADCs. Chargeredistribution successive approximation register (SAR) ADChas been a popular candidate in sensor node applications dueto its simplicity, low power consumption, medium speed, andresolution [2]– [4].

The three primary components of a SAR ADC are thedigital-to-analog converter (DAC), digital SAR logic, andcomparator. The power consumption of the DAC can be greatlyminimized by employing a small unit capacitor   [5]–[7]   anddigital circuits benefit from technology scaling. Consequently,

the comparator has become a major source of power consump-tion in recent power efficient SAR ADCs [7]–[9]. For example,the comparator consumes 60% of the total power of the ADC

Manuscript received February 11, 2015; revised May 21, 2015 and nulldate;

accepted June 29, 2015. This work was supported in part by the National Sci-ence Foundation (NSF) under Contract ECCS1310279. This paper was recom-

mended by Associate Editor A. M. A. Ali.The authors are with the Department of Electrical Engineering, University of 

Texas at Dallas, Dallas, TX 78712 USA (e-mail: muhammad.ahmadi@student.utdallas.edu; namgoong@utdallas.edu).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2015.2466831

reported in  [9]. Low-noise comparator can be used but at theexpense of increased power dissipation, since the comparator input-referred thermal noise variance is approximately in-versely proportional to the comparator power consumption.

This paper develops an accurate and simple model to ana-lyze the effect of comparator noise on ADC output error. Our mathematical analysis suggests that the comparator noise vari-ance need not be same for each bit cycle as in conventionalSAR ADCs. Simulation results show that the comparator power can be reduced by 50% in a 10 b SAR ADC if the comparator 

 power is optimally allocated to each bit step according to thenoise requirement of the corresponding bit. The optimal com-

 parator noise allocation requires comparators with differentnoise variances each sequentially enabled. As comparatorswould be difficult to employ in practice, the comparator opti-mization problem is solved assuming fewer than compara-tors are employed. For example, when constrained to using twocomparators, the comparator power can be reduced by 40% in a10 b ADC compared to a conventional SAR ADC while main-taining the same overall performance.

The rest of the paper is organized as follows.  Section IIdiscusses the motivation and contributions of the paper.   Sec-tion III   formulates the effect of comparator noise on outputnoise power of the ADC. The optimum allocation of com-

 parator power for each bit position is studied in Section IV. The

optimization problem with limited number of comparators isaddressed in Section V. Finally, simulation results are presentedin Section VI and conclusions drawn in Section VII.

II. BACKGROUND AND CONTRIBUTIONS

A block diagram of a fully differential SAR ADC is shownin Fig. 1. The input is sampled at the beginning of the conver-sion and the quantization steps are generated using a DAC. The

 binary search algorithm is employed to find the quantizationstep that is closest to the input signal. SAR control logic de-termines each of the bits sequentially from MSB to LSB basedon the comparator decision. We assume that any decision error 

is caused by the comparator thermal noise. In the conventionalSAR ADC, the comparator is designed for the tightest noise re-quirement set by the LSB bit position. A minimum-step size of 

 between four to six times the RMS noise is generally necessaryto ensure that the overall ADC performance is not limited by thecomparator noise [10].

As shown in our earlier works in [11], the comparator noise performance at each bit step need not be the same, since thesignal voltage distribution at the comparator input is differentfor each bit cycle. This suggests that using the same comparator for each bit cycle is suboptimal and results in more power con-sumption than necessary. As noisier comparator corresponds tolower power, our power reduction approach is to employ higher noise/lower power comparators near the MSB bit cycles and

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Fig. 1. The block diagram of a differential SAR ADC.

lower noise/higher power comparators closer to the LSB bit cy-cles so that the overall performance is maintained while mini-mizing the total comparator power consumption.

In   [11], the variable-noise comparator is realized by per-forming a majority-vote comparison. The drawback of sucha comparator is that performing multiple votes per bit cycleresults in speed overhead, limiting its use to low-frequencyapplications. To enable faster operation, the SAR ADC canswitch among multiple comparators with different noise vari-

ances. Multiple comparators have been employed in  [12] and[13] but without a rigorous theoretical justification. This paper analyzes theoretically the optimal comparators that need to

 be used to achieve a desired overall performance at minimum power levels. Unlike in   [14], an exhaustive search of theoptimal number of votes per bit cycle cannot be used, sincethe comparator noise variance is continuous when multiplecomparators are employed. The required comparator noisevariances need to be solved analytically.

Two contributions are made in this paper. First, we proposea simple and accurate mathematical model of the SAR ADCthat is amenable to analysis. A set of closed-form equations arethen derived to determine the optimal noise allocation in each

 bit cycle for a given overall power constraint. Second, we ana-lyze the optimal comparator noise allocation when fewer than

comparators are employed. Our analysis suggests that em- ploying only two comparators achieves close to optimal perfor-mance.

III. EFFECT OF  COMPARATOR  N OISE ON  SAR ADCPERFORMANCE

 A. Comparator Noise Model 

Comparator thermal noise affects the accuracy of its decision.In the presence of noise, the comparator can be modeled as anideal comparator with an additive noise source at the input asshown in Fig. 2. Therefore, the digital output of a noisy com-

 parator, , can be expressed as [10]

(1)

where is the comparator differential input voltage and isthe input noise voltage. The comparator input referred noise ismodeled as a Gaussian random variable with mean zero andvariance . Using the cumulative distribution function (CDF)of the normal distribution, the probability of making a correctdecision for a given and can be obtained by

(2)

where the -function is defined by

(3)

Fig. 2. Comparator noise model.

Fig. 3. Probability of a making a correct decision as a function of when.

As an example, Fig. 3 shows the probability of making the cor-rect decision by the comparator as a function of the comparator input voltage when . As a numerical example, theerror probability when the input voltage is , , and is

, , and , respectively.

 B. Code Mean-Squared Error De  finition

This subsection describes the effect of comparator noise onSAR ADC performance. Consider an -bit SAR ADC with

 binary weighted capacitor array. The ADC operates by cyclingfrom the st bit cycle to the 0th bit cycle. The th bit isresolved using a comparator with input referred RMS noise of 

. Then, the comparator noise array

(4)

represents the comparator noise performance at each bitstep. Denote the sampled input signal voltage as .Assuming an ideal -bit ADC, the resulting codewordis . In the presence of  comparator thermal noise, the measured codeword is

, which is not necessarily thesame as . For a given input voltage , the code-

word error is defined by the difference between measuredand ideal codeword. In order to take into account the code-word error for all possible values of , we define the codemean-squared-error (MSE) as

(5)

where is the conditional expectation operation of given , and is the probability distribution functionof . For simplicity, code MSE is subsequently referred to asMSE.

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Fig.6. Probability distributionfunction of the comparator input at th bit cycle.

cross product terms(e.g., ) are negligiblecomparedto the linear terms (e.g., ). The second approximation is

obtained for the same reason.

 D. Code MSE Formulation

To determine the code error caused by the comparator noiseat the th bit position, the comparator input voltage is first parti-tioned into non-overlapping regions as shown in Fig. 6. The

th partition of is defined as

(9)

If the comparator makes a wrong decision in the th bit cyclewhile , the output codeword error squared is and isindependent of , assuming all other comparisons are resolvedcorrectly. This independence on the bit cycle location is illus-

trated via an example in Fig. 7 for a 3-bit ADC. In Fig. 7(a), theoutput codeword error is two for the case that the comparator makes a wrong decision when . Similarly, the code-word error is also two for the comparison error occurring when

as shown in Fig. 7(b).By incorporating the approximation in (8) and noting thecode

error squared is when , the code MSE in (7) becomes

(10)

where is the joint probability of the th com- parator input voltage being in region and a comparison error occurring in the th bit cycle. This probability can be readilycomputed using Assumption 1 that 's are approximately uni-formly distributed, i.e.,

(11)

To further simplify the MSE formulation in (10), we consider only the comparison errors that occur at the three most criticalregions (i.e., , , and ), since the error probability is lowfor large comparator input voltage values. This approximationof ignoring errors caused by comparator input voltages of 

is accurate if . As a numerical example, if ,the probability of making an incorrect comparator decision isless than 0.2% when . For a well-designed ADC withan ENOB , is less than one LSB as shown in

Fig. 7. An example of 3-bit binary weighted SAR ADC: (a) when comparator makes a wrong decision at region of bit ; (b) when comparator makes

a wrong decision at region of bit .

Section VI. Denoting , the codeMSE in (10) is approximated as

(12)

where the mean-squared error contributed by and aresummed from bit cycle and , respectively. Thisis because region does not exist for the LSB, and regiondoes not exist for the least two significant bits, since the like-

lihood of making more than one comparison error is negligible(by Assumption 2). By integrating the error probability in (11),

, , and become

(13)

(14)

(15)

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AHMADI AND NAMGOONG: COMPARATOR POWER MINIMIZATION ANALYSIS FOR SAR ADC USING MULTIPLE COMPARATOR S 5

Fig. 8. Comparing the MSE found by the approximation formula with simula-tion results.

To verify the accuracy of the code MSE formulation in(12), the operation of a 10-bit SAR ADC is simulated using

MATLAB as shown in Fig. 8 when the comparator noise vari-ances are the same in all bit cycles, i.e., .As shown in Fig. 8, the approximate MSE in (12) matches sim-ulation well for reasonable comparator noise variance values.

IV. OPTIMAL COMPARATOR  NOISE ALLOCATION

The in (13), (14), and (15) is proportional to .This suggests that when the same comparator is employed, thecontribution to the overall code MSE decreases by a factor of two for every increase in the bit cycle . Higher noise/lower 

 power comparators, therefore, can be used at higher bit cyclesand lower noise/higher power comparators at lower bit cyclesto reduce the overall comparator power consumption. In this

section, we determine the optimal comparator noise allocationin each bit cycle. Specifically, two optimization problems aresolved: 1) minimize code MSE for a given total comparator 

 power consumption; 2) minimize total comparator power for atarget code MSE.

The comparator power model employed in our analysis is based on the inverse relationship to the comparator noise vari-ance [15]. The comparator power at the th bit cycle is given by

(16)

where is the power of a comparator with RMS noisevoltage of , and is the comparator power with RMSnoise voltage equal to one LSB. The total comparator power consumption, , can then be computed by summing thecomparator power at all bit cycles:

(17)

 A. Minimize MSE Given Power Constraint 

The comparator noise at each bit step is chosen so that thecode MSE is minimized subject to a given total comparator 

 power budget, . This optimization problem can be for-mulated as

(18)

where the optimization variables are . Using the La-grange multiplier method with Lagrange variable ,

(19)

The optimum solution can be found by solving the followingequations:

(20)

By substituting (13), (14), and (15) into (19) and calculating the

 partial derivatives, the optimal values must satisfy thefollowing equations:

(21)

for ,

(22)

for , and

(23)for . As each of the equations is a func-

tion of a single variable for a fixed , the optimalcan be readily solved. Moreover, since for  

, (21), (22) and  (23) have a unique solution for a selected , which corresponds to a specific power budget.

Fig. 9 plots as a function of the optimal comparator noiseat each bit step for a 10 b ADC. The intersection points of thehorizontal line represent the optimal values for thatspecific . As an example, for a line, the optimal

values are given by

(24)

which corresponds to the total power budget of and re-sults in . By comparison, a conventional SAR  ADC consuming corresponds to employing compara-tors with the following set of values

(25)

and results in . Thus, the optimal allocation of  comparator noise power improves the code MSE by approx-imately 26% while consuming the same comparator power.

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Using (16), the corresponding comparator power allocation for  both ADCs in this example is plotted in Fig. 10.

 B. Minimize Power for MSE Constraint 

Instead of minimizing MSE for a power constraint as in  (18),we minimize power for a target MSE, i.e.,

(6)

The Lagrange function of this optimization problem is

(27)

Solving the partial derivatives of the Lagrange function withrespect to all results in the same equations as (21), (22), and(23). Thus, the optimum solution of the problem in  (18) for agiven is also the optimum solution of the problem in(26)   for a specific MSE constraint. For example, the optimalcomparator noise for the constraint of will beequivalent to (24), which results in . To achievethe same MSE using the conventional approach in which com-

 parator noise remains the same for all bit steps, comparator RMSnoise becomes , which corresponds to a total com-

 parator power of . Therefore, the optimal noise alloca-tion according to (24) results in a 51% reduction in comparator total power consumption in a 10 b SAR ADC.

The process of identifying the optimal allocation of com- parator noise discussed in this section can be summarized bythe following steps:

1) Choose an arbitrary value for .2) For the given , solve (21), (22), and (23) for the desired

ADC resolution to determine the optimal values.3) Based on from step 2), use (17)  and  (12) to calculate

and MSE, respectively.

4) If the MSE or does not satisfy the design require-ments, change the accordingly and perform another iter-ation from step 2).

V. TWO-COMPARATOR  SAR ADC

Optimal comparator noise allocation studied in Section IV is based on the assumption that the comparator noise levels can be varied at each bit cycle. To implement such a noise-pro-grammable comparator, one possible approach is to use multiplecomparators with different noise levels. This approach could re-duce the comparators' overall power consumption by approxi-mately 50% in a 10 b ADC when ten comparators with opti-mized noise performance are employed. The drawback of thisapproach is the need to calibrate the offset voltages for each of the comparators. Therefore, implementing the SAR ADC ac-cording to the optimal comparator noise allocation requires a

Fig. 9. Lagrangemultiplier as a functionof comparator noise ateachbit cycles.

Fig. 10. Comparator power allocated to each bit cycle of the SAR ADC.

complex calibration process for the comparators with poten-tially a large area overhead. Another approach is to use a ma-

 jority vote-based comparator as in [11] at the cost of increaseddelay for performing multiple votes per bit cycle. Such a com-

 parator may not be applicable for mid-to-high frequency SAR ADCs.

This section considers the comparator noise allocation problem when a limited number of resources (fewer thancomparators) are available. We first discuss the conventional

approach when one comparator is employed. The multiple-re-source allocation problem when two comparators are usedis then studied. The remaining two subsections discuss thetwo-comparator ADC performance when the input is sinusoidand the comparators suffer from offsets. The more generalcomparator noise allocation problem with comparators,where , is not addressed in this section but deferred toAppendix B.

 A. Conventional SAR ADC With One Comparator 

The conventional SAR ADC uses a single comparator with afixed noise performance so that all bit steps have the same com-

 parison noise. As the comparator power budget will be equallydistributed among all bit steps, the comparator noise allocatedto each bit position for a given can be expressed as

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TABLE IOPTIMIZATION FOR A 10  B  ADC WITH TWO COMPARATORS  WHEN ADC I NPUT IS U NIFORMLY  DISTRIBUTED

(28)

By replacing all in (12) with , the MSE in conventionalSAR ADC can be computed by

(9)

where isdefinedby the power budgetin (28). As a numericalexample, for a conventional 10 b SAR ADC with

, and the resulting MSE is 0.1854.

 B. Optimization for Two Comparators

This subsection considers the optimal noise allocation

 problem assuming two comparators are employed with inputreferred RMS noise of and . The objective is to de-termine and values and assign these two resourcesto bit positions so that the MSE is minimized subject toa given comparison power budget. The optimal allocation of comparator noise requires that is assigned to the mostsignificant bits and to the LSB steps. The MSE in(12) can be rewritten as a function of ,

, and using the following expression:

(30)

where is Kronecker delta function of and (i.e.,equals 1 if , otherwise 0). , , and are derivedfrom (13), (14), and (15), respectively, and are given by

(31)

(32)

(33)

Optimization variables , , and can be found bysolving the following optimization problem:

(34)

To solve this mixed-integer optimization problem, a simplestrategy is to employ the Lagrange multiplier method to deter-mine the optimal and values for each possible values of 

. Among them, the set of values that minimize MSE are theoptimal design variables.

Substituting (30) into (34) and finding the partial derivativesof the Lagrange function with respect to and results in

the following set of equations:

(35)

(36)

For a given power budget,  (35) and (36) are solved for all pos-sible values. The minimum MSE among all different results

 provides the optimum design variables that minimize the MSEfor a specified power constraint.

As an example, the optimization problem is solved for a 10 bSAR ADC with with uniformly distributedinput voltage. Since the ADC input is uniform, the equations(35) and (36) are used to optimize the comparator noise alloca-tion. Parameter has been varied from 1 to 9 and the problem isoptimized for each . Table I  summarizes the optimization re-sults and shows that the MSE is minimized when . Thus,the optimum comparator noise at each bit step for this specific

 power budget is given by the following vector:

(37)

To achieve the same MSE using a conventional approach,comparator RMS noise should be equal to , corre-sponding to total comparison power of . As a result,optimal comparator noise allocation when constrained to usingtwo comparators results in 42% reduction in comparator power consumption, which is close to the optimal performance dis-cussed in Section IV-B. Two comparators achieve large gains

 because the optimal comparator noise allocation monotonicallydecreases from MSB to LSB. Therefore, as a rough approxima-tion of the ideal allocation, a high-noise/low-power comparator 

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Fig. 1 1. ENOB l oss a s a function o f c omparator o ffset f or and .

can be used for MSBs and a low-noise/high- power comparator 

for the LSBs. Clearly, employing more than two comparatorsfurther improves the ADC performance. However, comparedto the conventional ADC with a single comparator, most of the performance improvement occurs when two comparatorsare employed. The use of additional comparators suffers fromdiminishing returns.

C. Sinusoidal Input Simulation

Our discussion thus far assumes that the ADC input is uni-formly distributed. The uniform input distribution assumptionenables derivation of closed-form solutions of the code MSE,which in turn allows us to com pute the optimal allocation of comparator noise for each bit cycle. The uniform input distribu-

tion assumption is reasonable, since the ADC input distributionis in general unknown in practice.ADCs are commonly characterized by applying a sinusoidal

input. When a sinusoid is applied to the proposed ADC that has been optimized assuming a uniform input distribution, the per-formance advantage compared to a conventional ADC is ap-

 proximately the same as when the input is uniformly distributed.Monte Carlo simulation shows that applying a sinusoid inputto the comparator noise allocation in  (37) results in code MSEof 0.1354, corresponding to an ENOB of 9.77 b. To achievethe same code MSE using a conventional approach, comparator RMS noise should be , corresponding to a total power consumption of . As a result, optimal comparator noiseallocation results in more than 42% power reduction when the

input voltage is a sinusoid. This improvement is approximatelythe same as when the input signal is uniformly distributed, sug-gesting that the optimization solution derived in Section V-B isequally effective for sinusoidal inputs. The proposed ADC per-formance is also analogous to the conventional SAR ADC whenthe input voltage swing is varied. For example, the ENOB de-creases by approximately 1 b when the sinusoid input amplitudeis halved.

 D. Comparator Offset Consideration

In addition to noise, practical comparators suffer from off-sets.   When multiple comparators are employed, each suffer from different offsets, which introduce nonlinearity and de-

grade the overall ADC performance. The comparator offsetrequirement is quantified by performing a Monte Carlo sim-ulation to determine the ADC ENOB for different ratios of 

Fig. 12. Total comparator power budget as a function of Lagrange multiplier.

comparator offset normalized by the comparator noise standarddeviations.   Fig. 11   shows the loss in ADC ENOB when theratio of the comparator offset and comparator noise is swept

from 0 to 2. This simulation is performed for comparator power  budget of and . For , thecomparator offset needs to be less than the comparator RMSnoise in order to ensure ENOB loss of no more than 0.1 bit. Asa general rule of thumb, the comparator offset should be keptsmaller than the comparator RMS noise to ensure that the offsetcontribution is relatively negligible.

Low offset comparison is realizable by adopting a low offsetcomparator circuit and/or employing proper offset calibrationtechniques   [16]–[22]. Many works have successfully reducedthe comparator offset to sub-mV range using body biasing tech-niques [16], [17], differential pair dynamic comparator architec-ture  [18], pre-amplifier offset storage  [19], [20], charge pump

 based calibration   [22], and internal node capacitive trimming[21]. In general, the choice of comparator architecture and cal-ibration scheme depends on several other factors including theADC resolution, supply voltage range, and area constraint.

VI. SIMULATION  R ESULTS

The optimization problems discussed in Section IV and Sec-tion V   are solved for a 10 b ADC to validate the effective-ness of the proposed approach. First, comparator noise alloca-tion has been optimized as a function of different comparison

 power budget assuming ten comparators are avail-able. By sweeping in (21), (22), and (23), the optimal com-

 parator noise at each bit step is calculated and the comparator  power budget corresponding to each is then computed. Fig. 12

shows that the comparator power budget falls in the range of -to- as changes from 0.00008-to-0.014. Fig. 13

shows the comparator noise allocated to each bit position for a given power budget. As an example, if the power budget is

in Fig. 13, the resulting optimal noise allocation is

(38)

As discussed earlier, the most significant bit positions have morerelaxed noise requirement compared to the LSB steps. For theoptimal solutions found above, in addition to the analyticallytractable MSE derived using (12), the code MSE obtained viaMonte Carlo simulation is also plotted in  Fig. 14   to validate

the accuracy of our assumptions. The approximate MSE in (12)matches simulation well for different comparator power bud-gets.

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Fig. 13. Comparator noise allocated to each bit step as a function of the com- parator power budget.

Fig. 14. MSE of the optimal solutions found by approximation formula com-

 pared to the simulation results.

The comparator noise allocation is also optimized when tworesources are available (i.e., ). By sweeping andusing (35) and (36), the optimal noise allocation is determined.Fig. 15 shows the allocated noise RMS to each comparator as afunction of the overall comparator power budget. The optimalvalue of is also annotated.

In Fig. 16, the trade-off between comparator total power and

the MSE at the output of the ADC is evaluated in three dif-ferent cases: one, two, and ten resources. Fig. 16 shows that for a given power budget, the MSE decreases as the number of re-sources increases. That is, to achieve a given MSE, conventionalADC consumes the maximum power and comparator power de-creases when the number of resources increases.

Similarly, the optimization problems are solved for 12 b SAR ADC when two and twelve comparators are available.  Fig. 17represents the percentage of savings in power consumption of the comparator for 10 b and 12 b ADCs in the case of and   , compared to the conventional single-resource ap-

 proach. For a 10 b ADC, more than 40% and 50% reductionin power consumption is achievable for two and ten resources,respectively. On the other hand, the optimal comparator noiseallocation approach results in comparator power savings of upto 60% in 12 b SAR ADC. Greater potential for power savings

Fig. 15. Comparator noise allocation in 10 b ADC using two comparators.

Fig. 16. The trade-off between power budget and MSE in a 10 b SAR ADC

when one, two, and ten resources available as comparator noise levels.

is available in high resolution SAR ADCs. The difference inMSE is small when two and 10 comparators are employed, sug-gesting that two comparators may be adequate to achieve near ideal performance.

VII. CONCLUSION

An analytically tractable model of the MSE error of theSAR ADC has been derived. Based on this model, we show

that the comparison power allocated to each bit step need not be the same,   since the voltage distribution at the comparator input is different for each bit cycle. An optimization problemis, therefore, constructed to identify the optimal distribution of the compar ator power budget among all bit steps. The accuracyof our analytical model is validated via simulation. Simulationresults confirm that up to 50% comparator power savings isachieva ble for a 10 b SAR ADC. To reduce the implementationoverhead, comparator noise allocation is also performed whenfewer than   comparators are employed in -bit SAR ADC.As an example, we show that by using only two comparators,the comparator power can be reduced by 40% in 10 b ADC,which is close to the ideal performance. The power advantageof allocating different comparator noise powers is shown to begreater in high resolution SAR ADCs. The simulation resultsfor a 12-bit ADC shows that the power reduction could be

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10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 17. Comparator power saving when comparator noise allocation is opti-mized for a 10 b and 12 b ADCs with 2 and available resources, compared

to the conventional single comparator.

as much as 50% and 60% when optimal noise allocation is performed with two and twelve comparators, respectively.

APPENDIX  AR ELATIONSHIP  BETWEEN  ENOB  AND  CODE  MSE

This appendix formulates the relationship between the codeMSE, which is used to optimize the comparator noise alloca-tion, and the widely used ADC performance metric ENOB. Thedefinition of ENOB is based on the signal-to-noise ratio (SNR)of a sinusoidal input and is given by

(39)

where is input voltage of the ADC and is theequivalent digitized output voltage. In an ideal ADC, the de-nominator in (39) is the quantization error variance of ,resulting in an ideal SNR of 

(40)

In the presence of comparator noise, in(39) is greater than and the resulting SNR is smaller than(40). Based on (39) and (40), ENOB is defined as

(41)where in has been omitted for notational simplicity.

Denote the output code of an ideal ADC as and the quan-tization error as . Then, the denominator of  (39) becomes

(42)

In the right-hand-side of the last equality in  (42), the first termis the code MSE in   (5)  scaled by , the second term is the

Fig. 18. Effective number of bit as a function of code MSE, found by simula-

tion and approximated formula.

quantization noise of the ideal ADC, which is , and thelast term is the correlation between the code and quantization

errors. A mathematical relationship between andMSE is determined empirically for a 10 b ADC because of thedifficulty in deriving analytically. Then, (42) becomes approx-imately

(43)

where and . Finally, a closed-form relation-ship between ENOB and code MSE for a 10 b ADC is formu-lated by substituting (43) into (41). A similar approach can beemployed to derive a mathematical relationship between ENOBand code MSE for different ADC resolution bits. The accuracy

of this formulation for a 10 b ADC is validated in Fig. 18.APPENDIX  B

OPTIMIZATION FOR    COMPARATORS

This appendix studies the optimal comparator noise alloca-tion problem given comparators with input referred RMSnoise of . The solution for the comparator  noise allocation to each bit step can be expressed by the fol-lowing general form:

(44)where repeats times and for  

. The objective is to determine the optimal

comparator noise levels, , and the correspondingnumber of occurrence of each comparator, , so that the

MSE is minimized for a given power budget. The constrainedoptimization problem is formulated as

(45)

where MSE is given by (12). Using an approach similar to theearlier two-comparator problem, the procedure for finding theoptimal allocation of comparators can be summarized as fol-lows:

1) Construct the optimization problem defined by   (45)   in

which and are the optimization vari-

ables.

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AHMADI AND NAMGOONG: COMPARATOR POWER MINIMIZATION ANALYSIS FOR SAR ADC USING MULTIPLE COMPARATOR S 11

2) List all possible combinations of and the cor-

responding . The total number of possible sets is

.3) Construct a Lagrangian function and find the partial deriva-

tives with respect to each .

4) For a given combination of found in step 2), solve

the optimization problem to find , then calculatethe MSE.

5) Repeat step 4) until all combinations of have been

exhausted.6) The minimum MSE found in step 5) is the minimized value

of the objective function and the corresponding

and are the optimum solutions.

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Muhammad Ahmadi   received the B.S. degree in

electrical engineering from University of Mazan-daran, Babol, Iran, in 2005, and the M.S. degree in

energy system engineering from Sharif University

of Technology, Tehran, Iran, in 2009, and the M.S.and Ph.D degrees in electrical engineering from

the University of Texas at Dallas, Richardson, TX,USA, in 2012 and 2015, respectively.

He is currently with the analog and mixed signaldesign team at Synaptics Inc., Rochester, NY, USA.

His research interests include low-power mixed

signal circuits in the area of analog-to-digital converters.

Won Namgoong   received the B.S. degree in elec-

trical engineering and computer science from theUniversity of California at Berkeley, CA, USA, in

1993, and the M.S. and Ph.D degrees in electricalengineering from Stanford University, Stanford, CA,USA, in 1995 and 1999, respectively.

He is currently a Professor of Electrical En-gineering at the University of Texas at Dallas,

Richardson, TX, USA. His research activities are insignal processing systems and RF/analog circuits.

He is particularly interested in DSP-assisted analogcircuits and systems.