Comp Blocks Dsp

7/29/2019 Comp Blocks Dsp

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EC 324:DIGITAL SIGNAL

PROCESSORS AND APPLICATIONS

Lecture 12

Computational Building Blocks of DSP


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15/ 02/ 12 Dr.Shikha Tripathi,ASE, Bangalore 2

AmritaSc

hoolofEngineering,

Bangalore

2

Last Session

Some more architectural aspects

H/W and S/W aspects

RISC, CISC

Endian


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AmritaSc

hoolofEngineering,

Bangalore

Todays Session

DSP Computational building blocks

Multiplier

Shifter

MAC unit

ALU


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AmritaSc

hoolofEngineering,

Bangalore

Computational building blocks

DSP computational building blocks

Multiplier

Shifter MAC Unit

ALU


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AmritaSc

hoolofEngineering,

Bangalore

Multiplier

Single chip multiplier

Multiplication of 2 binary numbers

implemented in single processor cycle Parallel multiplier

Consider multiplication of two 4-Bit unsigned

numbers A and B

Each bit of product is obtained by summation using

an array of single bit adders

A 4 x 4 braun multiplier requires 12, 3 input, 2

output adders.

For an n x n multiplier number of adders is n(n-1)


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AmritaSchoolofEngineering,

Bangalore

Multiplier Cont.. Speed:

The shift & add technique requires n cycles for nxn

multiply The parallel multiplier is a fully combinational

implementation & once the operands are

available the multiply time is the longest pathdelay time through the gates & adders

It is desirable to have multiplication time

comparable to processing time of othercomputational units & access time of memories.

High speed multiplier is achieved through fully

parallel implementation


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Bangalore

Multiplier Cont..

Bus Width:

Consider Z = X .Y. If X & Y are n bit wide Z can

have maximum 2n bits. In single cycleimplementation we require 3 buses, which is quite

expensive

As an alternative, program bus can be used to carryone of the operands (say X) after multiplication

instruction is fetched from prog. Memory

Separate bus for Z can be avoided as one of thebuses (say X) can be used to transfer Z as X would

have been latched before Z is made available.


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Bangalore

To handle 2n bits of Z there are 2 alternatives:

a. Use X (n bits) & save Z at 2 successive locations

using 2 memory accessesb. Discard lower n bits of Z & save only higher n bits

(most often used)

If Z is to be further processed, all 2n bits areretained & passed to next stage to retain accuracy

of the product. The lower n bits are discarded after

all operations are done For applications where speed is not an issue buffers

& latches may be provided at input & output


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Bangalore

Shifter

Required to scale down or scale up operands

& results to avoid errors resulting from

overflows and underflows duringcomputations

(a) When N number of n bits are added, the

number of required bits increases to(n+log2N) bits

Loss due to overflow can be avoided by scaling

down each number by log2N

Results in decrease in accuracy but loss due to

overflow can be avoided


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Shifter Cont.. The actual sum can be obtained by scaling up the

result by log2N bits

(b) When 2 numbers represented by n bits aremultiplied the product can have maximum 2n

bits. Discarding lower n bits results is loss of

accuracy. In multiplying 2 signed numbersaccuracy is slightly increased by shifting the

product by 1 bit to left before storing higher

order bits.(c) While carrying out floating point additions,

the operands should be normalized to have

same exponent. Shifting is required.


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AmritaSchoolofEnginee

ring,

Bangalore

Barrel Shifter

In DSPs multibit shifts are common

Shifts by multibit is possible in one cycle using a

combinational circuit called Barrel shifter It connects the input lines representing a word to a

group of output lines with required shift determined

by its control inputs. Control unit also determinesthe direction of shift

For input word of n bits, 0 (n-1) bit shifts require

log2n control lines Bits shifted out in the left shift are filled with zeros

in LSB & new bit positions are filled with MSB to

retain the sign in case ofright shift


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ring,

Bangalore

MAC

Requires an add/subtract unit & an additional

register called accumulator at the output of

multiplier Consists of a multiplier that multiplies 2 n-bit

numbers and gives product 2n bits wide. This

is added to or subtracted from the contents of

accumulator and the result saved in

accumulator (A+BC)

If both multiply & accumulate work in parallel,

it can be done in one cycle.


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ring,

Bangalore

MAC Cont..

Saturation logic:

Overflow occurs when accumulator result becomes

larger than the largest (smaller than the smallest(-ve numbers) results in underflow)

Accumulator contents are limited to the most +ve

or most ve value to avoid error known as wrap-around error.


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Bangalore

ALU

In addition to shift, multiply and MAC, DSP is

required to carry out several arithmetic & logic

operations like add, subract, increment,decrement, nagate, AND,OR,NOT,EXOR and

compare like in microprocessor.

ALU is similar to microprocessor with some

additional features


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Bangalore

Example

(a) Find the number of bits required in the

accumulator to perform sum of 64, 16-bit

numbers so that sum can be computedwithout overflow or loss of accuracy?

(b) If all the numbers are fixed point integers,

what is the actual sum of numbers

(c) What is the error in computation of the sum


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ring,

Bangalore

Next Session

Architecture of TMS 320C54x Processor


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ring,

Bangalore

Thank You

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