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Combinational Logic

Chapter 4

Combinational Circuits

Combinational Circuits

• Adders• Subtractors• Comparators• Decoders• Encoders• MultiplexersAvailable as MSI Circuits and as Standard Cells in VLSI (Bonus Assignment: Get one example of each type of combinational circuits in the CMOS family, 5 points for the second exam)

Analysis Procedure

• Given a logical diagram, determine one or more of the following:– Boolean functions;– Truth table;– Explanation of circuit operation

• Make sure the circuit is combinational, not sequential (No feedback loops)

Analysis Procedure

1. Label all gate outputs that are a function of input variables. Determine the Boolean function for each gate output

2. Label the gates that are a function of input variables and previously labeled gates. Find the Boolean functions for these gates

3. Repeat step 2 until output of circuits are obtained4. By repeated substitution of previously defined

functions, obtain the output Boolean functions in terms of input variables

Analysis Procedure

Analysis Procedure𝑇 2=𝐴𝐵𝐶𝑇 1=𝐴=𝐵+𝐶𝐹 2=𝐴𝐵+𝐴𝐶+𝐵𝐶

Step 1

Step 2𝑇 3=𝐹 2

′ 𝑇1𝐹 1=𝑇 3+𝑇 2Steps 3 and 4𝐹 1=𝑇 3+𝑇 2=𝐹 2

′ +𝐴𝐵𝐶¿ ( 𝐴𝐵+𝐴𝐶+𝐵𝐶 )′ (𝐴+𝐵+𝐶 )+𝐴𝐵𝐶¿ ( 𝐴′+𝐵′ ) (𝐴′+𝐶 ′ ) (𝐵′+𝐶 ′ ) ( 𝐴+𝐵+𝐶 )=𝐴𝐵𝐶¿ ( 𝐴′+𝐵′𝐶 ′ ) (𝐴𝐵′+𝐴𝐶 ′+𝐵𝐶 ′+𝐵′𝐶 )+𝐴𝐵𝐶¿ 𝐴′𝐵𝐶 ′+𝐴′𝐵′𝐶+𝐴𝐵′𝐶 ′+ 𝐴𝐵𝐶

Analysis Procedure

1. Determine the number of input variables in the circuit. For inputs, form the possible input combinations and list the binary numbers from to in a table

2. Label the outputs of selected gates with arbitrary symbols

3. Obtain the truth table for the outputs of those gates which are a function of the input variables only

4. Proceed to obtain the truth table for the outputs of those gates which are a function of previously defined values until the columns for all outputs are determined

Analysis Procedure

Design Procedure

1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each

2. Derive the truth table that defines the required relationship between inputs and outputs

3. Obtain the simplified Boolean functions for each output as a function of the input variables

4. Draw the logical diagram and verify correctness of the design

Code conversion example

Code conversion example

Code conversion example𝑧=𝐷 ′𝑦=𝐶𝐷+𝐶 ′ 𝐷′=𝐶𝐷+𝐶+𝐷 ¿ ′𝑥=𝐵′𝐶+𝐵′𝐷+𝐵𝐶′ 𝐷′=𝐵′ (𝐶+𝐷 )+𝐵𝐶 ′𝐷 ′¿𝐵′ (𝐶+𝐷 )+𝐵 (𝐶+𝐷) ′

𝑤=𝐴+𝐵𝐶+𝐵𝐷=𝐴+𝐵(𝐶+𝐷)

Code conversion example

Binary Adder-SubtractorHalf adder

𝑆=𝑥 ′ 𝑦+𝑥𝑦 ′𝐶=𝑥𝑦

Half adder

Full adder

Full adder

𝑆=𝑥 ′ 𝑦 ′ 𝑧+𝑥 ′ 𝑦 𝑧 ′+𝑥 𝑦 ′ 𝑧 ′+𝑥𝑦𝑧𝐶=𝑥𝑦+𝑥𝑧+𝑦𝑧

Implementation of full adder in sum-of-products

Full Adder

Full adder

𝑆=𝑧⊕(𝑥⊕𝑦 )¿ 𝑧 ′ (𝑥 𝑦 ′+𝑥 ′ 𝑦 )+𝑧 (𝑥 𝑦 ′+𝑥 ′ 𝑦) ′¿ 𝑧 ′ (𝑥 𝑦 ′+𝑥 ′ 𝑦 )+𝑧 (𝑥𝑦+𝑥′ 𝑦 ′ )¿ 𝑥 𝑦 ′ 𝑧 ′+𝑥 ′ 𝑦 𝑧 ′+𝑥𝑦𝑧+𝑥′ 𝑦 ′ 𝑧

𝐶=𝑧 (𝑥 𝑦 ′+𝑥 ′ 𝑦 )+𝑥𝑦=𝑥 𝑦 ′ 𝑧+𝑥 ′ 𝑦𝑧+𝑥𝑦

Implementation of full adder using two half adders and one or gate

Binary adder

Carry propagation

Full Adder with and shownCarry Generate

Carry propagation𝑃 𝑖=𝐴𝑖⊕𝐵𝑖𝐺𝑖=𝐴𝑖𝐵𝑖𝑆 𝑖=𝑃𝑖⨁𝐶𝑖

𝐶𝑖+1=𝐺𝑖+𝑃 𝑖𝐶𝑖

𝐶0=input  carry𝐶1=𝐺0+𝑃0𝐶0

𝐶2=𝐺1+𝑃1𝐶1=𝐺1+𝑃1 (𝐺0+𝑃𝑜𝐶0 )=𝐺1+𝑃1𝐺0+𝑃1𝑃0𝐶0

𝐶3=𝐺2+𝑃2𝐶2=𝐺2+𝑃2𝐺1+𝑃2𝑃1𝐺0+𝑃2𝑃1𝑃0𝐶0

Carry lookahead generator

Four-bit adder with carry lookaheadCarry lookahead generator

Four-bit adder with carry lookahead

Binary subtractor

Overflow

• Occurs only when adding two positive numbers or two negative numbers;

• Overflow produces change in result signExample: eight-bit adder

+70

+80

+150

0 1

0 1000110

0 1010000

1 0010110

-70

-80

-150

1 0

1 0111010

1 0110000

0 1101010

Carry bits

Decimal Adder

• Consider adding two decimal digits in BCD

• Output sum cannot exceed 9+9+1=19 (the last 1 is the carry from previous digit)

Decimal AdderCarry

Nee

d co

rrec

tion

𝐶=𝐾+𝑍8𝑍 4+𝑍 8𝑍 2Condition for correcting result

Decimal Adder

Binary Multiplier

Exercise:Multiply

Explain how you carried the multiplication out. How many bits at the output?

Binary Multiplier

Two-bit multiplier

Binary MultiplierExercise: With your neighbor classmate discuss its operation.

Magnitude Comparator

Exercise: Discuss with your neighbor classmate and write down how you would compare two four-bit binary numbers and , where and . You should have three outputs corresponding to , , and . Explain how you determined each condition.

Magnitude Comparator

Does this circuit correspond to what you wrote down in the exercise? Discuss again with your neighbor classmate the comparison of your result with this circuit.

Decoders

Exercise: Minimize the functions for two of the eight output lines.

Decoders

Three-to-eight-line decoder

Exercise: Compare your function with the circuit.

Decoders

0

Decoders

decoder constructed with two decoders

Exercise: Explain how this decoder works.

Combinational logic implementation

Exercise: For the maps of the full adder shown above, express the sum (left) and the carry bit (right) as a sum of minterms.

Combinational Logic Implementation

𝑆 (𝑥 , 𝑦 ,𝑧 )=∑ (1,2,4,7)

𝐶 (𝑥 , 𝑦 , 𝑧 )=∑ (3,5,6,7)Compare in terms of propagation time and number of gates this Full Adder with the previously studied implementation.

Encoders

𝑧=𝐷1+𝐷3+𝐷5+𝐷7

𝑦=𝐷2+𝐷3+𝐷6+𝐷7

𝑥=𝐷4+𝐷5+𝐷6+𝐷7

Priority encoderValid outputHighest priority

Priority encoder

Exercise: obtain the function for

Priority encoder

Multiplexers

• Selects binary information from one of many input lines

• Directs input line to output, controlled by a set of selection lines

• input lines and selection lines

Multiplexers

Two-to-one-line multiplexer

Multiplexers

Four-to-one-line multiplexer

Multiplexers

Quadruple two-to-one-line multiplexer

Boolean function implementation

• Multiplexer is essentially a decoder with OR gates• Thus can implement Boolean functions, similar to

decoders• Minterms generated by circuit associated with

selection inputs• Individual minterms can be selected by data

inputs• Boolean function of variables and data inputs

Boolean function implementation

• More efficient method for implementing a Boolean function of variables with multiplexer of selection inputs

• Remaining variable of function is used for the data inputs

Boolean function implementation

• Example:

Implementation of a three-input Boolean function

0

1

2

3

Selected input line

Boolean function implementation𝐹 ( 𝐴 ,𝐵 ,𝐶 ,𝐷 )=∑ (1,3,4,11,12,13,14,15)

0

1

2

3

4

5

6

7

Three-state gates

Three-state gates

Multiplexers with three-state gates

Homework Assignment

• 4.3• 4.9• 4.17• 4.27• 4.33• Using LogicWorks, simulate a 4-bit full adder

with and without carry-lookahead.