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Pune Vidyarthi Griha’s

COLLEGE OF ENGINEERING, NASHIK – 3.

“ASM”

By

Prof. Anand N. Gharu (Assistant Professor)

PVGCOE Computer Dept.

30th June 2017 .

Introduction to VHDL

• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement

• Examples of VHDL Codes

8/29/2017 2

Introduction

• What is VHDL?

– VHDL is a Hardware Description Language used for

modeling digital systems made of interconnection of

components.

– It is used for describing hardware from the abstract to

concrete level.

Mrs. Sunita M Dol, CSE Dept. 8/29/2017 3

Introduction

• What is VHDL?

– V- VHSIC

• Very High Speed Integrated Circuit

– H- Hardware

– D- Description

– L- Language


Introduction

• VHDL source code file has two main sections

– Entity

• Each entity declaration includes a list of interface signals and

their types that can be used to connect it to other modules.

– Architecture

• The behavior of the circuit and each of its component is

described .

• The behavior may be described in

– Structural form or

– Set of concurrent statement or

– Set of sequential statement


Introduction

• Basic concept of VHDL


Architecture

Entity

Introduction

• Use of Lower Level Entities by Higher Level

Architecture


Architecture

A

Entity A

Architecture

E

Entity E

Architecture

B

Entity B

Architecture

C

Entity C

Architecture

D

Entity D

Introduction

• VHDL Rules and Characteristics

1. A strongly –typed language: Each signal, variable and

constants must match with the predefined type in the

program.

1. Operators: AND, OR, NAND, NOR, XOR, XNOR, NOT,

addition, subtraction, multiplication, division etc.

1. Reserved Keywords

1. Special Notation Symbols

8

Introduction


5. A Free Form Language: Carriage returns, blank

lines, and additional blank spaces may be used

between the words for clarity.

6. Long line can be continue over more than one line.

7. A line starting with two adjacent hyphens is treated

as comment

-- This is a comment


Introduction


8. Concluding semicolon is syntactically required

9. TIME is predefined type.

10. It allows arrays to be indexed in either direction

(ascending or descending)


Introduction


11. Data Flow Language: It is a programming paradigm

whose execution model can be represented by a directed

graph, representing the flow of data between nodes, similarly to a dataflow diagram

12. A basic identifier in VHDL is composed of a sequence of

one or more alphanumeric character and underscore

character. The first character must be an alphabet and the

last character must not be an underscore. Two

consecutive underscores are not allowed


Introduction


13. VHDL is case insensitive.

14. Boolean operators AND, OR, NAND, NOR, XOR,

XNOR, NOT are built in VHDL

15. A system library ieee library is provided which

stores the package for standard logic gates and

other commonly used gates. User library can be

created by the users.


Chapter 6: Introduction to VHDL

• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement



Entity

• Entity refers to any digital device that posses

some form of intercommunication characteristic.

• It is hardware abstraction of an actual digital

hardware device.

• It may be decomposed into its constituents lower

level entity or subcomponents or it may be

treated as a building block to construct a high

level entity.


Entity

• All designs are created using entities.

• A design must have at least one entity.


Entity

• The syntax of entity declaration:

ENTITY entity_name IS

PORT(signal1,signal2,….. :mode type;

signal3,signal4,….. :mode type);

END entity_name;


Name of the circuit Name of the ENTITY

User-defined

Data types:

In-built

User-defined

Port names or

Signal names

Direction of port

3 main types:

in: Input

out: Output

inout: Bidirectional

Note the absence of semicolon “;” at

the end of the last signal and the

presence at the end of the closing

bracket

Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 17

my_ckt

A

B

S

X

Y

• ENTITY my_ckt IS

• PORT (

• A: in bit;

• B: in bit;

• S: in bit;

• X: out bit;

• Y: out bit

• );

• END my_ckt;

Name of the circuit

User-defined

Filename same as circuit

name

Example.

Circuit name: my_ckt

Filename: my_ckt.vhd

Port names or

Signal names

Name of the circuit

User-defined

Filename same as circuit

name recommended

Example:

Circuit name: my_ckt

Filename: my_ckt.vhd

Datatypes:

In-built

User-defined

Direction of port

3 main types:

in: Input

out: Output

inout: Bidirectional

Note the absence of semicolon “;”

at the end of the last signal and the

presence at the end of the closing

bracket

Entity Example

Entity

• Entity Declaration for AND gate:

ENTITY and2 IS

PORT(A, B: IN BIT;

Q: OUT BIT);

END and2;


Entity

• Entity Declaration for OR gate:

ENTITY or2 IS

PORT(A, B: IN BIT;

Q: OUT BIT);

END or2;


Entity

• Entity Declaration for NOT gate:

ENTITY not2 IS

PORT(A: IN BIT;

Q: OUT BIT);

END not2;


Entity

• Entity Declaration for XOR gate:

ENTITY xor2 IS

PORT(A, B: IN BIT;

Y: OUT BIT);

END xor2;


Entity

• Entity Declaration for XOR gate:

ENTITY ckt_fig IS

PORT(A, B: IN BIT;

Y: OUT BIT);

END ckt_fig;


Entity

• Entity Declaration for RSFF gate:

ENTITY rsff IS

PORT(SET, RESET: IN BIT;

Q, QB: INOUT BIT);

END rsff;



• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement



Architecture

• A VHDL design entity is modeled using an entity

declaration and at least one architecture body.

• Entity Declaration describe the external view of

the entity whereas the architecture of body

contains the internal description of the entity.


Architecture

• The internal description can be specified as

– A set of interconnected components that represents

the structure of the entity.

– A set of concurrent statement that represent the

behaviour of the entity.

– A set of sequential statement that represent the behaviour of the entity.

• An architecture body is composed of two parts

– Declarative part and

– Statement part


Architecture

• The syntax of architecture body is ARCHITECTURE architecture_name OF entity_name IS

[declarative part]

BEGIN

[statement part]

END architecture_name

– Declarative part cab be used to declare signals, user

defined types, constants, components, function and procedure definitions which are local to that architecture.

– All the statement in statement part are concurrent

statement which means these are executed concurrently and not sequentially.


Architecture

• Structural Modeling

– An entity is described as a set of interconnected

component in the architecture body.

– The component declaration lists its name, mode and

type of each of its port.

– For each component, component instantiation

statement is required which includes

• a label

• component name and

• association between the actual signals that are visible in

architecture body and the ports of a component with being

instantiated


Architecture

• Structural Modeling Example


This circuit has two

2-input AND gates,

one 2-input OR gate

and two NOT gates

ENTITY xor2 IS

PORT(A, B: IN BIT; Y: OUT BIT);

END xor2;

ARCHITECTUER XOR_STRUCTURE OF xor2 IS

COMPONENT and2

PORT(X, Y: IN BIT, Z:OUT BIT);

END COMPONENT;

COMPONENT or2

PORT(P, Q: IN BIT, R:OUT BIT);

END COMPONENT;

COMPONENT not2

PORT(I: IN BIT, J:OUT BIT);

END COMPONENT;


Architecture name

entity name

For each type of

component, component

declaration is required

SIGNAL AB, BB, X1, X2: BIT;

BEGIN

I1: not2 PORT MAP (A, AB);

I2: not2 PORT MAP (B, BB);

A1: and2 PORT MAP (AB, B, X1);

A2: and2 PORT MAP (BB, A, X2);

Q1: or2 PORT MAP (X1, X2, Y);

END XOR_STRUCTURE;


Local signals or buried nodes

declaration which are neither

inputs nor outputs of the entity

of architecture

Component instantiation statements

includes

• a label such as I1, I2, A1, A2,.. ;

• component name such as not2, and2,

or2,…etc. and

• association between the actual signals

that are visible in architecture body and the

ports of a component with being instantiated

The signals in PORT MAP list are in

the same order in which they

appear in entity definition of the

component

ENTITY rsff IS


Q, QB: INOUT BIT);

END rsff;

ARCHITECTUER RSFF_STRUCTURE OF rsff IS

COMPONENT nand2

PORT(A, B: IN BIT, Y:OUT BIT);

END COMPONENT;

BEGIN

N1: nand2 PORT MAP(SET, QB, Q);

N2: nand2 PORT MAP(RESET, Q, QB);

END RSFF_STRUCTURE;


Architecture name

entity name

component

declaration

Component

instantiation statements

Architecture • Data Flow Modeling

– In this modeling, the flow of data through the entity

is expressed using concurrent signal assignment

statements.

– These statement execute concurrently i.e. in

parallel.

– The statement contained in the model assigns the

values to signals.

– A signal assignment statement is of the form

A<= B;

Signal A gets the value of signal B. Signal B is in

sensitivity list of this statement.


Architecture

• Data Flow Modeling

– Signal assignment statement is executed whenever a

signal in its sensitivity list changes value.

– Time delay can also be introduces in the signal

assignment statement.

A<= B AFTER 10 ns;

Signal A gets the value of signal B after a lapse of 10 ns.


• Architecture Body of AND gate using Data flow

model :

ENTITY and2 IS

PORT(A, B: IN BIT;

Q: OUT BIT);

END and2;

ARCHITECTUER df_and2 OF and2 IS

BEGIN

Y <= A AND B AFTER 10ns;

END df_and2;


Architecture

• Architecture Body of OR gate using Data flow

model :

ENTITY or2 IS

PORT(A, B: IN BIT;

Q: OUT BIT);

END or2;

ARCHITECTUER df_or2 OF or2 IS

BEGIN

Y <= A OR B AFTER 10ns;

END df_or2;


Architecture

• Architecture Body of NOT gate using Data flow

model :

ENTITY not2 IS

PORT(A: IN BIT;

Q: OUT BIT);

END not2;

ARCHITECTUER df_not2 OF not2 IS

BEGIN

Y <= NOT A AFTER 10ns;

END df_not2;


Architecture

• Architecture Body of XOR gate using Data flow

model :

ENTITY xor2 IS

PORT(A, B: IN BIT;

Q: OUT BIT);

END xor2;

ARCHITECTUER df_xor2 OF xor2 IS

BEGIN

Y <= (A AND (NOT B)) OR (B AND (NOT A));

END df_xor2;


Architecture

• Architecture Body of RSFF using Data flow

model:

ENTITY rsff IS


Q, QB: INOUT BIT);

END rsff;

ARCHITECTUER df_rsff2 OF rsff IS

BEGIN

Q <= NOT (QB AND SET) after 5ns;

QB <= NOT (Q AND RESET) after 5ns;

END df_rsff2;


Architecture

Architecture


– There are two types of concurrent signal assignment

statement :

• Conditional Signal Assignment and

• Selected Signal Assignment


Architecture


– Conditional Signal Assignment allows a signal to be

one of several values based on certain conditions to be

satisfied.

– It uses keywords WHEN and ELSE, boolean operators

such as AND, OR, NOT, and XOR and relational operators =, /=(inequality), >, >= and <=



– Conditional Signal Assignment Example

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY mux2 IS

PORT(A, B, S: IN STD_LOGIC;

Y: OUT STD_LOGIC);

END mux2;

ARCHITECTURE df_mux2 OF mux2 IS

BEGIN

Y<= A WHEN S=„0‟ ELSE B;

END df_mux2;


2:1 MUX

A

B

S

Y

Use if IEEE library which

includes STD_LOGIC

type.

STD_LOGIC type is a standard

data type for representation of

logic signals in VHDL

Architecture


– Selected Signal Assignment allows a signal to be

assigned one of several values based on selection

criterion.

– It begins with the keyword WITH, specifies the

selection criterion and then SELECT keyword.

Syntax is

WITH select_signal SELECT

signal_name <= value1 WHEN value1_of_select_sig,

value2 WHEN value2_of_select_sig,

value3 WHEN value3_of_select_sig,

value_default WHEN others; Mrs. Sunita M Dol, CSE Dept. 8/29/2017 43


– Selected Signal Assignment Example

LIBRARY ieee;

USE ieee.std_logic_1164.all

ENTITY mux2 IS

PORT(A, B, S: IN STD_LOGIC;

Y: OUT STD_LOGIC);

END mux2;

ARCHITECTURE df_mux2 OF mux2 IS

BEGIN

WITH S SELECT

Y<= A WHEN „0‟,

B WHEN OTHERS;

END df_mux2;


2:1 MUX

A

B

S

Y

Use if IEEE library which

includes STD_LOGIC

type.

STD_LOGIC type is a standard

data type for representation of

logic signals in VHDL

Architecture

• Behavioural Modeling

– The behaviour of the entity is expressed using

statement which are executed sequentially.

– A process statement is the main mechanism used to model the behaviour of an entity.

– The process statement starts with keyword PROCESS

and ends with the keyword END PROCESS.

– Any assignment made to the signal inside the process

are not visible outside the process until all of the

statement in the process have been evaluated.


Architecture


– The process statement consist of three parts

• Sensitivity list

• Declarative part and

• Statement part.

– Sensitivity list:

• A process statement is always active and executes at all times

if not suspended.

• Following the PROCESS keyword, the sensitivity list in

parentheses is specifies.

• It includes all input signals that are used inside the PROCESS.


Architecture


– Sensitivity list:

• When the program flow reaches the last sequential statement,

the process becomes suspended until another event occurs on

the signal that it is sensitive to.


Architecture


– Declarative part:

• It is used to declare local variables or constants that can be

used only inside the process.

• Signals and constant are declared in declarative part of an

architecture that encloses a process statement can be used

inside the process.

• Initialization of objects declared in a process is done only once

at the beginning of a simulation run.

• The initialization in a subprogram are performed each time the

subprogram is called.


Architecture


– Statement part:

• It consist of the area between the keywords BEGIN and END

PROCESS.

• All the statements are sequential and are executed one after

the other in sequential order.

• The statement part of a process is always active.

• When the program flow reaches the last sequential statement

of this part, the execution returns to the first statement in the

statement part and continues.


ENTITY rsff IS


Q, QB: INOUT BIT);

END rsff;

ARCHITECTUER behave_rsff2 OF rsff IS

BEGIN

PROSESS (SET, RESET)

BEGIN

IF SET=„1‟ AND RESET=„0‟ THEN

Q<= „1‟ AFTER 10ns;

QB<= „0‟ AFTER 10ns;

ELSEIF SET=„0‟ AND RESET=„0‟ THEN



ELSEIF SET=„0‟ AND RESET=„1‟ THEN



ENDIF;

END PROCESS;

END behave_reff2;


Sensitivity list which

includes all input

signals will have

SET and RESET.

Statement

part


• Example:

– Behavior for output X:

• When S = 0

• X <= A

• When S = 1

• X <= B

– Behavior for output Y:

• When X = 0 and S =0

• Y <= „1‟

• Else

• Y <= „0‟

Architecture

my_ckt

A

B

S

X

Y


ARCHITECTURE ARCH_NAME OF MY_CKT IS

BEGIN

PROCESS (A,B,S)

BEGIN

IF (S=„0‟) THEN

X <= A;

ELSE

X <= B;

END IF;

IF ((X = „0‟) AND (S = „0‟)) THEN

Y <= „1‟;

ELSE

Y <= „0‟;

END IF;

END PROCESS P1;

END;

Error: Signals defined as

output ports can only be

driven and not read

Architecture


ARCHITECTURE ARCH_NAME OF MY_CKT IS

SIGNAL XTEMP: BIT

BEGIN

PROCESS (A,B,S, XTEMP)

BEGIN

IF (S=„0‟) THEN

XTEMP <= A;

ELSE

XTEMP <= B;

END IF;

IF ((XTEMP = „0‟) AND (S = „0‟)) THEN

Y <= „1‟;

ELSE

Y <= „0‟;

END IF;

X<= XTEMP;

END PROCESS;

END;

Signals can only be defined in

this place before the BEGIN

keyword

General rule: Include all

signals in the sensitivity list

of the process which either

appear in relational

comparisons or on the right

side of the assignment

operator inside the

PROCESS construct.

In our example:

XTEMP and S occur in

relational comparisons

A, B and XTEMP occur on

the right side of the

assignment operators

Architecture

8/29/2017 Mrs. Sunita M Dol, CSE Dept. 54

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY AND_EXAMPLE IS

PORT(A,B: IN STD_LOGIC;

YA,YB,YC: OUT STD_LOGIC);

END ENTITY AND_EXAMPLE;

ARCHITECTURE TEST OF AND_EXAMPLE IS

BEGIN

-- DATAFLOW MODEL (YA)

YA <= A AND B;

-- STRUCTURAL MODEL (YB)

AND2:A_7408 PORT MAP(A,B,YB);

-- BEHAVIORAL MODEL (YC)

PROCESS(A,B)

BEGIN

YC <= „0‟;

IF((A=„1‟) AND (B = „1‟)) THEN

YC <= „1‟;

ELSE

YC <= „0‟;

END IF;

END PROCESS;

END ARCHITECTURE TEST;

Complete AND GATE Example


• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement



Package

• Package is a collection of codes of commonly

used data type definition, declaration of signals

and component.

• It allows the sharing of definitions of data type,

signals and components among design entities

which access the package.

• It is stored in a computer file system at a location

specified by its name.


Package

• Definition and declarations provided in the

package can be used in any source code file by

including the statement

LIBRARY library_name,

USE library_name.package_name.ALL


The library_name

represents the location in

the computer file system

where the package is

stored. A library may a

system library or a user

library

The package name

is specified by a

package_name

which may a

system library or a

user library

ALL is used to

for having

access to the

entire

package

USE is

used for

accessing

the

package


• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement



Data Objects

• In VHDL code, information is represented as

signals, variables and constants which are

referred to as data objects.

• Signals basically represent wires in a circuit.

• VHDL variables are similar to signals but they do

not have physical significance in a circuit.

• Variables are used in functions, procedures and

processes

• Constant are names assigned to specific values

of a type.


Data Objects

• Declaration of Data Objects

– A signal is declared as

SIGNAL signal_name: type_name

– Signal Type: The most commonly used signal types

are:

• BIT

• BIT_VECTOR

• STD_LOGIC

• STD_LOGIC_VECTOR

• INTEGER

• ENUMERATION

• BOOLEAN


Data Objects

• Declaration of Data Objects

– Signal Type

• BIT: this type is predefined signal type in VHDL. Objects of BIT

type can have the values „0‟ or ‟1‟

SIGNAL A: BIT;

• BIT_VECTOR: This is also a predefined type. It is used to

declare a group of elements of the same type together as a

single object such as byte

SIGNAL byte: BIT_VECTOR(7 DOWN TO 0);

byte<= “11001001”;

…

SIGNAL byte: BIT_VECTOR(1 TO 4);


MSB LSB

byte(7)=1 Byte(6)=1 Byte(0)=1

Data Objects • Declaration of Data Objects

– Signal Type

• STD_LOGIC: This type of data object was added to VHDL

standard in IEEE standard 1164. For using this type, the

following two statements are to be included

LIBRARY IEEE;


• STD_LOGIC_VECTOR: This type is an extension of

BIT_VECTOR type. It represents an array of STD_LOGIC

objects. A signal declaration statement can be:

SIGNAL A, B, C: STD_LOGIC_VECTOR (3 DOWN TO 0);

Use of STD_LOGIC_VECTOR type also require access to

STD_LOGIC_1164 package



– Signal Type

• INTEGER: It is similar to mathematical integer. An INTEGER

signal represents a binary number of 32 bits and hence it can

represent the number s from –(231-1) to +(231-1). It is also

possible to declare integer with fewer bits using the RANGE

keyword.

SIGNAL B: INTEGER RANGE -127 TO 127;

• ENUMERATION: This type of signal can have user specified

possible values of the signal. Its type declaration has the list-

value separated by commas.

TYPE traffic_light_state IS (reset, stop, wait, go);



– Signal Type

• BOOLEAN: This type of object has two values, true and false

where true is equivalent to 1 and false is 0. BOOLEAN type is a

predefined type.

SIGNAL lock_out: BOOLEAN;



– VARIABLE data object

• A variable is declared as

VARIABLE variable_name: variable_type;

Assignment operator used for variable is :=.

• Examples

VARIABLE temp: INTEGER;

temp:=0;

VARIABLE sum : INTEGER RANGE 0 TO 100 :=10;

VARIABLE found, done: BOOLEAN;



• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement



CASE statement

• It is similar to a selected signal statement.

• The CASE statement has a selection signal or

expression and WHEN clauses for various

valuations of the selection signal.


CASE statement

• Its general form is shown below:

CASE expression IS

WHEN constant_value => statement;

WHEN constant_value => statement;

WHEN OTHERS => statement;

END CASE;


Examples of VHDL Code

• Multiplexers in VHDL:

– Consider the 4:1 multiplexer circuit


•Using

CASE

statement

LIBRARY IEEE;

USE

IEEE.STD_LOGIC_116

4.ALL;

ENTITY MUX IS

PORT( I3: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I2: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I1: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I0: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

S:IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

O:OUT

STD_LOGIC_VECTOR(

1 DOWNTO 0));

END MUX;

ARCHITECTURE

BEHV1 OF MUX IS

BEGIN

PROCESS(I3,I2,I1,I0,S)

BEGIN

-- USE CASE

STATEMENT

CASE S IS

WHEN "00" => O <=

I0;

WHEN "01" => O <=

I1;

WHEN "10" => O <=

I2;

WHEN "11" => O <=

I3;

WHEN OTHERS =>

O <= "ZZZ";

END CASE;

END PROCESS;

END BEHV1;



• Introduction

• Entity

• Architecture

• Package

• Data Objects

• CASE Statement




• Describing Truth Table in VHDL:

– Consider the truth table given below


Row no

Inputs

A B C

0 0 0 0 0

1 0 0 1 1

2 0 1 0 1

3 0 1 1 0

4 1 0 0 1

5 1 0 1 0

6 1 1 0 0

7 1 1 1 1

ENTITY table1 IS

PORT(A, B, C: IN BIT; Y: OUT BIT);

END table1;

ARCHITECTUR truth_table of table1 IS

SIGNAL comb_cir : BIT_VECTOR (2 DOWN TO 0);

BEGIN

comb_cir <= A&B&C;

Y <= „0‟ WHEN “000”,

„1‟ WHEN “001”,

„1‟ WHEN “010”,

„0‟ WHEN “011”,

„1‟ WHEN “100”,

„0‟ WHEN “101”,

„0‟ WHEN “110”,

„1‟ WHEN “111”;

END truth_table;


& is used to connect

the bit variables to

form a bit vector

Row

no

Inputs

A B C

0 0 0 0 0

1 0 0 1 1

2 0 1 0 1

3 0 1 1 0

4 1 0 0 1

5 1 0 1 0

6 1 1 0 0

7 1 1 1 1


• Arithmetic Circuits in VHDL:

– Consider the half adder circuit


• Using Structural Architecture:

LIBRARY IEEE;


ENTITY H_A IS

PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC);

END H_A;

ARCHITECTURE HA_STR OF H_A IS

COMPONENT XOR2

PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC);

END COMPONENT;

COMPONENT AND2

PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC);

END COMPONENT;

BEGIN

X1: XOR2 PORT MAP (A,B,S);

X2: AND2 PORT MAP (A,B,C);

END HA_STR;


• Using Data Flow Architecture:

LIBRARY IEEE;


ENTITY H_A IS


END H_A;

ARCHITECTURE HA_DF OF H_A IS

BEGIN

S <= A XOR B AFTER 10ns;

C <= A AND B AFTER 5ns;

END HA_DF;


• Using Behavioural Modeling ENTITY H_A IS

PORT(A, B: IN BIT;

S, C: OUT BIT);

END H_A;

ARCHITECTUER BEHAVE_HA OF H_A IS

BEGIN

PROSESS (A, B)

BEGIN

IF A=„0‟ AND B=„0‟ THEN

S <= „0‟ AFTER 10ns;

C <= „0‟ AFTER 10ns;

ELSEIF A=„0‟ AND B=„1‟ THEN









ENDIF;

END PROCESS;

END BEHAVE_HA;


• Using Data Flow Architecture with selected

signal assignment:

LIBRARY IEEE;


ENTITY H_A IS


END H_A;

ARCHITECTURE HA_DFSS OF H_A IS

BEGIN

HA_X <= A & B;

HA_Y <= C & S;

WITH HA_X SELECT

HA_Y <= “00” WHEN “00”,

“01” WHEN “01”,

“01” WHEN “10”,

“10” WHEN “11”;

END HA_DFSS;



• Arithmetic Circuits in VHDL:

– Consider the half subtractor circuit


• Using Structural Architecture:

LIBRARY IEEE;


ENTITY H_S IS

PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC);

END H_S;

ARCHITECTURE HS_STR OF H_S IS

COMPONENT XOR2

PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC);

END COMPONENT;

COMPONENT AND2

PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC);

END COMPONENT;

COMPONENT NOT2

PORT (M: IN STD_LOGIC; N: OUT STD_LOGIC);

END COMPONENT;

SIGNAL BB: BIT;

BEGIN

X1: XOR2 PORT MAP (A,B,DIFF);

X2: NOT2 PORT MAP (A, AA);

X3: AND2 PORT MAP (AA,B,BORROW);

END HS_STR;


• Using Data Flow Architecture:

LIBRARY IEEE;


ENTITY H_S IS


END H_S;

ARCHITECTURE HS_DF OF H_S IS

BEGIN

DIFF <= A XOR B AFTER 10ns;

BORROW <= ((NOT A) AND B) AFTER 5ns;

END HS_DF;


• Using Behavioural Modeling ENTITY H_S IS

PORT(A, B: IN BIT;

DIFF, BORROW: OUT BIT);

END H_S;

ARCHITECTUER BEHAVE_HS OF H_S IS

BEGIN

PROSESS (A, B)

BEGIN

IF A=„0‟ AND B=„0‟ THEN

DIFF <= „0‟ AFTER 10ns;

BORROW <= „0‟ AFTER 10ns;










ENDIF;

END PROCESS;

END BEHAVE_HS;


• Using Data Flow Architecture with selected

signal assignment:

LIBRARY IEEE;


ENTITY H_S IS


END H_S;

ARCHITECTURE HS_DFSS OF H_S IS

BEGIN

HA_X <= A & B;

HA_Y <= BORROW & DIFF;

WITH HA_X SELECT

HA_Y <= “00” WHEN “00”,

“11” WHEN “01”,

“01” WHEN “10”,

“00” WHEN “11”;

END HS_DFSS;



• Multiplexers in VHDL:

– Consider the 4:1 multiplexer circuit


•Using

CASE

statement

LIBRARY IEEE;

USE

IEEE.STD_LOGIC_116

4.ALL;

ENTITY MUX IS

PORT( I3: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I2: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I1: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

I0: IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

S:IN

STD_LOGIC_VECTOR(

1 DOWNTO 0);

O:OUT

STD_LOGIC_VECTOR(

1 DOWNTO 0));

END MUX;

ARCHITECTURE

BEHV1 OF MUX IS

BEGIN

PROCESS(I3,I2,I1,I0,S)

BEGIN

-- USE CASE

STATEMENT

CASE S IS

WHEN "00" => O <=

I0;

WHEN "01" => O <=

I1;

WHEN "10" => O <=

I2;

WHEN "11" => O <=

I3;

WHEN OTHERS =>

O <= "ZZ";

END CASE;

END PROCESS;

END BEHV1;



• Decoder in VHDL:

– Consider the 2:4 decoder circuit


• Using Sequential Architecture model

LIBRARY IEEE;


ENTITY DECODER24 IS

PORT( A, B, EN:IN STD_LOGIC;

Z:OUT STD_LOGIC_VECTOR(0 TO 3));

END DECODER24;

ARCHITECTURE BEHV_DEC OF DECODER24 IS

BEGIN

-- PROCESS STATEMENT

PROCESS (A, B, EN)

VARIABLE AB, BB: STD_LOGIC;

BEGIN

AB := NOT A;

BB := NOT B;

IF EN = „1‟ THEN

Z(3) <= NOT(A AND B);

Z(2) <= NOT (AB AND B);

Z(1) <= NOT (A AND BB);

Z(0) <= NOT (AB AND BB);

ELSE

Z <= “1111”;

END IF;

END PROCESS;

END BEHV_DEC;


• Using CASE Statement

LIBRARY IEEE;


ENTITY DECODER24 IS


Z:OUT STD_LOGIC_VECTOR(0 to 3));

END DECODER24;

ARCHITECTURE BEHV_DEC2 OF DECODER24 IS

SIGNAL AB : STD_LOGIC_VECTOR (1 DOWN TO 0);

BEGIN

AB <= A & B;

PROCESS (AB, EN)

BEGIN

IF EN = „1‟ THEN

CASE AB IS

WHEN "00" => Z <= “1110";

WHEN "01" => Z <= “1101“;

WHEN OTHERS => Z <= “1011“;

END CASE;

ELSE Z <= “1111";

END IF;

END PROCESS

END BEHV_DEC2;


• Using Selected signal Assignment Statement

LIBRARY IEEE;


ENTITY DECODER24 IS


Z:OUT STD_LOGIC_VECTOR(0 TO 3));

END DECODER24;

ARCHITECTURE BEHV_DEC2 OF DECODER24 IS

SIGNAL ENAB : STD_LOGIC_VECTOR (2 DOWN TO 0);

BEGIN

ENAB <= EN & A & B;

WITH ENAB SELECT

Z <= “1110” WHEN “100”,

“1101” WHEN “101”,

“1011” WHEN “110”,

“0111” WHEN “111”;

“1111” WHEN OTHERS;

END BEHV_DEC2;



• Priority Encoder in VHDL:

– Consider the Decimal to BCD Priority Encoder circuit


• Using Conditional Signal Assignment

Statement

LIBRARY IEEE;


ENTITY PRIORITY_ENCODER IS

PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);

Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );

END PRIORITY_ENCODER;

ARCHITECTURE BEHV_PE OF PRIORITY_ENCODER IS

BEGIN

Y <= “0110” WHEN I(9) = „0‟ ELSE

“0111” WHEN I(8) = „0‟ ELSE

“1000” WHEN I(7) = „0‟ ELSE

“1001” WHEN I(6) = „0‟ ELSE

“1010” WHEN I(5) = „0‟ ELSE

“1011” WHEN I(4) = „0‟ ELSE

“1100” WHEN I(3) = „0‟ ELSE

“1101” WHEN I(2) = „0‟ ELSE

“1110” WHEN I(1) = „0‟ ELSE

“1111”

END BEHV_DEC2;


• Using Sequential Signal Statement

LIBRARY IEEE;


ENTITY PRIORITY_ENCODER IS

PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);

Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );

END PRIORITY_ENCODER;

ARCHITECTURE BEHV_PE2 OF PRIORITY_ENCODER IS

BEGIN

PROCESS(I)

BEGIN

IF I(9) = „0‟ THEN Y <= „0110‟;

ELSEIF I(8) = „0‟ THEN Y <= „0111‟;

ELSEIF I(7) = „0‟ THEN Y <= „1000‟;

ELSEIF I(6) = „0‟ THEN Y <= „1001‟;

ELSEIF I(5) = „0‟ THEN Y <= „1010‟;

ELSEIF I(4) = „0‟ THEN Y <= „1011‟;

ELSEIF I(3) = „0‟ THEN Y <= „1100‟;

ELSEIF I(2) = „0‟ THEN Y <= „1101‟;

ELSEIF I(1) = „0‟ THEN Y <= „1110‟;

ELSE Y <= „1111‟

END IF;

END PROCESS;

END BEHV_DEC2;



• Comparator in VHDL:



LIBRARY IEEE;


USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COMPARATOR IS

PORT( A, B : IN STD_LOGIC_VECTOR(1 DOWN TO 0);

AGTB, AEQB, ALTBY : OUT STD_LOGIC);

END COMPARATOR;

ARCHITECTURE BEHV OF COMPARATOR IS

BEGIN

AGTB <= „1‟ WHEN A>B ELSE „0‟;

AEQB <= „1‟ WHEN A=B ELSE „0‟;

ALTB <= „1‟ WHEN A<B ELSE „0‟;

END BEHV;


• BCD to 7-Segment Decoder in VHDL:



LIBRARY IEEE;


ENTITY DEC_7_SEG IS

PORT( BCD : IN STD_LOGIC_VECTOR(3 DOWN TO 0);

LED7 : OUT STD_LOGIC_VECTOR(1 TO 7));

END DEC_7_SEG;

ARCHITECTURE BCDTO7SEG OF DEC_7_SEG IS

BEGIN

PROCESS(BCD)

BEGIN

CASE BCD IS

WHEN “0000” => LED7 <= “1111110”;

WHEN “0001” => LED7 <= “0110000”;

WHEN “0010” => LED7 <= “1101101”;

WHEN “0011” => LED7 <= “1111001”;

WHEN “0100” => LED7 <= “0110011”;

WHEN “0101” => LED7 <= “1011011”;

WHEN “0110” => LED7 <= “0011111”;

WHEN “0111” => LED7 <= “1110000”;

WHEN “1000” => LED7 <= “1111111”;

WHEN “1001” => LED7 <= “1110011”;

WHEN OTHERS => LED7 <= “-------”;

END CASE;

END PROCESS;

END BCDTO7SEG;


• Describing Sequential Circuit using VHDL:

– EVENT Attribute: the EVENT attribute when attached

to a signal name such as Clock, yields a value of type

Boolean that is 'true' or 'false' depending upon the

occurrence of the event or not respectively.

• It is expressed as Clock' EVENT.

• Its value is 'true' when a change occurs in the value of clock

and 'false' when there is no change.

• The Clock' EVENT AND Clock='1' statement describes LOW to

HIGH transition of the clock signal when a change occurs in the

value of Clock. This statement describe the positive edge

triggered FLIP-FLOPS.




– WAIT statement: A WAIT statement is used to suspend

the sequential execution of a process or subprograms.

• The suspended process or subprogram can be resumed

by specifying the WAIT statement in the following three

ways:

– WAIT ON signal changes

– WAIT UNTIL an expression is true

– WAIT FOR a specific amount of time




– WAIT statement

• WAIT ON: This statement is used for suspending the

execution of the process for the time specified in terms of

an event occurring on the signal specified in the WAIT

statement.

– e.g. in a clocked FF with an asynchronous reset input

WAIT ON reset, clock; statement causes the process to

suspend execution until an event occurs on either reset or

clock input.

– This clause can be used in clocked synchronous circuits

description.




– WAIT statement:

• WAIT UNTIL: This statement suspends execution of the

process until the expression specified in the statements

returns a value true.

– e.g. for a clocked FF, the WAIT UNTIL statement given

below causes resumption of execution of the process when

a rising edge occurs on the clock input

WAIT UNTIL Clock = '1' AND Clock' EVENT;




– WAIT statement:

• WAIT FOR: This statement is used for suspending the

execution of the process for the time specified either

directly or by an expression. The execution continues on

the statement following the WAIT statement after the

specified time.

– e.g. WAIT FOR 10 ns;

– suspends the execution for 10 ns after which the execution

continues with the statement following the WAIT statement.

– If the time is specified by an expression such as (A+B*C)

then the time is calculated evaluating the expression.



• Flip Flop in VHDL:

– Consider DFF


Data IN

Clock

Output

D Q

_

Q

LIBRARY IEEE;


ENTITY DFF IS

PORT(DATA_IN:IN STD_LOGIC;

CLOCK:IN STD_LOGIC;

DATA_OUT:OUT STD_LOGIC);

END DFF;

ARCHITECTURE BEHV_DL OF DFF IS

BEGIN

PROCESS(DATA_IN, CLOCK)

BEGIN

-- CLOCK RISING EDGE

IF CLOCK='1' THEN

DATA_OUT <= DATA_IN;

END IF;

END PROCESS;

END BEHV_DL;


Data IN

Clock Output

D Q

_

Q



– Consider DFF


Data IN

Clock

Output

D Q

_

Q

LIBRARY IEEE;


USE WORK.ALL;

ENTITY DFF IS


CLOCK:IN STD_LOGIC;


END DFF;

ARCHITECTURE BEHV OF DFF IS

BEGIN

PROCESS(DATA_IN, CLOCK)

BEGIN

-- CLOCK RISING EDGE

IF (CLOCK='1' AND CLOCK'EVENT) THEN


END IF;

END PROCESS;

END BEHV;


Data IN

Clock Output

D Q

_

Q



– Consider DFF


Data IN

Clock

Output

D Q

_

Q

LIBRARY IEEE;


USE WORK.ALL;

ENTITY DFF IS


CLOCK:IN STD_LOGIC;


END DFF;

ARCHITECTURE BEHV1 OF DFF IS

BEGIN

PROCESS

BEGIN

WAIT UNTILCLOCK'EVENT AND CLOCK='1'


END PROCESS;

END BEHV1;


Data IN

Clock Output

D Q

_

Q


• Register in VHDL:

8/29/2017 108


LIBRARY IEEE;


ENTITY SHIFT4 IS

PORT(DIN:IN STD_LOGIC;

CLOCK, CLEAR:IN STD_LOGIC;

Q:OUT STD_LOGIC(3 DOWN TO 0));

END SHIFT4;

ARCHITECTURE BEHV OF DFF IS

BEGIN

PROCESS(CLEAR, CLOCK)

BEGIN

IF CLEAR ='0' THEN Q <= “0000”;

ELSEIF (CLOCK='1' AND CLOCK'EVENT) THEN

Q(3) <= DIN;

Q(2) <= Q(3);

Q(1) <= Q(2);

Q(1) <= Q(0);

END IF;

END PROCESS;

END BEHV;

Thank You

8/29/2017 110

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