COE 1502Design Synthesis

Synthesis Theory

Idea:– “Compile” VHDL into a cell-level netlist

A netlist is a graph– Vertices represent cells (such as gates, latches, etc.)– Edges represent interconnection wires

To do this, we need– VHDL– A technology cell library

– Place-and-route netlist onto FPGA/ASIC To do this, we need

– Netlist– CLB specification and routing matrix (FPGA)

Output is FPGA routing bitmap

Netlists

Leonardo Spectrum’s output format is a text EDIF netlist Example:

port

port

port

OR2

AND2

port

A

B

C

D

E

instance OR2 as ix1instance AND2 as ix3

ix1 A B Dix3 D C E

Note that AND2 and OR2 are technology cells

Netlists

Actual Leonardo output:

(edif example (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2003 01 23 17 13 48) (program "LeonardoSpectrum Level 3" (version "2002b.21")) (author "Exemplar Logic Inc"))) (external PRIMITIVES (edifLevel 0) (technology (numberDefinition )) (cell OR2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p0 "in[0]") (direction INPUT)) (port (rename p1 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))) (cell AND2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p2 "in[0]") (direction INPUT)) (port (rename p3 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))))

(library alu (edifLevel 0) (technology (numberDefinition )) (cell example (cellType GENERIC) (view struct (viewType NETLIST) (interface (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port E (direction OUTPUT))) (contents (instance ix1 (viewRef INTERFACE (cellRef OR2 (libraryRef PRIMITIVES )))) (instance ix3 (viewRef INTERFACE (cellRef AND2 (libraryRef PRIMITIVES )))) (net A (joined (portRef A ) (portRef p0 (instanceRef ix1 )))) (net B (joined (portRef B ) (portRef p1 (instanceRef ix1 )))) (net C (joined (portRef C ) (portRef p3 (instanceRef ix3 )))) (net E (joined (portRef E ) (portRef out (instanceRef ix3 )))) (net D (joined (portRef out (instanceRef ix1 )) (portRef p2 (instanceRef ix3 )))))))) (design example (cellRef example (libraryRef alu ))))

ALU Wrapper

Your ALU design must be placed into a wrapper before you perform synthesis

– The ALU wrapper is located in the COELib library Wrapper shares a signal namespace with its wrapper and the signals

on the Wild-One card Copy the wrapper to your ALU library

– Your ALU is already instantiated inside Your job:

– Wire up desired signals to 32 output buffers (which will be visible on the logic analyzer for testing)

– Topmost buffer corresponds to LSB on LA (wire downward)– Suggestion: bring out ALUOp, 8 bits of A, B, and R, and Overflow, Zero,

RST, and PCLK One you do this, generate a netlist for the wrapper using Leonardo

– Use the tutorial on the website

ALU Wrapper

Your ALURegisters

Controller that selectively

enables the registers (reading

FIFO) and controls writing result to FIFO

memoryFIFOIn_Reg bus from

FIFO memory4x1 bit buffers

AnalyzerData

FIFOOut_Data

FIFO control signals

ALU Wrapper

Your ALU in pe0

pe1

Daughter card connectors

PCI interface

Memory

ALU Wrapper

Da

ug

hte

r card

con

ne

ctor

PCI host interface

FPGA

FIF

OS

RA

M

Pinout wrapper

ALU wrapper

ALU

Preparing for Synthesis

Copy the CPE0 directory from I:\1502 to your group directory…– This is the directory where you will perform

synthesis, place-and-route, and test your design using the logic analyser

Leonardo Spectrum

Setup Leonardo…

Leonardo Spectrum

If the synthesis completes without error, copy ALU_WRAP.edf from<ALU_root>\ls\netlists\alu_wrap_struct\netlists\alu_wrap.edf

into your CPE0 directory.

Place-and-route

Once we have the netlist, we need to build the FPGA configuration file

– GOAL: map netlist onto FPGA by writing to CLBs and perform routing

– CLBs use registered lookup tables, so cells need to be translated into SRAM cells

Placing and Routing

Place and route the design…– Open a command window using Start | Run | cmd– Change to your CPE0 directory– Edit the Makefile by changing line 4 such that the variable points to

your CPE0 directory– Enter the following command:

set PATH=n:\xilinx\bin\nt;d:\local\wild-one\tools;%PATH% set xilinx=n:\xilinx

– Run make– Run mcs2bin cpe0.mcs cpe0.bin

This creates the bin file Notes:

– Use make clean to start over– Use the generated log file to check for errors

Testing Design on Logic Analyzer