Co-Simulation of interconnected power electronics … of interconnected power electronics using...
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1 © 2016 The MathWorks, Inc. Bao Nguyen, Senior Pilot Engineer, MathWorks Kishore Karnane, Product Management Director, Cadence Co-Simulation of interconnected power electronics using Simulink-PSpice interface and components defined in C/C++ and SystemC
Transcript of Co-Simulation of interconnected power electronics … of interconnected power electronics using...
1© 2016 The MathWorks, Inc.
Bao Nguyen, Senior Pilot Engineer, MathWorksKishore Karnane, Product Management Director, Cadence
Co-Simulation of interconnected power electronics using Simulink-PSpice interface and components defined in C/C++ and SystemC
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AGENDA
Challenges in Analog/Mixed-Signal Design
The SLPS Co-Simulation Interface
The Device Modeling Interface (DMI) and Exporting Models from Simulink– Demo
Conclusion
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Analog/Mixed-Signal Design
Digital Analog Electro-mechanical
Target:• MCU (SW)• FPGA, ASIC (HW)
Target:• Transitor-level
Design
Example: Field-oriented Control of a Permanent-Magnet-Synchrone-Machine
This control technique is common in motor drive systems for hybrid electric vehicles, manufacturing machinery, and industrial automation
Field-OrientedController PWM Power
InverterPMSM
LoadIv
vexp
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IMPLEMENTATION
INTEGRATION
TEST & VER
IFICATIO
N
Analog
SPICE
IMPLEMENTATION
Digital
C/C++HDL
DigitalHardware
AnalogHardware
Specification isolated from verification
No run-time analog/digital links
Disconnected teams
Design trade-offs difficult
Limited analog design abstractions
SPECIFICATION
Slow design iterations
Challenges in Classical Mixed-Signal Design
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„Executable Specification“
Simulink as multi-domain simulation environment– Time-continuous and time-discrete
(sampled)– Event-triggered– Mathematical and physical algorithm
modeling– Robustness through environment
modeling
Automatic code generation (C/C++, HDL)
Continuous Verification
INTEGRATION
IMPLEMENTATION
TEST & VER
IFICATIO
N
SPICE
SiliconMCU DSPFPGA ASIC
HDL C/C++C/C++HDL
TEST SYSTEM
DESIGNDESIGN
Environment Models
Timing and Control Logic
Digital Models Analog Models
Algorithms
RESEARCH
Digital Models
Timing and Control Logic
Algorithms
Analog Models
REQUIREMENTS
Environment Models
Model-Based Design
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Bottom-Up Workflow– Starting point:
Transistor-level schematic
– Needs Input stimuli generation Integration in surrounding multi-domain
system Analysis in time/frequency domain
– Solution Co-simulation with OrCAD PSpice using
SLPSINTEGRATION
IMPLEMENTATION
TEST & VER
IFICATIO
N
SPICE
SiliconMCU DSPFPGA ASICTEST
SYSTEM
HDL SPICE
DESIGN
REQUIREMENTS
Environment Models
Timing and Control Logic
Digital Models Analog Models
Algorithms
RESEARCH
Timing and Control Logic
Algorithms
Digital Models
C/C++
Model-Based Design for Analog/Mixed-Signal
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Top-Down Workflow– Starting point:
Mathematical Model Physical Model
– Needs Simulation speed (proof of
concept) Reuse of existing testbench Sign-off Transistor-level simulation
– Solution Co-simulation with Simulink and
PSpice using SLPS Model integration through
automatic C code generationand PSpice DMI
INTEGRATION
IMPLEMENTATION
TEST & VER
IFICATIO
N
SPICE
SiliconMCU DSPFPGA ASICTEST
SYSTEM
HDL SPICE
DESIGN
REQUIREMENTS
Environment Models
Timing and Control Logic
Digital Models Analog Models
Algorithms
RESEARCH
Timing and Control Logic
Algorithms
Digital Models Analog Models
C/C++C/C++
Model-Based Design for Analog/Mixed-Signal
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What is SLPS?
SLPS = Simulink + PSpice Co-Simulation
– Simulink Multi-domain simulation environment for dynamic systems Algorithm development and verification platform
– PSpice: SPICE-based simulator Simulation of electrical and electronic circuits Circuit design platform Hardware
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How does SLPS work?
Simulink plays the master role
The SLPS-block in Simulink builds the interface between both simulators
Both simulators work with their own time-step-control algorithm– guarantees the optimal compromise
out of simulation accuracy and performance.
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Step 1: Algorithm Design and Verification
Physical Models of Mechanical
Load Scenarios
Time-continuousPI Controllers
(speed, current)
Time-discretePWM
Generator
Physical Modelsof
Electrical Components
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Step 1: Algorithm Design and Verification
Load Scenario: with Load
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Step 1: Algorithm Design and Verification
Load Scenario: with Load and Vibration
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Step 2: Schematic Entry (PSpice)
IGBT
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SLPSCo-Simulation
Interface
Step 3: Simulink/PSpice Co-Simulation (SLPS)
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Simulink Simulation
Simulink / PSpiceCo-Simulation
(SLPS)
wm
_ref
, wm
wm
_ref
, wm
Te [N
m]
Te [N
m]
Vs_a
bc [V
]
Vs_a
bc [V
]
Is_a
bc [A
]
Is_a
bc [A
]
Step 3: Simulink/PSpice Co-Simulation (SLPS)
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Vehicle Electronics
Emission and Fuel
Economy
Comfort &Performance
Safety & Quality
Automotive Engineering Interdisciplinary Design Challenge
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Vehicle Electronics
Explosion of Interconnected Electronic Systems with Embedded Software having some very challenging Power Density issues created by System miniatuarization for reliability, form & functions.
Automotive Engineering Interdisciplinary Design Challenge
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• Mixed Signal Control “Drive By Wire” over bus protocols
Interconnected Systems
• Complex Algorithmic Control, Configurability and Maintenance
Embedded Software
• Reliability, smaller space, increased Functions packaged in Lower Power consumption
System Miniaturization
• Smaller form factors handling huge power transfer are driving higher power density
Power Density
System Design linked to System Implementation
Mixed Signal Accuracy accelerated with System Model Abstractions
Virtual Prototyping –Model/HIL/SW Co-Simulation for early S/W Validation
Implementation across multiple design fabrics –Chip/Package/Board
Analog Behavioral and New Technology Physical Device modeling
PSpice SolutionDesign Trends
Automotive Engineering Interdisciplinary Design Challenge
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Physical device compact model
SystemC model supporting embedded S/W and different abstraction levels
Analog behavioral
Digital C/C++ with embedded SW block
Every complex device on PCB - a system model embedded in mixed-signal device model
PSpice complex device macro-model
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Algorithmic Models(MATLAB, Simulink, C/C++)
System Models (SystemC)
Digital Models with IO/Timing/Constraint
Digital Functional Models
PSpice Behavioral Models
Compact Device Models
PSpice Models
Model Abstractions
Architectural
Functional
Behavioral
Gate Level
Circuit Level
Physical Implementation
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PSpice PCB Implementation
PSpice System Design
PSpice PCBBlock in Simulink
Simulink Coderto PSpice Block
System Design Exploration to Implementation
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Model CodeDMIPhysicalDevices
Analog BehavioralDevices
Digital Devices
C/C++, SystemC, VerilogA, MATLAB, Simulink
Communicatingwith PSpicePSpice Simulator
Device Modeling Interface
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Device Modeling Interface Libraries
PSpice Common API Definitions
PSpice Common Model API Definitions
PSpice BasePspice Digital API Definitions
PSpice Engine Functions
PSpice Device User Information
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Generate C++ Code
for Simulink Model
Generate Device User Information and register with Engine Function
Compile and
generating DLL, LIB
Associate PSpice
model with symbol and
Simulate
Device Modeling Interface – Embedded Coder Steps
Requires Embedded Coder license
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OrCADCapture
Embedded Coder
Embedded Coder
Embedded Coder
PSpice
Top Level Analog
Schematic
Associate PSpice Model with a Symbol
Run Simulation
Simulink Model
Generated C++ Code
Code Embedded inside DMI
Compile and generate dll
PSpice
Device Modeling Interface – Steps for integrating Simulink models
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Simulink Model Example
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Simulink-PSpice Target Configuration – Code Generation
Embedded Coder Target
Custom Template Makefile
C++ Code
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Simulink-PSpice Target Configuration – Custom Code
DMI‘s Libraries Path
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Simulink-PSpice Target Configuration – Interface
Fucnction Prototype
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Simulink-PSpice Target Configuration – Templates
Custom DMI Wrapper Code
Template
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Simulink Simulation Results
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PSpice Model Example
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PSpice DMI Library
Generated by Embedded Coder
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PSpice Simulation Results
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Demo
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Q&A
MathWorks’s Point-of-Contact:– Bao Nguyen [email protected]– Corey Mathis [email protected]
Cadence’s Point-of-Contact : – Kishore Karnane [email protected]
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Conclusion
SLPS is a needed tool because of:– Introduction of newest technologies and efficient methods.– Possibility to verify and optimize SW-Algorithms with HW-Models.– Reconnaissance and compensation of errors during the specification and
implementation reducing development time.
DMI increase the possibilities: – System Level Simulation importing C/C++/SystemC and Simulink Blocks into a
unique simulator. – Hardware in the Loop, getting the results in a completely reliable environment to
test the new critical functions.
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Conclusion
PSpice SLPS SimulinkHiL DMI
