Cmpe 125 Verilog Notes

8/2/2019 Cmpe 125 Verilog Notes

1/32

Module Definition

module module_name (module_outputs, module_inputs);output module_outputs;input module_inputs;

..

.endmodule

Ex:

x_gatein[3:0] out

module exegete(out,in);output out;input[3:0] in;

.

.

.endmodule

Ex:

a

bZ

module and_gate( z, a, b)output z;input a,b;

.

.

.endmodule


2/32

Instantiating Modules

x_gatein[3:0] out

a

bZ

pout1

out2m[3:0]

n

module y_gate( out1, out2, m, n, p);

output out1, out2;input[3:0] m;input n, p;

and_gate name1 (.a (n), .b(p), .z(out2)); // I/O order is not important!x_gate name2 (.out(out1), .in[3](m[3]), .in[2](m[2]), .in[0](m[0]), .in[1](m[1]));

endmodule

Modules that do not need instantiations

and nandor norbuf notxor xnor

Verilog primitives DO NOT need instantiations!

Ex: Full Adder

s =a b cincout = ab + cin (a + b)

a

b

cin

node1

node4node3

node2


3/32

module full_adder( s, cout, a, b, cin);

output s, cout;input a, b, cin;xor (node1, a, b); // no module name is necessary

xor (s, node1, cin);and (node2, b, a);or (node3, a, b);and (node4, cin, node3);or (cout, node2, node4);

endmodule

Test Fixture

module testfixture_name;

// all inputs are declared with reg_statement

// full adder instancefull_adder name1 (.s(sum), .a(in1), .b(in2), .cin(carryin), .cout(carry_out));

// stimulus

// display results

endmodule

cin

a

b

s

cout

FA

sum

carry_out

carry_in

in1

in2


4/32


5/32

$time, $monitor for displaying results

$time // Displays the current simulation time$monitor // Displays the variable value whenever the variable value changes

Ex:

$monitor ($time, output, input1, input2);$monitor ($time, ,output, input1, input1, input2); //space between time & output during display$monitor ($time, output=%h input=%b, out, in);

Thus,

module testfixture_name;reg carry_in, in1, in2;full_adder name1 (.s(sum), .cout(carry_out), .a(in1), .b(in2), .cin(carry_in));

initialbegin...end

initial//only 1 statement in a procedural block, does not need being-end statements$monitor( $time, ,in1=%b in2=%b carry_in=%b carry_out=%b sum=%b,

in1, in2, carry_in, carry_out, sum);endmodule

Displaying waveforms

signalscan is the verilog XL waveform display tool. Signalscan& opens up the waveform tool. One hasto create a database & specify the signals to be able to use signalscan.

In testfixture.v

Module testfixture;...//Display resultsinitial$monitor($time);

// Display waveform


6/32

initialbegin

$shm_open(full_adder.shm);$shm_probe(AC); // All nodes are probed

end

endmodule

Verilog Software

Verilog can be started as:

Verilog full_adder.v testfixture.v

or create run.f : full_adder.v, testfixture.v

Verilog f run.f

Comments in Verilog

Single line comment:

//

multi-line comment:

/*

*/

Strings

\t -> tab \n -> new line

Ex:

$monitor ($time \t, in1= %b out=%b, in1, out \n);// \n new line, not really necessary here// \t tab, leaves open space


7/32

Numbers in verilog

size: # of bits

base: binary, decimal, hexadecimal, octal

Ex:

32h3c -- 32-bit hexadecimal 3c ( x 00_00_00_3c)8b1 -- 8-bit binary 1 (0000_0001)

64e-3 -- 64x10-3=0.064

120E1 -- 120x101=1200h8a -- unsized hexadecimal 8a (x 00_00_00_8a)b1 -- unsized binary 18bz -- 8-bit binary z (zzzz_zzzz)

4bx -- 4-bit binary x (xxxx) // x values are automatically extended

Compiler directives

`timescale ns / psns / nsps / psus / us

Ex:

`timescale 1ns/100ps // 100ps is simulation accuracy. Simulation goes through 10 stepsmodule inverter (out, in);

output out;input in;not #1 (out,in);

endmodule

Ex:

`timescale 100ps/10psmodule inverter (out, in);

output out;input in;not #3 (out,in);

endmodule


8/32

define

`define #or < parameter 2>

.

..` ..

Ex:

`timescale 100ps/10ps`define inv_delay #3 // 300psmodule inverter (out, in);

output out;input in;

not ìnv_delay (out,in);endmodule

include

ìnclude //includes into the present file for simulation

Ex:

ìnclude /lab1/full_adder.v`timescale 100ps/10ps`define inv_delay #3module inverter (out, in);

.

.

.endmodule

* Here, we include full_adder.v in a different directory system into inverter module.


9/32

parameters

parameter =value;

Ex:

module alu (out, in1, in2);parameter BUS=31;output [BUS:0] out;input [BUS:0] in1, in2;...

endmodule

Basics of Structural Modueling

(a) Primitives supported by Verilog XL:and nandor norbuf notxor xnor

nor (out, in1, in2, in3);

in3in2

in1

out

buf (out,in);

in out

and (out,in4,in3,in2,in1);

in4

in3in2

in1

out


10/32

(b) Conditional primitives supported by Verilog XL:

bufif1

in out

en

if en=1 then out=inelse out=z(floats)

bufif1(out, in, en)

bufif0

in outen

if en=0 then out=inelse out=z

bufif0(out,in,en);

Name $ delay attributes to nonconditional/conditional prims

and and3 (out, in1, in2, in3);nor #3 (out, in1, in2);xor #2.1 (out, in1, in2);

Multiple outputs

Multiple outputs from a gate is NOT supported by Verilog XL.

Ex:

not #100 not1 (out1, out2, out3, in); // No Way!

inout2out1

out3


11/32

not #100 not1 (out, in); // correct

inoutout

out

Module instantiation

module gate (out, a, b, en);output out;input a, b, en;...

endmodule

Option 1

module alu (out, in1, in2);output[3:0] out;input[3:0] in1, in2;gate #(100:120:150) gate1 (out1, m, n, control); // delay (min:type:max)...

endmodule

Option 2

module alu (out, in1, in2);...gate #100 gate1 (.out(out1), .en(control), .b(n), .a(m)); //no port order!..

.endmodule


12/32


13/32

8-bit register

in2 in1

D

Q

out[7]

data[7]

in2 in1

D

Q

out[6]

data[6]

in2 in1

D

Q

out[0]

data[0]

sel_data

2-1 mux

in2

in1

selb

node1

node2

out

sel

Flip-Flop

d

clock

clock

node1 node2 node3 node4

nodec

q

clock


14/32

Display Control

Rise delay/ fall delay and specify block

nand #(10, 15) (out, a, b) //#(rise delay, fall delay)

Tbr,Tbf

Tar,Tafa

bout

Tar = Tbr = #10Taf = Tbf = #15

However in reality TarTbr, TafTbf

Therefore, one use block to describe delays.specify..endspecify

Ex:nand (out, a, b);specify

(a => out) = (10, 15); // rise delay = 10, fall delay = 15(b => out) = 9; // rise delay = fall delay = 9

endspecify

nand (out, a, b);specify

(a =>out) = (9:10:11, 14:15:16); //rise_delay(min:t:max)=9:10:11//fall_delay(min:t:max)=14:15:16

(b =>out) = (8:9:10); //rise_delay=fall_delayendspecify


15/32

Ex: Bus access

bus

read_outread_in

in out

for bufferTr = 200psTf = 100ps

for inverterTr = 100psTf = 50ps

`timescale 10ps/10psmodule bus_access (bus, out, in, read_in, read_out);

output out;input in, read_in, read_out;

inout bus;

bufif1 (bus, in, read_in);notif1 (out, bus, read_out);

specify(in => bus) = (20, 10);(bus => out) = (10, 5);

endspecifyendmodule

Ex:

gate

8 8

8

out[7:0]

in2[7:0]in1[7:0]

Trfromin1toout1ns

Tffromin1toout800ps

Trfromin2toout1.2ns

Tffromin2toout1ns


16/32

`timescale 100ps/10psmodule gate (out, in1, in2);

output[7:0] out;input[7:0] in1, in2;

specifyspecparam Tr1=10, Tf1=8, Tr2=12, Tf2=10;(in1[7:0] => out [7:0] ) = (tr1, tf1);(in2[7:0] => out [7:0] ) = (tr2, tf2);

endspecify

endmodule

Timing checks (Setup/hold time definitions)

valid datadata

clock

Tsetup Thold

Setup check

reg notifier;.

.$setup (data, reference, Tsetup, notifier); // notifier is a flag which comes up

// every time violation occurs.

Ex:

specify$setup (data, posedge, clock, 10, notifier);

endspecify

Hold check

reg notifiers;..$hold (reference, data, Thold, notifier);


17/32

Ex:

specify$hold (posedge clock, data, 12, notifier);endspecify

One can check the setup and hold in the same statement

reg notifier;$setuphold ( reference, data, Tsetup, Thold, notifier);

Ex:

specify$setuphold (posedge clock, data, 10, 12, notifier);

endspecify

Timing Attributes to register_8.vff.vmux_21.v

Declare

in1 in2

out

(in1,in2,sel=>out)

rise fall

max=500ps400ps

type=400ps300ps

min=300ps200ps

sel

Declare

clock

qd(clock=>9)

rise fall

max=900ps 800ps

type=700ps 600ps

min=600ps 500ps


18/32

register_8.v

clock.v

data

sel_data

clock

sel

test.vin

outclock

out

8

8

Behavioral Modeling

1. Procedural blocks.a. initial @ (condition) // one time shot!

begincondition1 statement1;condition2 statement2;..

end

b. always @(condition) //loop!

begincondition1 statement1;condition2 statement2;..end


19/32


20/32


21/32

Ex

Z=1011X=0110

~Z= 0100Z&X= 0010Z~|X= 0000

Ex

A= 4 b1101B= 8 b 01110101

sign extend A A=8b0000_1101A&B=0000_0101

3. Conditional statements

start procedural blockbeginif (condition1)

if( condition2)if(condition3)

statement3else condition4

else statement5else

if(condition 6)statement6

else statement7end

Note: (condition) could contain may parameters and operators

Ex( a


22/32

Ex

procedure blockbeginif ( a> 0)

if (x


23/32

Ex:

module mux_n (out, sel, in1, in2, in3);output out;input in1, in2, in3;

input [1:0] sel;reg out;

always @ (sel or in1 or in2 or in3)case (sel)2b00: out=in1; // out must not change until one of the inputs changes, thus out is a reg2b01: out=in2;2b10: out=in3;2b11: out=1bx;endcase

endmodule

Ex:

module mux_alu (out, opcode, a, b);output [7:0] out;input [7:0] a, b;input [1:0] opcode;`define XOR 2b00 //no; here`define SHIFT 2b01`define ADD 2b10`define ZERO 2b11reg[7:0] out;

always @ (opcode or a or b)case (opcode)`XOR: out = a^b;`SHIFT: out = a


24/32

5. Loop statements

a. for_statement

procedural block

for ( i=start; i


25/32

Ex:

module split (out1, out2, we, re, out);

output [3:0] out1;

output[1:0] out2;output we, re; // write-enable, read enableinput [7:0] out;wire [3:0] out1= out [7:4];wire [1:0] out2=out [3:2];wire we= out[1] & out[0;wire re= out[1] | out[0];

endmodule

b. Conditional Operator

en

outin

wire out;assign out= en? in: 1bz;

a

c

b out

sel

wire out;assign out= (sel==2b00) ? a:

(sel == 2b01) ? b:c;


26/32

Ex:

module mux_21 (out, in1, in2, sel);

output [7:0] out;

input [7:0] in1, in2;input sel;wire [7:0] out;assign out= sel ? in1: in2;

endmodule

possible?

module mux_21 (out, in1, in2, sel);

output [7:0] out;input [7:0] in1, in2;input sel;wire [7:0] out=sel? in1:in2;

endmodule

too long!

reg [7:0] out;always @ (in1 or in2 or sel0casex (sel)1b0: out=in2;1b1: out=in1;default:

beginout=8bx;$display(out of order);end

endcase


27/32

Memory Modeling

a. Memory declaration

memory

x 1

y

1

reg[x:1] memory [y:1];

fifo

7 015

0

reg[7:0] fifo [15:0];

b. Memory addressing

fifo

7 0

15

0

msb 7

.

.input [3:0] addr;reg[7:0] fifo[15:0];

reg[7:0] slice;slice = fifo [addr];reg msb, lsb;msb=slice [7];lsb=slice [0];...


28/32

c. Modeling a memory

fifo

7 015

0

were

data[7:0]

addr[3:0]

clk

module fifo (data, addr, we, re, clk);input [7:0] data;input [3:0] addr;input we, re, clk;reg[7:0] fifo [15:0];reg[1:0] state;reg[7:0] data;

always @ (posedge clk)

state={we, re};case (state)

2b00: data= 8bz;2b01: data= fifo[addr];2b10: fifo[addr]=data;2b11: $display(Error;default: data=fifo[addr];

endcaseendmodule


29/32

d. Loading memory array

Memory is always loaded by a text file.

$readmemb (memdata.load, fifo, , ); //binary file

$readmemh (memdata.load, fifo, , ); //hexadecimal file

Ex:

$ readmemh(text.load, fifo, 6, 4 );

72fc

10104a8b

15

0

15 0

6

54


30/32

Ex: Another memory definition31 0

15

0

32

8

32

ByteEn[3:0]

we3 2 1 0

clk

Addr[3:0]

re

DataIn

DataOut

module fifo (DataOut, DataIn, we, re, ByteEn, Addr, clk);output [31:0] DataOut;input [31:0] DataIn;input [3:0] Addr, ByteEn;input re, we, clk;

reg[31:0] temp;reg[31:0] fifo [15:0];

always @ (posedge clk)if (we)

begintemp=fifo[Addr];casex (ByteEn)

4b0001: temp[7:0] =DataIn[7:0];4b0010: temp[15:8] =DataIn[15:8];4b0011: temp[15:0] =DataIn[15:0];4b0100: temp[23:16] =DataIn[23:16];4b0101: begin

temp[23:16] =DataIn[23:16];temp[7:0] =DataIn[7:0];

end..

4b1111: temp[7:0] =DataIn[7:0];default: begin

temp[31:0] =32bx;$display (No bytes enabled);

endendcase

fifo[Addr]= temp;


31/32

else if (re)DataOut= fifo[Addr];

elseDataOut= 32 bz;

endmodule

ALU representation

b

Aluout

opcode

ALU

a

opcode ALU

0000 ADD A+B0001 SUB A-B

0010 ADDI A+B(imm)0011 SUBI A-B (imm)0100 AND A&B0101 OR A|B0110 XOR A^B0111 MUL A*B ( A and B are 16 bit products)1000 LD A+B (imm)1001 STO A+B (imm)1010 SHL AB (imm)1100 BEQ NOP

1101 BNE NOP1110 JAL NOP1111 RET NOP


32/32

//structural code`timescale 100ps/10psmodule d_flop_reset (q, reset, d, clk);

output q;input reset, d, clk;

notif0 i1 (out1, d, clk);not i2 (in1, out1)nand i3 (out1, reset, in1);bufif1 i4 (out2, in1, clk);not i5 (in2, out2);nor i6 (out2, resetb, in2);not i7 (resetb, reset);not i8 (q, in2);

specify

(reset => q) = (4, 3.5);(clk => q) = (4.5, 4);endspecify

endmodule

Cmpe 125 Verilog Notes

Documents

Transcript of Cmpe 125 Verilog Notes