Cmos Scaling R&D

Master Thesis/Internship Topic Guide 2012-2013

Master Thesis/Internship Topics 2012-2013

Information..........................................................................................................................................................................................1

I. CMOS Scaling R&D ................................................................................................................. 2

Defect characterization of hetero-epitaxial III-V layers for future high-performance sub-16 nm CMOS transistors .................................................................................................................................................................................... 2

Random Telegraph Noise (RTN) and the ITRS Roadmap: is it the beginning of the end? ..................................... 3

Deposition and characterization of dielectric barrier films ............................................................................................ 4

Using variational calculus to solve Poisson's and Schroedinger's equations self-consistently within a single loop: how far can we go? ......................................................................................................................................................... 5

Parallelization of CMOS time-dependent variability measurements............................................................................. 6

Modeling of leakage in very high permittivity dielectrics for DRAM applications ..................................................... 7

Low damage etch: use of CF3I as reactant for patterning of 2.0 porous SiOCH materials .................................... 8

Post-etch ULK restoration strategies: effect of H2-CH4-based plasma treatments on dielectric recovery of 2.0 porous SiOCH materials .............................................................................................................................................. 9

Plasma treatments of model polymers used in EUV lithography: PS and PMMA .................................................... 10

ESD reliability of high mobility FinFET devices for sub-14 nm CMOS ....................................................................... 11

Evaluation of photoresist outgassing for extreme ultraviolet lithography ................................................................ 12

Methodologies for memory analysis using C-AFM .......................................................................................................... 13

Carbon nanotube contacts: electrical characterization of CNT Cu damascene contacts ................................ 14

Graphene synthesis and characterization .......................................................................................................................... 15

Growth of carbon nanotubes for future generations of interconnects ..................................................................... 16

Atomic layer deposition for applications in nanotechnology ....................................................................................... 17

XRD study of nano-structured hetero-epitaxial III-V compound semiconductors for VLSI CMOS applications ................................................................................................................................................................................ 18

Developing in-situ doping of III-V compound semiconductors by hetero-epitaxial MOCVD growth .............. 18

Surface preparation and interface passivation of high mobility channel materials for beyond 14 nm technology nodes ..................................................................................................................................................................... 19

Development of a fixed ramp rate breakdown voltage procedure for gate dielectric testing ............................ 20

Electrical evaluation and reliability assessment of local interconnects....................................................................... 20

Investigation of advanced resistance-switching (RRAM) memory cells ..................................................................... 21

Investigation and optimization of the electrical switching properties of Conductive Bridging RAM memory cells (CBRAM) ......................................................................................................................................................... 22

Passivation of Ge for high-performance applications ..................................................................................................... 23

Graphene: device fabrication and characterization ......................................................................................................... 24

Graphene: device fabrication for optoelectronics ........................................................................................................... 25

Characterization of ohmic contacts to high-mobility materials (Ge, III-V) ............................................................... 26

Spin transfer torque magnetic random access memory ................................................................................................ 27

Wet processing of high aspect ratio nanostructures...................................................................................................... 28


Surface chemistry of III-V semiconductors for cleaning applications ......................................................................... 29

The creation of nanoforces by microbubbles ................................................................................................................... 30

Galvanic corrosion in micro-bump with different bumping metallurgy ..................................................................... 31

Direct heteroepitaxy of III-V semiconductors on silicon mediated by strain-relaxed buffer layers .................. 32

3D FIB/SEM structural analysis of nano-electronic devices .......................................................................................... 33

Carrier depth profiling with micro-probes on advanced ultra-shallow high-mobility CMOS semiconductor structures ................................................................................................................................................................................... 34

Development of a professional data analysis package for the micro-four point probe (M4PP) .......................... 35

Development of an industrial analysis-package in Visual C++ for SSRM-measurements ...................................... 36

Development of probes for nanoscale electrical measurements and manipulation in a nanoprober system ......................................................................................................................................................................................... 37

Diamond probes more efficient and optimized yield assessment .......................................................................... 38

Advanced materials characterization using ion beam scattering ................................................................................. 39

Ultra high vacuum SSRM nanocontact modeling - Electrical and mechanical impacts of low temperatures (70K) ........................................................................................................................................................................................... 40

Atomic Layer Deposition of ultrathin metal films for advanced nanoelectronic applications ............................. 41

In-situ molecular beam passivation of III-Sb compounds ............................................................................................... 42

Developing in-situ doping of III-V compound semiconductors by hetero-epitaxial MOCVD growth ................ 42

Effect of confinement and position of dopants on the ionized impurity scattering limited mobility in a few-dopant double gate junctionless FET or all-around gate cylindrical nanowire junctionless transistor ...... 43

Characterization and modeling of the junctionless III-V nanowire for novel device applications ..................... 44

Remote Coulomb, surface roughness and ionized impurity scattering in novel nanowire all-around gate FET devices ................................................................................................................................................................................ 45

Symbolic analysis of logic cells for advanced technologies ............................................................................................ 46

II. CMORE ................................................................................................................................... 47

Design and modeling of a single sensor 3-axis gyroscope for IMUs (inertial measurement units) .................... 47

Capacitive micromachined ultrasound transducers for imaging, telecom and power transmission applications ................................................................................................................................................................................ 48

(NANO)PHononicS: MEMS/NEMS acoustic devices and circuits ............................................................................... 49

Nano relays and logic gates: designing at the nanoscale, in presence of nano adhesion forces .......................... 50

MEMS-based loudspeaker ...................................................................................................................................................... 51

III. Smart Systems ....................................................................................................................... 52

Measurement and calibration of models for advanced photovoltaic modules ......................................................... 52

Life-time measurements and modeling of organic photovoltaic solar modules....................................................... 53

Machine learning on low power parallel architectures .................................................................................................. 54

Algorithm and architecture co-optimizations for cost and power constrained Signal processing system ....... 55


Complexity modeling and algorithm transformations for software defined radios ................................................ 56

Collaborative spectrum sensing for cognitive radios ...................................................................................................... 57

Development of integrated passives for cellular duplexer module in CMOS .......................................................... 58

Analog signal processing for medical signals ..................................................................................................................... 59

Radio-frequency communication with metal-oxide electronics on plastic ............................................................... 60

IV. HUMAN++ .............................................................................................................................. 61

Light up your brain - An intracranial communication network ................................................................................... 61

Towards a non-linear time-varying I-V model for biomedical stimulation electrodes ........................................... 62

Investigating the long term behavior of TiN as electrode material for cell interfacing technologies ................ 63

Localized electrical stimulation of in vitro neurons for guided growth ..................................................................... 64

Signal analysis of recorded electrical activity by advanced microelectrode arrays ................................................. 65

Improving the function, stability, and biocompatibility of carbon nanotube microelectrodes for neuro-electronic applications ............................................................................................................................................................ 66

Development of a test system for standards-compliance measurements for biopotential amplifiers ............... 67

Study of effects of thinning & design of test structures for analog chips ................................................................... 67

Signal processing algorithms for a neuronal interface chip ........................................................................................... 68

Data acquisition system for integrated cell interfacing systems .................................................................................. 68

V. Energy...................................................................................................................................... 69

Degradation mechanisms in organic solar cells ................................................................................................................ 69

Solving the Caldeira-Leggett model with balance equations ......................................................................................... 70

Modeling ionic diffusion in solid-state materials for energy storage applications.................................................... 71

Bonding of cells to glass for next-generation c-Si PV modules .................................................................................... 72

Radio-frequency communication with metal-oxide electronics on plastic ............................................................... 73

Metal contacts for amorphous Si solar cell applications ................................................................................................ 74

Morphological control of organic bulk solar cells ........................................................................................................... 75

Spectral characterization of organic tandem solar cells ................................................................................................. 76

Tunneling barriers for the passivation of metal contacts in silicon solar cells ......................................................... 76

Development of amorphous silicon deposition for silicon heterojunction solar cells........................................... 77

CIGSSe and CZTSSe films formation from selenization/sulfurization of metals and chalcogenide compounds ................................................................................................................................................................................ 78

Optimization of the optical properties of the layers in a multi-junction solar cell ................................................. 79

Hydrogen generation with III-Nitrides and catalysts ...................................................................................................... 80

Novel semiconductor alloys for optoelectronics of the future ................................................................................... 80

Electrical characterisation of amorphous Si layers for solar cell applications .......................................................... 81

Characterization and power-loss analysis of interdigitated back contact (IBC) silicon solar cells ..................... 82


Reliability testing of c-Si solar cells with Cu plated metallization ................................................................................ 83

Copper contact plating for advanced solar cell contacts .............................................................................................. 83

EBIC analysis of thin-film polycrystalline-silicon solar cells ........................................................................................... 84

Raman and EDS analysis for thin-film solar-cell applications ........................................................................................ 85

Organic solar-cell material characterization by TOF-SIMS ........................................................................................... 86

Characterization of organic materials using UHV conductive AFM at low temperatures .................................... 87

Characterization and modeling of Back-surface field formation in Si-based solar cells ......................................... 88

Initiation of random pyramid formation: impact of contamination and surface roughness .................................. 89

VI. INVOMEC ............................................................................................................................... 90

Visualisatie van DfX analyse feedback in een elektronisch ontwerp .......................................................................... 90

Pre-routing metal layer estimation ...................................................................................................................................... 91

VII. NERF........................................................................................................................................ 92

Studying the function of neural circuits .............................................................................................................................. 92

Design, prototyping and testing of miniaturized brain implants .................................................................................. 93

1


Information

Students from universities and engineering schools can apply for a master thesis and/or internship project at imec. Imec offers topics in engineering and (industrial) sciences in different fields of research.

The topics are arranged according to the imec business programs. You can find more detailed information on each research program under the heading Research on www.imec.be.

How to apply?

Send an e-mail with your motivation letter and detailed resume to the responsible scientist(s) mentioned at the bottom of the topic description of your preference. The scientist(s) will screen your application and let you know whether or not you are selected for a project at imec.

It is not recommended to apply for more than three topics.

For more information, go to the Internship and Master Thesis pages under the Education heading on our website.

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I. CMOS Scaling R&D

Defect characterization of hetero-epitaxial III-V layers for future high-performance sub-16 nm CMOS transistors

As the silicon device scaling for future generations becomes increasingly difficult, alternative device structures and high mobility channel materials like Ge (P-type), InGaAs (n-type), InSb have gained popular research interests. However owing to high cost of III-V or Ge wafers, the active layers are proposed to be deposited epitaxially on silicon substrates. This presents itself as a challenge: due to the large lattice mismatch between Si and Ge or III-V materials, a high density of extended defects like misfit and threading dislocations, stacking faults, twins is created. Furthermore, the deposition of polar III-Vs on non-polar Si creates additional defects like polar and anti phase domains. It has been studied that these defects acts as non-radiative recombination centers and limits the electrical transport of carriers in the device. Therefore, it is important to characterize these defects on the basis of extent of performance degradation caused by them in the CMOS devices. Subsequently, based on these studies it is desired to introduce variants in the growth strategies to mitigate the harmful effects or completely eliminate them.

The focus of this internship/thesis would be to study the electrical properties of p-n junction diodes containing extended defects, fabricated under different processing conditions. This would be done by measuring Current-Voltage (I-V) and Capacitance-Voltage(C-V) characteristics. Temperature dependent measurements can also be carried out. The information about the generation and recombination lifetime, ideality factor, activation energy can be extracted from these measurements which in turn indicate the dominant mechanism (Shockley-Read-Hall, Field Assisted Tunneling) in the devices.

Additionally, defect characterization which involves identifying and classifying the defects can also be performed using facilities available at IMEC in close collaboration with its industrial partners.

Type of project: Thesis/internship of 3-4 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science, physics, electronics.

Responsible scientist(s): For further information or for application, please contact Eddy Simoen ([email protected]) and Somya Gupta ([email protected]).

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Random Telegraph Noise (RTN) and the ITRS Roadmap: is it the beginning of the end?

Low-frequency noise is present in all physical, electronic, biological and even societal systems and is for most experimentalists a source of error. However, it can also provide fundamental information on the basic transport mechanisms through a semiconductor device, for example. Flicker noise or 1/f noise appears to be universal in most large systems but breaks down when the dimensions reach the nanoscopic level. In the case of a MOSFET, it is believed that trapping and de-trapping of charge through many defect states is at the origin of the 1/f noise. When scaling the device dimensions to the sub-micrometer area, the number of active traps reduces, so that eventually, only one or a few traps are active and determine the charge transport fluctuations. In practice, this means that for a small-area device, the current through the channel can switch between a high and a low state, which is called Random Telegraph Noise (RTN). As the occurrence of a trap and associated RTN is a random process, this may give rise to significant variation from device to device. As such, RTN is a source of temporal device variability and may form a performance limitation for 16-nm and below CMOS memories. It is the aim of the work to study the low-frequency noise and RTN behavior of advanced CMOS technology devices and to investigate the possible impact of various process options. At imec, there is a computer-controlled noise measurement system, combined with a 300 mm probe station, allowing a detailed analysis in function of the gate and drain voltage. As RTN traps may also affect the mobility by scattering, a correlation with other device parameters, like the threshold voltage and the mobility will be looked for. It is also possible to study the RTN and noise behavior as a function of temperature. This enables the determination of the thermal activation of the emission and capture processes underlying the RTN and noise and provides information on the trap level energy and capture cross section. In a way, RTN allows for trap spectroscopy in small systems. As there is more and more interest from the industry, this work will be performed in close collaboration with the imec industrial Partners.

Type of project: Thesis of 3 months. Degree: Master in Science or Master in Engineering majoring in e.g. device physics. Responsible scientist(s): For further information or for application, please contact Eddy Simoen ([email protected]).

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Deposition and characterization of dielectric barrier films

In copper interconnect technology, typically SiCN films are deposited in-between the low-k dielectric layers, serving at the same time as a etch stop layer, dielectric Cu barrier, and moisture barrier. Driven by the continuing scaling, requiring a lower overall k-value of the dielectric stack, alternative materials are investigated. These should have a lower k-value than SiCN, while maintaining the barrier and etch stop properties, or have similar properties at a lower thickness. In this project, the deposition process window is screened for a certain precursor, varying process conditions, based on literature research. This involves extensive characterization of the deposited films, starting with the determination of thickness, refractive index, chemical composition through FTIR, stress, Youngs modulus, hardness, porosity, hydrophilicity, dielectric constant, and leakage of the films. For the most promising films, a second series of tests which simulate other (former and later) process steps, is performed; this also includes tests to determine the adhesion to other films, mainly by 4 point bending analysis. Also, a more detailed chemical analysis, e.g. through XPS and TOFSIMS, will be performed. If all tests are positive, finally, the material is used in an integration process, resulting in a real test chip and the final electrical characterizations (including reliability characterizations) are made. The student will be strongly involved in both the actual deposition of the films and the detailed characterization of the basic film properties. Hereby (s)he will use state of the art equipment, such as an industrial PE-CVD reactor, ellipsometers, a Fourier Transform Infrared spectrometer, a high precision mass measurement system, and others. Furthermore (s)he will also be involved in the next phase of the characterization cycle, as setting up the processes for the simulation of integration aspects and the electrical characterization on test chips. Also, the student can be involved in setting up a practical test procedure to measure Cu barrier properties. Academic and industrial results will be reported in meetings where both imec staff and industrial affiliates participate.

Type of project: Thesis or internship of minimum 5 months, to start in 2013. Degree: Master in Science or Master in Engineering majoring in material science, physics, electronics. Responsible scientist(s): For further information or for application, please contact Els Van Besien ([email protected]).

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Using variational calculus to solve Poisson's and Schroedinger's equations self-consistently within a single loop: how far can we go?

Transport calculations for modern semiconductor devices heavily rely on the local charge distribution and the related electrostatic potential established inside a device structure. As such, one is bound to solve the Schroedinger equation self-consistently with Poisson's equation and a number of constitutive equations relating the electron and hole concentrations to the wave functions of the quantum states and their occupancies. Designing appropriate numerical code to deal with this task, one is immediately faced with a significant computational burden due to the highly non-linear and non-local dependence of the charge density on the potential. Moreover, the necessity of feeding back the charge density into the module that solves Poisson's equation is reflected in the conventional, double loop that handles the fully self-consistent solution. Recently, an efficient but non-linear variational principle has been developed that provides a simultaneous solution of all equations involved, while being carried out merely within a single loop that minimizes a proper action functional. So far however, the necessary condition that the charge density be a local functional of the potential, has restricted the application of the principle to cases where the adiabatic approximation or local density approximation leads to an acceptable description of the quantum mechanical charge density. The purpose of this thesis is to work out the non-linear variational principle for a number of simple test structures (e.g. planar and/or double-gate MOS capacitors) and to explore any possible extension of the variational calculus beyond the local density approximation.

Type of project: Thesis of 8 months. Degree: Master in Science majoring in physics. Responsible scientist(s): For further information or for application, please contact Wim Magnus ([email protected]) and Bart Soree ([email protected]).

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Parallelization of CMOS time-dependent variability measurements

It is well established that with the size of CMOS devices decreasing to atomic dimensions, the number of dopant atoms in each device reduces to numerable levels, resulting in increased time-zero (i.e., as-fabricated) variability. At the same time also the number of defects is decreasing to literally single-digit numbers, resulting in further variability increase with time (i.e., increased time-dependent variability and thus, further reduced reliability). This trend has recently lead to a shift in our perception of reliability: the top-down approach (deducing the microscopic mechanisms behind the average degradation in large devices) is being replaced in deeply-scaled devices by the bottom-up approach, in which the time-dependent variability is understood in terms of individual defects. The small ensembles of stochastically behaving individual defects are then responsible for the wide time-dependent distributions of CMOS device parameters. Understanding these distributions requires electrical measurements on a large number of devices, necessitating in turn parallel evaluation schemes. The thesis project will build on a previously-designed on-chip array for parallel device stressing and testing. Programming of the measurement instruments and the computer-controlled prober will be needed, followed by statistical analysis of the data, and optionally, designing improved on-chip circuitry. The required skills include computer programming (Perl), performing electrical measurements and data analysis, and optionally SPICE, and CAD layout. Type of project: Thesis possibly with internship of minimum 6 months. Degree: Master in Science or Master in Engineering majoring in electrical engineering, physics, nanotechnology, material sciences. Responsible scientist(s): For further information or for application, please contact Ben Kaczer ([email protected]) and Jacopo Franco ([email protected]).

7


Modeling of leakage in very high permittivity dielectrics for DRAM applications

Future dynamic random access memories (DRAM) require metal-insulator-metal capacitors (MIMcaps) with equivalent oxide thicknesses (EOT) 0.4 nm, necessitating the introduction of dielectrics with very high dielectric constant (k~100). Furthermore, low leakage current densities ( 10-7 A/cm2) are required for sufficient retention of charge. Regrettably, high-throughput industrial deposition techniques can result in dielectric films with defects that can facilitate electronic conduction. Reducing the leakage thus requires thorough understanding of the role of the defects. The general aim of the thesis is to interpret the measured leakage and capacitance characteristics (IV and CV at varying temperature). This will be achieved by modeling trap-assisted leakage mechanisms in MIM structures with non-uniform electric field due to charge trapped inside the dielectric. Requirements therefore include understanding of the physics of various conduction mechanisms, self-consistent solving of the Poisson equation, and optionally electrical IV and CV measurements. Type of project: Thesis possibly with internship of minimum 6 months. Degree: Master in Science or Master in Engineering majoring in electrical engineering, physics, nanotechnology, material sciences. Responsible scientist(s): For further information or for application, please contact Ben Kaczer ([email protected]).

8


Low damage etch: use of CF3I as reactant for patterning of 2.0 porous SiOCH materials

In order to cope with device scaling, inter-line crosstalk and interconnect delays, chip manufacturers are introducing since a few years low dielectric constant materials (low-ks) as insulating material separating conducting Cu lines. Currently, targeted k values for 2016 are of the order to 2.0 and below, to be compared with 4.2 for bulk SiO2 (reference dielectric for the semiconductor industry). In order to achieve such low k value, Si-based CVD materials are favored, where methyl groups are introduced (less polarizables) together with substractive porosity. Those materials are referred as p-SiOCH, hybrid dielectrics, or organo-silicon glass (OSG). Current state-of-the-art synthesis methods allow to reach k values ~ 2.0, with porosity ~ 45% and average pore size ~ 2.4nm. Recent studies indicate that those materials can be damaged by plasma processing, leading to methyl group suppression and loss of hydrophobicity. An option to overcome this issue is to use new plasma chemistries, where the damaging component has been reduced. One possibility is to replace the conventional fluorocarbon CF4 molecule by trifluoroiodomethane CF3I1

Type of project: Internship or thesis with internship of approx. 6 months full-time.

. The objective of this work-package is to evaluate the efficiency of this solution for plasma etching of a 2.0 porous OSG material, in comparison with conventional CF4-based chemistries. Starting from pristine blanket low-k films, the vertical damage caused by plasma processing will be evaluated as a function of various important processing parameters (plasma power, composition, RF driving frequency, pressure, time). Bulk k-value will be evaluated, as well as structural modifications caused by plasma exposure. Possibly, pattern tests will be conducted as well, in order to estimate the degree of damage reduction in the transverse direction (parallel to the wafer surface). Techniques for such a study would be broad and represent a significant part of the stay: deep understanding of etch tool usage, film characterization (ellipsometry for thickness-n&k, FTIR or ATR-FTIR for bulk composition, WCA for film hydrophobicity, k-value extraction by C-V measurements on metal dots). More specific material characterization (XPS, AFM, TOF-SIMS etc...) may be used.

Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material sciences, physics, chemistry, electronics. Responsible scientist(s): For further information or for application, please contact Jean-Francois de Marneffe ([email protected]), Laurent Souriau ([email protected]) and Mikhal Baklanov ([email protected]).

1 E. Soda, S. Kondo, S. Saito, Y. Ichihashi, A. Sato, H. Ohtake and S. Samukawa, J. Vac. Sci. Technol. B 26, 875 (2008)

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Post-etch ULK restoration strategies: effect of H2-CH4-based plasma treatments on dielectric recovery of 2.0 porous SiOCH materials

In order to cope with device scaling, inter-line crosstalk and interconnect delays, chip manufacturers are introducing since a few years low dielectric constant materials (low-ks) as insulating material separating conducting Cu lines. Currently, targeted k values for 2016 are of the order to 2.0 and below, to be compared with 4.2 for bulk SiO2 (reference dielectric for the semiconductor industry). In order to achieve such low k value, Si-based CVD materials are favored, where methyl groups are introduced (less polarizables) together with substractive porosity. Those materials are referred as p-SiOCH, hybrid dielectrics, or organo-silicon glass (OSG). Current state-of-the-art synthesis methods allow to reach k values ~ 2.0, with porosity ~ 45% and average pore size ~ 2.4nm. Recent studies indicate that those materials can be damaged by plasma processing, leading to methyl group suppression and loss of hydrophobicity. An option to overcome this issue is low-k restoration, i.e. add a processing step after plasma etch, that would repair the damaged material (attach new CH3 groups and restore hydrophobicity of the surface). Currently, we are considering the use of soft plasma processes at low temperature, based on H2, CH4 and additives. Starting from in-situ damaged low-k films (after etch with 2 typical chemistries, Ar-CF4-based and N2-CF4-based), the objective of the work-package will be to screen various important process parameters (plasma power, composition, RF driving frequency, pressure, time), and characterize the level of bulk k value recovery and material structural modifications. Techniques for such a study would be broad and represent a significant part of the stay: deep understanding of etch tool usage, film characterization (ellipsometry for thickness-n&k, FTIR or ATR-FTIR for bulk composition, WCA for film hydrophobicity, k-value extraction by C-V measurements on metal dots). More specific material characterization (XPS, AFM, TOF-SIMS etc...) may be used. The work-package would also include the optimization of a damage-less photoresist strip process.

Type of project: Internship or thesis with internship of approx. 6 months full-time. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material sciences, physics, chemistry, electronics. Responsible scientist(s): For further information or for application, please contact Jean-Francois de Marneffe ([email protected]), Laurent Souriau ([email protected]) and Mikhal Baklanov ([email protected]).

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Plasma treatments of model polymers used in EUV lithography: PS and PMMA

Nowadays, nano-patterning is facing two main challenges, closely linked together: scaling (dimension reduction) and line-width roughness (LWR), i.e. sidewall roughness appearing in course of the etch sequence. Advanced lithography makes use of EUV photo-resist, which is patterned by 13.6nm light. This photo-resist is composed of two main polymers, PS and PMMA, together with attached groups for protection and de-protection (PAG = photo-acid generator). Currently, a lot of progress is being made on LWR by performing pre-etch plasma treatments based on H2. However the precise mechanism of LWR improvement remains not well understood, especially which photo-resist component is responsible for LWR. In order to clarify this, we propose to study the effect of plasma treatments (H2, Ar, HBr, He-H2 mainly) on model polymers used in EUV photo-resist, i.e. PS and PMMA. The objective of the work-package is to perform various plasma treatments (varying plasma power, bias, composition, exposure time) on PS and PMMA thin films, then perform an in-depth characterization of the processed films, including ellipsometry (thickness, n & k ()), FTIR or ATR-FTIR (bulk changes), WCA, Tg measurements). In order to separate the effect of light (VUV, UV, visible), radicals and ion bombardment, the small-gap technique will be used with MgF2, Fused Silica and BK7 windows.

Type of project: Internship of minimum 3 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in materials sciences, physics, chemistry, electronics. Responsible scientist(s): For further information or for application, please contact Jean-Francois de Marneffe ([email protected]) and Efrain Altamirano ([email protected]).

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ESD reliability of high mobility FinFET devices for sub-14 nm CMOS

In this thesis, the intrinsic ESD robustness of bulk FinFET technology for future CMOS nodes using high mobility channels and Local interconnect layer will be analysis. Test structures are available to be measured and analyzed. In the last decade, new processing features have been introduced into VLSI technology: source/drain stressors (90 nm node), high-k dielectrics and metal gate electrodes (45 nm node). Recently, a new transistor architecture (finFET or multi-Gate FET or 3D-transistor) has been introduced for the 22nm node. The next technology option to be possibly introduced into the FinFET device architecture is the use of high-mobility (non-silicon) channel materials. For pFETs, (Silicon)Germanium-based devices are being considered due to their compatibility with the existing Si technology. For nFETs, III-V alloys such as InGaAs are being investigated. Note that the bulk hole mobility of Ge (1900 cm2/Vs) is significantly higher than that of Si (450 cm2/Vs). Similarly, the electron mobility in In0.53Ga0.47As (~12.000 cm2/Vs) is a lot higher than in Si (1400 cm2/Vs). A key reliability characteristic that needs to be investigated before any commercial product can be shipped, is its ESD (Electrostatic discharge) reliability. An ESD event on an IC, is a discharge event where up to 10 A of current over a time span below 100 ns needs to be able to flow through any 2 pin combinations of that IC without destroying or wounding it. In order to cope with such an event, a pre-designed ESD current path must be provided on the IC, using dedicated ESD clamps (voltage sensitive switched), which are off during normal operation and on during an ESD event. Such ESD clamps need to be evaluated in every new CMOS technology, and if needed to be optimized or altered. Based on excising test structures, destructive ESD measurements will be performed on various clamps and test structures. These measurements reveal the high current high voltage behavior which needs to be physically analyzed; also the failure signatures need to be understood. Once this is understood, ESD FinFET device layout optimization can be done, and ESD protection strategies developed. The multi-disciplinary work combines the use of ESD characterization tools, physical analysis of ESD device operation and the use of TCAD to clarify the underlying physical operation. The student will have to bridge the fields between advanced technology development, characterization tools, simulation and analog design, joining a team of imec specialists in this field.

Type of project: Thesis or thesis with internship. Degree: Master in Engineering majoring in electronics, nanotechnology.

Responsible scientist(s): For further information or for application, please contact Geert Hellings ([email protected]) and Dimitri Linten ([email protected]).

12


Evaluation of photoresist outgassing for extreme ultraviolet lithography

Extreme Ultraviolet (EUV) light is currently of increased interest in semiconductor processing. EUV Lithography (EUVL) is the leading candidate for 22nm half-pitch device manufacturing and beyond. One of the concerns of this process technology is related to outgassing of materials in the vacuum environment e.g. from photoresists , which, enhanced by the EUV irradiation, can result in a reflectivity decrease of the optical elements and in other decrease of exposure tool performance.

In this field the student would work at imec on an experimental outgassing set-up (Fig. 1) to evaluate the EUV related outgassing and contamination and is involved in outgassing analysis of various photoresist materials. This will contribute significantly to the understanding how materials and process conditions can impact contamination in the EUV scanners, and lead to procedures to qualify resist materials before they are used on the EUV scanners.

Fig. 1 : Experimental EUV outgassing set-up at IMEC for investigation of outgassing of lithography materials.

Type of project: Preferably internship of minimum 6 months. Degree: Master in Science or Master in Engineering majoring in material sciences, physics, chemistry.

Responsible scientist(s): For further information or for application, please contact Ivan Pollentier ([email protected]).

13


Methodologies for memory analysis using C-AFM

Conductive bridging resistive RAM memory CBRAM, based on resistance switching mechanisms, is emerging as a potential replacement for Flash and/or DRAM applications, due to its high scalability potential, for future 20 nm technology nodes and beyond (fig. A).

Conductive atomic force microscopy C-AFM (fig. B) is a scanning probe microscopy technique, relying on a normal atomic force microscope equipped with a current sensor capable to measure ultra low currents. C-AFM represents an invaluable tool in two ways. First it allows examining very small features with nm-scale spatial resolution (nanoscopic electrical probing), and secondly the tip can be used as a nano sized electrode.

This internship/thesis fits into the characterization framework for CBRAM using C-AFM. You will be trained in the use of the tool and intensively use it focusing on device de-process methodologies. During the period of the internship the student will focus on different aspects of this point, using the C-AFM twofold as a microscope and to de-process memory devices in situ. The data analysis and interpretation will cover an important part of the work; you will apply statistical principles in data collection and will be asked to rule out your results. You will work in an international R&D team; a good command of English language is required.

The detailed content of the work will be defined in detail at the moment of starting this project.

Type of project: Thesis or internship of 6 months. Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science, chemistry.

Responsible scientist(s): For further information or for application, please contact Umberto Celano ([email protected]).

14


Carbon nanotube contacts: electrical characterization of CNT Cu damascene contacts

Carbon Nanotube (CNT) interconnect devices are being processed and electrically evaluated at imec in Leuven (Belgium). The processing and electrical evaluation of the 150nm diameter CNT contacts on TiN proceeds at full wafer level in the imec cleanrooms and testing facilities. All the integration steps for the CNT integration, the steps for patterning the Cu damascene top contact, and the mask set used are compatible with 130nm device technologies on 200mm wafers.[1,2] These CMOS-compatible processes were optimized previously on 300nm via test structures, with the optimization mostly concerning the CNT growth.[3] This new platform is designed for automatic electrical testing using Kelvin vias, parallel vias or other probing pads. It allows for fast and quantitative comparison using automatic probing of 200mm wafers. The high yield that we can obtain, and the agreement between the single contact resistances measured from Kelvins and the parallel contacts indicate that the process is stable. Our work is focusing on improving the CNT quality to reduce the contact resistance. In parallel, splits in the integration module on the top contact are included to obtain more insight in the CNT-to-metal contact. In addition, we are searching for CNT growth methods from catalysts compatible with future interconnect substrates. Here, the underlayer specs may go beyond the CoSi2 or NiPtSi2 era. We will have wafers with CNT interconnects available processed under different conditions. Electrical measurements can be performed at imec for: (1) Obtaining a better understanding of the behavior of the CNT interconnect under stressed conditions (high frequency, breakdown, aging, reliability...), supported by theoretical modeling. (2) Developing a theoretical model that can be validated experimentally to distinguish the Rc-bottom contact (between CNT and bottom contact). The electrical performance studies have the objective to obtain a detailed understanding of the CNT interconnect and find ways to improve the CNT interconnect performance. The CNT growth and integration work is realized in a cross-functional team bridging the two groups of Prof. Dr. S. De Gendt (team Nano Applications Materials Engineering) and Dr. Zs. Tkei (team InterConnect Integration).

[1] N. Chiodarelli et al., IEEE IITC conf. proc. (2011) 153155. [2] M.H. van der Veen et al., Electrical Characterization of CNT contacts with Cu damascene Top Contact, Microelectron. Eng., submitted (2012). [3] N. Chiodarelli et al. Nanotechnology 22 (2011) 085302.

Cross-section of the electrical structure showing four 150nm contact holes

filled with CNT and metallized with Cu single damascene top contact.

Type of project: Thesis or internship. Degree: Master in Science or Master in Engineering majoring in physics, electronics, material sciences, nanotechnology.

Responsible scientist(s): For further information or for application, please contact Yohan Barbarin ([email protected]) and Marleen van der Veen ([email protected]).

15


Graphene synthesis and characterization

Graphene is a 2D, semi metallic, one-atom-thick sheet of sp2-bonded carbon atoms.[1] Graphene synthesis by means of mechanical exfoliation gives highest quality graphene but is not a CMOS compatible process due to (1) randomness of flake deposition (2) low yield. Growth on metal films (CVD graphene) or by annealing of SiC crystals (epitaxial graphene) still need high T budgets.[2] Although graphene is intrinsically compatible with CMOS processing because of its planar nature and transferability, technology will need a CMOS compatible synthesis method. Synthesis from solid carbon sources offers a clean method that is potentially compatible with front end of line processing, tools and scaling.[3]

The objective of this internship is to develop processes to synthesize graphene by means of anneal-type of solid stated reactions using SiC-based film stacks and by means of epitaxial growth from crystalline SiC. The candidate will also learn how to manipulate graphene in order to transfer it to alternate supports with the objective to fabricate and characterize devices.[4] Part of the work will entail the manipulation of graphene produced by mechanical exfoliation, for benchmarking purposes. The challenges involved are:

1. Fine tuning of process parameters to control the number of graphene layers grown. 2. Investigation of the influence of the substrate texture/crystallinity on the properties and quality of

synthesized graphene. 3. Study of the interfacial reactions between the substrate and graphene. 4. Post-processing of as-grown graphene (e.g., transfer, modification, device design).

The work will start from earlier findings within the graphene team[4] and is conducted in the group of Prof. Dr. S. De Gendt.

[1] Novoselov et al, Science 306 (2004) 666. [2] de Heer et al., Solid State Communications 143 (2007) 92. [3] Juang et al., Carbon 47 (2009) 2026. [4] Nourbakhsh et al, PSS 6 (2012) 53.

Type of project: Thesis or internship. Degree: Master in Science majoring in material sciences, nanotechnology, chemistry.

Responsible scientist(s): For further information or for application, please contact Marleen van der Veen ([email protected]) and Inge Asselberghs ([email protected]).

16


Growth of carbon nanotubes for future generations of interconnects

Due to their remarkable electrical, thermal and mechanical properties, carbon nanotubes (CNT) have been considered for various applications in different fields of research. One particular application, situated in the world of integrated circuits, is a CNT based interconnect.

In the literature, various reports exist where the growth of carbon nanotubes with a high quality is demonstrated. However, most of these results are obtained under process conditions that are not fully CMOS compatible and hence cannot be used in a back-end-of-line process.

The aim of this project therefore is to investigate and develop a CMOS compatible growth process that results in high quality CNTs. In addition to this, the CNTs need to be grown in very small via features (sub 22 nm), as is projected for future generations of interconnects (Figure 2). The major restrictions for the process are:

1) Process temperature has to be below 400 C. 2) Achieve CNT growth directly on conductive substrates. 3) CNT (shell) density has to be sufficiently high.

The student will be involved in experimental work, focusing on catalyst deposition techniques for CNT growth (such as electrochemical deposition of catalytic nanoparticles) as well as studying the CNT growth process itself.

The work will start from earlier findings within the CNT team and is conducted in the group of Prof. Dr. Stefan De Gendt.

Type of project: Thesis or internship. Degree: Master in Science majoring in material sciences, nanotechnology, chemistry.

Responsible scientist(s): For further information or for application, please contact Marleen van der Veen ([email protected]) and Johannes Vanpaemel ([email protected]).

Figure 1: CNTs grown on TiN

17


Atomic layer deposition for applications in nanotechnology

Atomic Layer Deposition (ALD) is an advanced technique to deposit thin films on a substrate from gas phase precursors. The film is deposited layer by layer through a cyclic process of self-limiting surface reactions. The use of self-limiting surface reactions results in a number of unique features, such as growth control at the atomic level and conformal deposition on extremely complex nanostructures.

Thanks to the process control at the atomic level, ALD has applications in nanotechnology. For example, the performance of computer chips and memory cells can be improved by introducing novel materials deposited by ALD, for example high-k dielectric oxides. A new potential application is energy storage in supercapacitors with nanostructured materials. ALD can also be used to increase the efficiency of solar cells, e.g. by introducing a passivation layer.

This thesis or internship topic frames in the research and development of ALD processes of metal oxides (e.g. Al2O3, HfO2, SrTiO3 , TiO2 ). The ALD process parameters need to be optimized in order to achieve uniform (nanometer thin) films with optimized properties. For example, the self-limiting aspect of the surface reactions is examined as it provides the basis for the process control at atomic level. The deposition temperature can affect the amount of impurities in the film and its phase. For deposition of metal oxides, the oxidant precursor (H2O, O3 ) also plays an important role. Insight in the surface chemistry (ligand exchange reactions or oxidation reactions) can provide a substantial contribution to the optimization of the process.

In order to characterize the nm-thin films, complementary measurement techniques are applied, such as spectroscopic ellipsometry, X-ray photoelectron spectroscopy, Secondary Ion Mass Spectroscopy

Type of project: Thesis and/or internship of approx. 6 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in chemistry, physics, material sciences.

Responsible scientist(s): For further information or for application, please contact Annelies Delabie ([email protected]) and Sven Van Elshocht ([email protected]).

18


XRD study of nano-structured hetero-epitaxial III-V compound semiconductors for VLSI CMOS applications

Since a few years, III-V compound semiconductors such as InGaAs, InP and InAlAs are being researched by the micro-electronics community as candidate materials for replacing silicon in the most advanced CMOS generations for 2020 and beyond. Due to the lattice mismatch and chemical differences, the epitaxial growth of these III-V materials on Si substrates requires specific approaches to control defect formation, which is lethal for highly performing circuits. Therefore, it is critically important being able to measure and analyze not only the thickness of these layers and their exact composition, but also such parameters as crystalline quality, defects and defect density. One of the most important techniques to assess the crystalline quality of semiconductor layers is X-ray diffraction, but in principle this technique is only applicable on bulk materials or blanket films. The purpose of this work is to develop measurement routines which allow to analyze nano-size structures by means of advanced XRD-tools, featuring thin film diffraction, grazing incidence X-ray diffraction, high-resolution X-ray diffration, X-ray pole figure analysis and/or X-ray rocking curve analysis.

Type of project: Thesis and/or internship. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science, physics, electronics, ...

Responsible scientist(s): For further information or for application, please contact Clement Merckling ([email protected]) and Weiming Guo ([email protected]).

Developing in-situ doping of III-V compound semiconductors by hetero-epitaxial MOCVD growth

The epitaxial growth of III-V compound semiconductor on silicon substrate as channel material is a very promising method for future CMOS device fabrication because of their high electron mobility. Their implementation in conventional MOS structures requires thin III-V layers to be grown on a silicon substrate with shallow, abrupt and well-controlled doping profiles.. The doping efficiency is influenced by many growth conditions such as precursors, the growth temperature, annealing treatments etc. This work focuses on the doping of III-V thin layers (typically InGaAs, InAlAs) during MOCVD growth, by using different doping elements such as carbon and silicon. The aim is to develop effective and reproducible growth processes so that the doping concentration and diffusion of the doping elements can be tightly controlled.

Type of project: Thesis and/or internship. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science, physics, electronics, ...

Responsible scientist(s): For further information or for application, please contact Clement Merckling ([email protected]) and Weiming Guo ([email protected]).

19


Surface preparation and interface passivation of high mobility channel materials for beyond 14 nm technology nodes

The continuous demand for downscaling pushes the Si transistor towards its physical limits. Therefore, new materials need to be introduced as channel materials. Possible candidates are SiGe, Ge, and III/V (e.g. InGaAs and InP). These materials exhibit high bulk mobilities. However, in order to fulfill their high expectations, the interface between the channel and the high-k needs to be passivated. Simply stated, a good passivation preserves the bulk properties throughout the interface between the channel material and the high-k oxide. In order to achieve this, we need to start from a defect free surface and the subsequent high-k deposition should not introduce new defects. Therefore, the first step is to control the surface chemistry of the channel material. This can be done by a wet chemical treatment or by a gas phase treatment prior to the high-k deposition. The goal is to study the resulting surface chemistry by highly advanced analysis techniques such as AR-XPS (Angle Resolved X-Ray Photo-electron Spectroscopy), TXRF (Total X-Ray Reflection Fluorescence), SIMS (Secondary Ion Mass Spectroscopy) ... . The next step is to study the influence of the surface chemistry on the high-k deposition by ALD (Atomic Layer Deposition) and hence the passivation of the interface created. Again, several analysis techniques need to be used in order to unravel the chemical bonding at the interface. Additionally, electrical characterization is needed to study the passivation of the interface formed. In the end, we need to come to a high quality interface with low defect densities in order to allow the introduction of these new materials in the next technology nodes.

Type of project: Thesis and/or internship. Degree: Master in Science or Master in Engineering majoring in chemistry, material sciences.

Responsible scientist(s): For further information or for application, please contact Sonja Sioncke ([email protected]).

20


Development of a fixed ramp rate breakdown voltage procedure for gate dielectric testing

CMOS scaling is not only concerned with the reduction of the channel length and channel width, but also the scaling of other transistor parameters such as the gate dielectric thickness. The long-term reliability of these ultra-thin layers is of major concern. Several critical reliability mechanisms are identified and under investigation. Some of these tests however are quite time-consuming.

The main aim of this thesis/internship is to develop a fixed ramp rate breakdown voltage procedure for fast gate dielectric testing. This includes the selection of the proper measurement tools, the implementation of the test software within our measurement environment, the demonstration of the finished routine and the electrical testing of advanced gate stacks.

Type of project: Thesis or internship of 6 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in electronics.

Responsible scientist(s): For further information or for application, please contact Thomas Kauerauf (Thomas.Kauerauf @imec.be).

Electrical evaluation and reliability assessment of local interconnects

In future CMOS technologies the individual transistors will be connected through local interconnects in order to increase the device density and to reduce the metal one complexity. These local interconnects however have to fulfill the same strict reliability specification as the other chip components and a thorough understanding of the potential degradation mechanisms is needed.

The main aim of this thesis/internship is the electrical characterization of these local interconnects. This includes the evaluation of various newly designed test structures, the comparison of different local interconnect processes and the investigation of potential reliability issues.

Type of project: Thesis or internship of 6 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in electronics.

Responsible scientist(s): For further information or for application, please contact Thomas Kauerauf (Thomas.Kauerauf @imec.be).

21


Investigation of advanced resistance-switching (RRAM) memory cells

Resistive Random-Access-Memory (RRAM), based on resistance switching mechanisms, is emerging as a potential nonvolatile memory candidate for below-20nm technology nodes, due to its better scalability, beyond the limits currently predicted for NAND Flash. 10nm-small RRAM cells are shown to have low voltage operation, very fast switching time, in the order of ns and below, small energy consumption per switching and good reliability. To take on the benefits of these excellent attributes to circuit level and enable high density memory array implementation, additional self-rectifying functionality is required for the resistive switching stack. The main task of this internship/thesis is to investigate RRAM cells that show self-rectifying characteristics, with the aim of understanding the switching behavior, relate it to intrinsic performance and identify paths for further improvement/optimization. You will be involved in electrical characterization, focusing on either performance or reliability aspects. You will be using state-of-the-art instrumentation and you will apply statistical principles in data collection using in-house developed characterization methodologies, so as to ensure a short response time in characterization. You will process data and assist in their interpretation. Feedback for process improvement is a key point. You must have a good background in semiconductor physics and knowledge of CMOS technology. You must be fluent in at least one programming/data analysis environment such as Matlab or similar and familiar with LabView and basic instrumentation for electrical testing. You will work in an international R&D team; a good command of English language is required. The detailed content of the work will be defined in detail at the moment of starting this project.

Type of project: Thesis or internship of 4-6 months. Degree: Master in Science or Master in Engineering majoring in electronics, electrical engineering, physics.

Responsible scientist(s): For further information or for application, please contact Bogdan Govoreanu ([email protected]).

22


Investigation and optimization of the electrical switching properties of Conductive Bridging RAM memory cells (CBRAM)

The Resistance RAM is a new class of memories emerging as serious candidate for future memory replacement, in particular for high-density memory application. Resistance RAM cells typically consist of an insulator material sandwiched between two metal electrodes, and exhibiting resistive-switching properties, that is to say the application of an electrical current/voltage to the cell induces reversible changes of the cell resistance, which allows thus programming different memory states. The Conductive Bridging RAM (CBRAM) is a sub-class of RRAM, for which one of the electrode contains mobile elements (usually Cu or Ag) and which is based on the following switching mechanism: (1) applying a positive voltage to the Cu- or Ag-containing electrode activates the formation of a conductive bridge (or filament) in the insulator, resulting in the switching of the cell to a low resistance state (LRS); (2) on the other hand, a negative voltage activates the dissolution of this filament and thus the return to the high resistance state (HRS) (see Fig.1).

Fig1. Current-voltage switching traces and schematic of filament formation due to electrochemical dissolution and growth of the electrode metal element (from R. Waser et al., Adv. Mater., 21, 2009) At imec, we started a project aiming to develop Cu-based CBRAM cells. We fabricate cells consisting of different materials for the Cu-based electrode (pure Cu, or Cu-alloys) and for the insulator (binary oxides, nitrides, ...). The purpose of the thesis is to study the resistive-switching properties obtained for different stacks and to relate these switching characteristics to the physical properties of the used materials. The gained understanding of these relationships will allow to (1) better understand the switching mechanism, and (2) identify optimum material stack characteristics improving the memory parameters of the cell. To this aim the study will mainly consist in electrical measurements using conventional Current-Voltage measurements, as well as pulse-programming testing for scaled devices. Specific measurements like temperature-dependent I-V or impedance measurements may also be required. The study will be carried out within a project team consisting of experts in different fields (processing, integration, physical characterization, modeling ...), and in close collaboration with industrial partners. Type of project: Thesis or internship of minimum 5 months. Degree: Master in Science or Master in Engineering majoring in material sciences, physics, electronics.

Responsible scientist(s): For further information or for application, please contact Ludovic Goux ([email protected]).

23


Passivation of Ge for high-performance applications

Since several decades, the semiconductor material of interest to fabricate computer chips and other electronic devices has been Si. In the near future however, such high-performance applications may require a different type of semiconductor because Si does not fulfill the needs anymore. Due to its higher intrinsic carrier mobility and hence the possibility to operate at higher speed, Ge is being considered as a potential candidate to replace Si. A critical issue for the successful integration of Ge devices on the other hand is the electrical passivation of the Ge surface. This passivation is mandatory because defects like dangling bonds at the Ge/gate stack interface are able to trap charges and as such decrease the carrier mobility.

This thesis or internship topic frames in the research and development of an optimal passivation of the Ge surface, resulting in the highest feasible carrier mobility. We will focus on GeO2 as this type of passivation has shown to be promising. Also, the integration of GeO2 is quite straightforward since it can be obtained by oxidation of the Ge semiconductor surface. The quality of the GeO2 layer however will depend largely on the preparation method. Therefore, we will evaluate several techniques in order to obtain GeO2 of the best quality and a defect-free Ge/GeO2 interface. The physical quality of the GeO2 passivation layer will be examined by means of several measurement techniques like Spectroscopic Ellipsometry, X-Ray Photoelectron Spectroscopy and Atomic Force Microscopy. Capacitance-Voltage and Current-Voltage measurements will be applied for electrical evaluation. This electrical evaluation will first be done on capacitors, which consists of a Ge semiconductor substrate, a GeO2 passivation layer, a high-k dielectric layer and a metal gate. At the final stage, the passivation layer will be evaluated on transistors, resembling the eventual electronic device.

Type of project: Thesis and/or internship. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in chemistry, physics, material sciences, electrical engineering.

Responsible scientist(s): For further information or for application, please contact Laura Nyns ([email protected]) and Sven Van Elshocht ([email protected]).

24


Graphene: device fabrication and characterization

Graphene, an atomically-thin sheet of carbon atoms arranged in a sp2 honeycomb lattice, has been successfully isolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666.]. The peculiar electronic properties of graphene arise mainly from the configuration of its energy band structure, which, combined with the intrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-D physical phenomena. Graphene has been proposed as a candidate for CMOS and post-CMOS electronics. However, in order to make electronic applications of graphene realistic, one has to necessarily tune its electronic properties, so that, for example, a bandgap is introduced. The realization of a proper bandgap is critical for the device performance. Most recently, the research team has demonstrated the tuning of single-layer graphene by p- and n- doping due to engineering the interactions with the SiO2 support [Nourbakhsh et al, PSS 6 (2012) 53.].

Figure: (a) Transfer characteristics and (b) transconductance of SLG-FETs fabricated on pristine and silanized Si/SiO2 substrates. The latter sample is then treated in basic (red) and acidic (blue) solutions to turn the behavior from n- to p-type.[Figure taken from: Nourbakhsh et al, PSS 6 (2012) 53.] (c) image of a graphene device.

The candidate will learn how to manipulate and functionalize graphene, to characterize the doping level and the bandgap formation. Therefore, he/she will be involved in the design, fabrication, and characterization of graphene devices. Part of the work will entail the manipulation and functionalization of graphene produced by both mechanical exfoliation and synthetically grown graphene, for benchmarking purposes. The challenges involved are: The study of the interfacial reactions between the substrate, graphene and doping layer; Post-processing of as-grown graphene (e.g., transfer, modification, device design); Device fabrication by lithography; Electrical device characterization. The work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. De Gendt.

Type of project: Thesis or internship. Degree: Master in Science or Master in Engineering majoring in material sciences, nanotechnology, chemistry, physics.

Responsible scientist(s): For further information or for application, please contact Inge Asselberghs ([email protected]).

25


Graphene: device fabrication for optoelectronics

Graphene, an atomically-thin sheet of carbon atoms arranged in a sp2 honeycomb lattice, has been successfully isolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666.]. The peculiar electronic properties of graphene arise mainly from the configuration of its energy band structure, which, combined with the intrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-D physical phenomena. With respect to optoelectronic device performances, the high transparency in the visible-light range and the low resistivity of graphene sheets are the most attractive features, which makes graphene an ideal candidate to explore further its potential as a transparent electrode. The goal of this project is to study the layer interactions between substrate, graphene and optical active materials (e.g. quantum dot interactions), to characterize device performances and by molecular fine-tuning increase the optoelectronic device performance.

(a) (b) (c)

Figure: (a) Schematic of the QD-treated graphene transistor in the typical measurement configuration employed in this work. (b) Transfer characteristics Ids vs. Vg of a SLG FET in pristine conditions, after QD deposition, and during QD excitation (532 nm laser). The inset shows an optical microscope image of the 2-probe graphene device (scale bar: 2 m). (c) Energy level diagram of the CdSe/ZnS QDs in contact with SLG.[Pictures taken from: Klekachev et al, Physica E: Low-dimensional Systems and Nanostructures (2011) 43(5) 1046-1049]

During the internship/master thesis you will learn how to manipulate and functionalize graphene, to characterize the doping level and the bandgap formation. Therefore, you will be involved in the design, fabrication, and characterization of graphene optoelectronic devices. The challenges involved are: The study of the interfacial reactions between the substrate, graphene and doping layer; Post-processing of as-grown graphene (e.g., transfer, modification, device design); Device fabrication by lithography; Electrical and optical device characterization The work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. De Gendt.

Type of project: Thesis or internship. Degree: Master in Science or Master in Engineering majoring in material sciences, nanotechnology, chemistry, physics.

Responsible scientist(s): For further information or for application, please contact Inge Asselberghs ([email protected]) and Alexander Klekachev ([email protected]).

26


Characterization of ohmic contacts to high-mobility materials (Ge, III-V)

In near future, CMOS technology will have to implement novel semiconductors materials in the existing Si-based platform. This will allow maintaining good performances while scaling the CMOS features dimensions. High-mobility materials, like Ge and III/V compounds (GaAs, InGaAs, InAs...) are considered the best candidates to replace Si. In order to be able to implement these materials, contact schemes need to be developed to obtain low resistive ohmic contacts to Source and Drain areas of MOSFET devices. This needs also to be achieved working out integratable solutions. Fabrication and characterization (electrical and physical) of Metal/high-mobility materials test structures allows for extraction of specific contact resistivity values, which combined with thermal stability studies can lead to determination of proper contact scheme to satisfy ITRS requirements for sub-22 nm node. The candidate will start by studying the theory of ohmic contacts and metal/semiconductor systems. He/she will get familiar with state-of-the-art solutions for contacts on high mobility materials. He/she will follow closely the fabrication steps of test structures and perform electrical characterization, backing the results theoretical studies and simulations of Metal-Semiconductors systems.

Type of project: Internship or thesis with internship of 3-6 months. Degree: Master in Science or Master in Engineering majoring in physics, electronics, material sciences (focusing semiconductors materials). Responsible scientist(s): For further information or for application, please contact Andrea Firrincieli ([email protected]) and Jorge Kittl ([email protected]).

27


Spin transfer torque magnetic random access memory

As the demand for faster, smaller and more power-efficient devices is increasing, the present memory technologies, such as DRAM, SRAM, and NAND Flash are reaching their limits in terms of scalability beyond the 16-nm generation. Alongside the thriving effort to push further the boundaries of current technologies, new emerging memories have been developed and the spin-transfer torque magnetic random access memory (STT-MRAM) is considered the most promising replacement. This is the next generation of consumer mass-scale application of spintronics, following the widespread read head technology that hard drives use nowadays, which could open the way to a new era in which nano-spintronics complements or even replaces nano-electronics in a broad scale.

STT-MRAM is a type of non-volatile memory, it retains the information even when is not powered. It is based on magnetic materials, more specifically on magnetic tunnel junctions (MTJ), a sandwich composed of two ferromagnetic electrodes separated by an oxide barrier. The information in these devices is stored given the relative orientation of the ferromagnetic layers. A high resistive state is found when they are antiparallel and a low resistive state when both ferromagnets are pointing towards the same direction. The control of the magnetization is done via the spin-transfer torque effect (STT) that enables to manipulate magnetizations by applying electrical currents that become spin-polarized when traveling through the ferromagnets.

Imec is implementing a very exciting and challenging program on the development of STT-MRAM devices on the 300-mm platform, aiming ultrafast devices at the smallest possible technology nodes.

Several possibilities for master thesis and internships are possible. Experimental studies will be carried out on the magnetic properties of novel materials with perpendicular magnetic anisotropy. This will be carried out via combinatorial sputtering deposition (outsourced), electrical (transport) and optical (MOKE) characterizations. To support the experimental findings, micromagnetic simulations will be investigated on distinct properties. For example, to predict the magnetization behavior during the write process is crucial to reduce the necessary write current. This reduction in current also depends on the optimization of key parameters such as magnetic damping and anisotropy energies.

Knowledge on magnetism is an asset.

Type of project: Thesis and/or internship. Degree: Master in Science or Master in Engineering majoring in material sciences, physics.

Responsible scientist(s): For further information or for application, please contact Mauricio Manfrini ([email protected]), Sven Cornelissen ([email protected]) and Jorge Kittl ([email protected]).

28


Wet processing of high aspect ratio nanostructures

In semiconductor manufacturing, two critical issues in the wet processing of nanostructures with high aspect ratio are incomplete wetting and pattern collapse. The contact angle that a liquid drop makes with an ideally flat surface depends mainly on surface chemistry. Amplification of hydrophobicity by surface patterns is frequently seen in nature (e.g. so-called lotus effect) and is illustrated in Figure 1 for flat and nano-patterned silicon surfaces. Development of superhydrophobic behavior can lead to processing defects from incomplete wetting in between nanostructures. On the other hand, as the critical dimensions of structures scale down, capillary force can cause significant deflection of high aspect ratio structures and pattern collapse can occur after complete drying. Figure 2 shows the SEM images of free standing nano pillars before a wet treatment (a), and self organized patterns formed after pillars are brought together by capillary forces (b & c). These pattern collapses should be prevented in industrial fabrications.

In this project we investigate the wetting behavior of solutions on nanostructures with different surface chemistries and the parametric dependence of pattern collapse on the wetting properties of the structure material as well as structure dimensions. The student will have access to imecs state-of-the-art cleanroom facilities and get hands on experience of contact angle measurement, Fourrier transform infra-red spectroscopy (FTIR), electroless metal deposition and surface modification by adsorption.

(mirror image)

Figure 1. Water droplets on flat (left) and nano-patterned (right) silicon surfaces.

(a) (b) (c)

Figure 2. Top-down SEM images of (a) free standing pillar structures with high aspect ratio; (b) and (c) self-organized collapsing patterns formed after a wet processing.

Type of project: Thesis or internship of minimum 3 months. Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material sciences, chemistry, physico-chemistry.

Responsible scientist(s): For further information or for application, please contact Guy Vereecke ([email protected]) and XiuMei Xu ([email protected]).

29


Surface chemistry of III-V semiconductors for cleaning applications

In order to meet the future demands imposed by the scaling roadmap, the heart of the transistor, the channel, needs to be replaced by a new material in which the mobility of the charge carriers is higher than for silicon. Semiconductor compounds based on group III and V elements of the periodic system e.g. InP and InGaAS meet these requirements. The III-V materials are grown in transistor structures through the gas phase with epitaxial and atomic layer deposition techniques. A critical factor controlling deposition is the starting condition of the surface as this influences the nucleation and properties of the grown layer. When contamination is present in the form of native oxides, metals and particles, or when dangling bonds are not fully passivated, defects will be introduced in the deposited layer or at the interface. Such defects are usually electronically active and reduce the efficiency of the transistor. Minimizing defect densities in transistor structures is essential and can be achieved with controlled chemical surface treatments. In order to design wet chemical solutions that lead to an appropriate surface pre-conditioning and allow for nano-scale processing of these III-V materials, a thorough understanding of the interactions between the substrate and the chemical solutions is needed and the basic etching mechanism needs to be investigated on a (sub) nanometer level.

The goal of this project is to find a suitable chemistry which leads to selective contaminant removal and controlled etching of the substrate in order to guarantee removal of surface defects in the crystal lattice. This (sub)nanometer etching should be independent of crystal orientation in order to keep the surface stoichiometry intact. After contamination and defect removal reoxidation of the surface poses a problem and can be minimized by sulfur based passivation. At present we are screening various sulfur chemistries and we are characterizing the passivation process. For this research the following techniques are important: ICP-MS to determine the amount of dissolved III-V material (ppb-ppt level) TXRF to measure metallic contamination on III-V surfaces Electrochemistry to study kinetics of etching and metal deposition Photoluminescence to obtain insight in surface passivation and defect levels XPS to measure surface composition Atomic Force Microscopy to measure surface roughening at the atomic scale.

We are looking for enthusiastic and motivated students majoring in chemistry, material sciences or related field with a strong interest in chemistry/physics of semiconductors and analytical chemistry. The duration of this project is 2-12 months (assuming full time presence).

Type of project: Internship with thesis (2-12 months full-time). Degree: Master students majoring in chemistry, material sciences.

Responsible scientist(s): For further information or for application, please contact Dennis van Dorp ([email protected]).

30


The creation of nanoforces by microbubbles

Bubbles can be created in fluids and are used for a broad range of applications. Under the influence of pressure variations, bubbles can implode which is shown in figure 1. The last few years, the research in microbubbles has been ramped up, because imploding microbubbles can be used in biomedical applications. An example is the implosion of microbubbles near a cancer cell, which result in the perforation of the cell membrane. Once the cell membrane is open, the injection of medicine is facilitated. The ruptured membrane of living cells usually heals within a time span of a few minutes. An example of a ruptured cell is shown in figure 2. In the semiconductor industry, oscillating bubbles are used to remove contaminants or nanoparticles from fragile structures. By using

ultrasound or, in other words, the same sound field for visualizing fetuses, small bubbles can be created. These microbubbles oscillate with the same rhythm as the sound field. If the sound pressure is high enough, the bubbles will oscillate very strong and they can even collapse. Such a collapsing bubble will remove nanoparticles from a surface. Currently the implosion is not very well controlled and also results in damaged fragile structures. More in depth research is necessary to control the nanoforces created by the imploding microbubbles. The final goal of the work is to control the microbubble size and to facilitate bubble nucleation. Several aspects need to be investigated, including the effect of charge, surface tension, spatial distribution of microbubbles, changes in the sound field... The experimental tools which can be used for this type of work are sonoluminescence tests, cavitation noise measurements, damage

Cmos Scaling R&D

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