CMOS RFIC Design for Direct Conversion...

CMOS RFIC Design for Direct Conversion

Receivers

Zhaofeng ZHANGSupervisor: Dr. Jack Lau

Outline of PresentationOutline of PresentationOutline of PresentationOutline of Presentation

Background Introduction Thesis Contributions Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

Research Goal

• Low Cost– Process: CMOS

• Device is good enough• Improved passive components

– Integration level• Minimize external components• Minimize IC area and pin numbers

• Low Power– High integration = low power– Low power individual block design– System architecture is important

Heterodyne Receivers

• High IF: more than 2 down-conversions– Best sensitivity– Need off-chip image-rejection SAW filters and

channel-selection filters– Highest cost, high power, low integration

• Low IF– Relaxed image-rejection requirement compared

to high-IF– No DC offset problem– Quadrature LO is required– Flicker noise may be a problem– High integration level, low cost

Homodyne Receivers

! Simple architecture ! No image problem! No 50ohm interfaces! High integration level! Lowest cost, low power

! DC offsets! Flicker noise! LO leakage! Even-order distortion

ProsCons

90º

I

Q

LNA

Thesis Contribution (I) On-chip cross-talk and substrate noise was

studied and shielding schemes were proposed [RFIC1998, Baltimore].

Flicker noise under switching conditions was studied experimentally for the first time and a simple flicker noise model was proposed [CICC2001, San Diego].

Square-law based harmonic mixing technique was proposed to solve DC offset and LO leakage problem in a CMOS process [RAWCON2000, Denver].

Thesis Contribution (II)

A lateral bipolar harmonic mixer was developed for solving both DC-offset and flicker noise problem [RAWCON2001, Boston].

A direct-conversion RF front-end was developed [ISCAS2001, Sydney].

Fully-integrated single-chip pager in a CMOS process was demonstrated [ISSCC2001, SFO].


Thesis Contributions Background Introduction Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

Origin of Problem

! DC offsets! Flicker noise! LO leakage! Even-order distortion! Linearity requirement! Noise requirement! IQ mismatch

The mixer: the most critical component!All problems are limited by the mixer design!

Our research focus!

DC Offsets & LO Leakage

+ Offset

The offset originates from self-mixing. It can be as large as mV range at the mixer output. It varies with the environment and moving speed of the mobile and changes with time. The maximum bandwidth can be as large as kHz range. LO leakage forms an interference to other receivers.

LO Leakage

Zero IF

Pow

er

Narrow Band Broad Band

Frequency

Pow

er

Frequency

Pow

er

Frequency

Pow

er

Frequency

Signal

DC

Off

sets

Off

set-

Free

DC offset

Spectrum Illustration

Flicker noise

High-pass corner

Existing Solutions on DC Offset

AC coupling or high pass filtering Autozeroing or double sampling Offset cancellation in digital domain Double LO frequency method [ISSCC99] Adaptive dual-loop algorithm combined with the mixer

[RAWCON00] Pulse-width-modulation based bipolar harmonic mixer [CICC97]

However, these methods are either not so effective or very complicated, or not

suitable for CMOS process.

Proposed Harmonic Mixing

Con

vent

iona

lO

ur W

ork

flo=frf

RF Signal

frf

BB Signal

0

2flo=frf

RF Signal

frf

BB Signal

0

LO Leakage DC Offset

LO Leakage

flo=frf/2 flo

Square-law Based Mixer

LO leakage free. Ideally self-mixing free. Current controlled switching. No noise contribution from LO stage.

LO

2

RF IFCurrent

Voltage

Voltage

CouplingNo

Vlo+ Vlo-

Vrf+ Vrf-

3V

Flicker Noise Reduction

Flicker noise is proportional to the current. Current injection is used to reduce flicker noise. No noise contribution from current source too.

Vrf+I0

Vlo+ Vlo-

Vrf-

3V

Offset Cancellation20

10

0-10

-20

-30

-40 -22 -20 -18 -16LO Input Power (dBm)

Gai

n (d

B) >35dB

TSMC0.35µµµµ

Noise Performance60

50

40

30

20400 600 800 1000

Injected Current I0 (µµµµA)

Noi

se F

igur

e @

10k

Hz

(dB

)

How to improve more? However, flicker noise is still too large due to CMOS

devices, minimum noise figure achieved is larger than 24dB @ 10kHz for CMOS harmonic mixer. It requires a high gain and low noise LNA to overcome flicker noise while the front-end linearity suffers.

For a narrow-band communication system such as FLEX pager, the noise requirement at low frequency is very tough.

It is well known that bipolar device is a good candidate to eliminate flicker noise.

But, can we do it in a CMOS process and how good is the device? YES!

Lateral Bipolar Transistor in a Bulk CMOS Process

W.T. Holman95

Gate

Emitter

Collector

Base

Ground

P+ N+

Emitter

Vertical

Collector

Collector

Lateral

Base

Gate

Physical Model of LBJT

D. Mac98

P-Sub

Gate

EmitterCollector

Base Base

P-Sub

M1Q1

Q2Q3

Pure LBJT: M1, Q3 off, Q1, Q2 on.

Gummel Plot of LBJTTSMC0.35µµµµ

ββββ>40 at mAs

max fT ≈≈≈≈4GHz

LBJT Harmonic Mixer

RLRLOUT- OUT+

VRF+ VRF-Ii

VLO-VLO+ M1 M2

VDD

Q1 Q2

Noise Performance

Large LO improves noise.

Even Order Distortion

RF Signal

frf

BB Signal

0

Interference IM2 (f2-f1)

It is mainly introduced by layout asymmetry and device mismatch. Since direct-conversion, the intermodulation components IM2 will fall into the demodulated signal spectrum. Therefore, good IIP2 is required for homodyne receivers. It is found that varying the loading resister or voltage bias can compensate the device mismatch and improve IIP2 significantly.

a1x+a2x2+a3x3+…

f1 f2

IIP2 Improvement

IIP2=18dBm IIP2>40dBmSame DC bias Compensation

LBJT Mixer Performance

<2.2mWPower consumption>+40dBmInput-referred IP2>-9dBmInput-referred IP3>-20dBm1dB compression point<18dBNoise figure @ 10kHz>30dBDC offset suppression+15dBSignal Gain3VVDDTSMC 3M2P 0.35µmTechnology

Summary on MixerSummary on MixerSummary on MixerSummary on Mixer Flicker noise free, corner frequency is

below 10kHz. DC offset free, more than 30dB DC offset

suppression is achieved. No LO leakage problem. Sufficient IIP2 after bias compensation. High gain and low power consumption. Complete CMOS process. Suitable for CMOS direct conversion

applications.

Difficulties in FLEX PagerFLEX 6400, 4FSK

0

-20

-40

-60

dB

1050-5-10kHz

Narrow band modulation Significant energy near DC High pass filtering is not viable DC offset problem Flicker noise is significant

10 -1

10 -2

10 0

BER

Eb/N0 (dB)4 8 12 16

DC

Off

set

Eff

ect

Hig

h pa

ss e

ffec

t

High pass corner (Hz)

BER

@ 1

2dB

Eb/N

0

-210

-1

Big Challenges

4-FSK Pager Receiver

Fully differential architecture to reject substrate noise. Harmonic mixers are used to solve time-varying DC offset. Peak detectors are used to cancel static DC offset. High front-end gain and current injection to reduce flicker noise.

45°°°°

AGC

AGC

LNA DEMODVCO

RF: Zhaofeng

BB: Zhiheng

LNA Non-quasi-static

phenomenon makes it unnecessary to do on-chip matching.

Off-chip matching by a single inductor and a balun.

|S11|<-20dB @ 930MHz

Both on-chip and off-chip inductive loads were tried.

Double Balanced Mixer

Improve the linearity; Provide constant impedance to LNA;Current injection provides more than 20dB flicker noise reduction.

Ring Oscillator

Half RF frequency,

Provide 45°°°° phase.

AGC

Gain: -14.5dB~18.6dB. The linear resistor R0 is used to improve the linearity. The signal level is sensed by the peak detector.

Static DC Offset Cancellation

Peak Detector

Fmin≈200Hz

Zero-IF 4-FSKSignal

Low Pass Filter

5th order elliptic gyrator-C filter Pass-band gain 6.2dB, ripple ≤ 0.5dB (≤ 9kHz) Stop-band attenuation ≥ 63dB (≥17.8kHz)

Gai

n [d

B]

0 10 20 30Frequency [kHz]

0

-20

-80

-60

-40

-100

Noise Performance

Front End Base Band

Performance SummaryPager receiver with off-chip ind

Maximum Gain: 62dB

Noise figure@10kHz: 14.5dB

Overall DC offset at LPF output: <1mV

(Signal: 400mV)

Power dissipation: 58mW

Technology: TSMC0.35µm 4M2P

Die area: 4.6 mm2

Front-End Off-chip ind On-chip ind

RF/BB gain: 51.13dB 40.33dB

NF@10kHz: 11.5dB 24.0dB

NF@100kHz: 5.8dB 15.0dB

IIP3: -26dBm -20.7dBm

IIP2: -10dBm -5.6dBm

Operating frequency: 930.1MHz

LO frequency: 465MHz

IQ gain mismatch: < 0.3dB

IQ phase mismatch: < 5°

RF/BB over LO/BB: > 54dB

Self-mixing free

Input matching: < -20dB

Power dissipation: 52.76mW

Baseband (Zhiheng)AGC gain: -14.5dB~18.6dB

LPF: Pass-band gain-6.2dB, ripple ≤0.5dB (≤9kHz)

Stop-band attenuation ≥ 63dB (≥ 17.8kHz)

Offset cancellation: <2mV (under ±100mV input offset)

Input Referred Noise: 600nV/ @ 10kHz

Clock Recovery: Capture range > 550Hz

Power dissipation: 5.4mW (including all testing buffers)

Hz

Die Photo

DEM

OD

LPF

AG

C

Mixer

OSC

LNA

LNA

OSC

Mixer

Base Band Circuitry[Zhiheng]

RF Front-End

RF Front-End

45°°°°

AGC

AGC

LNA DEMODVCO

Summary on Pager Receiver

Feasibility of direct conversion has been demonstrated.

Proposed harmonic mixing technique solves self-mixing induced DC offset problem successfully.

With the help of static DC offset cancellation, the total DC offset is less than 1mV at the receiver output.

The modified ZIFZCD 4-FSK demodulator functions correctly.

A 4-FSK FLEX pager receiver in a single chip has been implemented successfully.

Conclusion Circuit design for direct-conversion has been

discussed. DC offset: more than 30dB improvement LO leakage: no longer a problem Flicker noise: corner frequency is less than kHz due to

lateral bipolar device. IIP2: larger than +40dBm after bias compensation.

System on chip has been successfully demonstrated using CMOS direct conversion architecture.

Crosstalk has been studied and can be improved more than 20dB with proposed shielding method.

Flicker noise under switching has been studied and a flicker noise model has been proposed.

Crosstalk & Substrate Noise

Line-line crosstalk

Device noise

Capacitive coupling

Inductive couplingSwitching noise

Substrate noise

Inductor induced noise

Interference

Very bad for high-level integration!

Signal Leakage

Crosstalk in RFPCB

Thickness-distance ratio (h/d) 0 0.5 1.0 1.5 2.0 2.5

Nea

r en

d cr

osst

alk

S21

(dB)

-20-25-30-35-40-45-50-55-60-65-70

Crosstalk in RFIC

Separation distance (µm)0 2 4 6 8 10 12 14 16 18 20 22

Nea

r en

d cr

osst

alk

S21

(dB) -32

-34-36-38-40-42-44-46-48-50-52

Shielding Schemes

w d wAirSiO2

P- Epi (~20 Ω-cm)

P+ Bulk (~0.05 Ω-cm)

P- Epi (~20 Ω-cm)


Airw d w

Method IIMethod I

P- Epi (~20 Ω-cm)


Air w d w

P- Epi (~20 Ω-cm)


w d wAir

Method III Method IV

Crosstalk Comparison

Method IV

Method III

Method II

Method I

No shielding

Separation distance (µm)2 4 6 8 10 12 14 16 18 20 22

Nea

r en

d cr

osst

alk

S21

(dB)

-30-40

-50-60

-70

-80-90-100

-110

-120

Summary on Crosstalk Crosstalk in RFIC: about -30~-40dB at GHz

range. Separation is pointless. Proper shielding provides excellent crosstalk

immunity, crosstalk can be improved by 20~40dB.

Receiver gain can be improved due to reduced feedback effect through substrate.

Penalty: One metal layer may be sacrificed.

Flicker NoiseFlicker NoiseFlicker NoiseFlicker Noise CMOS is the best candidate for low cost and high

integration, but flicker noise may be a problem in homodyne receivers, how to reduce it?

Flicker noise under static bias was well studied and modeled, but how about under switching conditions, such as in mixers?

Will this correlated noise respond to the switching signal? If yes, how and how much?

The flicker noise performance usually depends on measurements. Is it possible to optimize the flicker noise in the circuits without any measurements?

Measurement SetupMeasurement SetupMeasurement SetupMeasurement Setup

SR780

3VDynamic Signal Analyzer

DS34584/284/2

RL512

RL512

MethodologyMethodologyMethodologyMethodology

High Frequency SwitchingComplicated Non-linear System

+Frequency IndependentNon-linear System

Frequency Dependent Linear System

Low Pass FilteringEnough Output Bandwidth

Low Frequency Switching

Assumption

SolutionFortunately, the assumption is true, we will see.

Fast SwitchingFast SwitchingFast SwitchingFast Switching(Switching frequency > 100kHz)

Switching frequency independent.

1MHz Switching500kHz Switching200kHz Switching

Square WaveVGS=0.6VVPK=0.5V

1 10 100Frequency (KHz)

Out

put P

SD (d

Bm

/Hz)

-132

-136

-140

-148

-144

Slow SwitchingSlow SwitchingSlow SwitchingSlow Switching(Switching frequency < 100kHz)

1 10 100Frequency (KHz)

Out

put P

SD (d

Bm

/Hz)

-132

-136

-140

-148

-144

Base Band Output NoiseBase Band Output NoiseBase Band Output NoiseBase Band Output Noise

VGS(V)0.5 1 1.5 2 2.5O

utpu

t PSD

@ 1

kHz

(dB

m/H

z) -120

-125

-130

-135

-140

Proposed Noise ModelProposed Noise ModelProposed Noise ModelProposed Noise Model

1/f v2 G(t)v

∑∞

=

=0

0 )cos()(k

k tkgtG ω

Gate voltage noise is used. Linearized model: AM modulations and noise superposition. Valid for most cases except LIN-OFF switching! Where g0 reflects base band noise, g1 reflects noise at switching

frequency. They are important to mixers and VCOs.

Model VerificationModel VerificationModel VerificationModel Verification(With different switching)

0.60.50.40.30.2Swing amplitude VPK (V)

0

4

8

12

16

20N

oise

ratio

g0/g

1(d

B)

Line: SimulationSymbol: Measured

Summary on Flicker Summary on Flicker Summary on Flicker Summary on Flicker NoiseNoiseNoiseNoise

Flicker noise mechanism under switching conditions has been explored experimentally.

Flicker noise should be modeled as a gate voltage noise.

Not-so-hard switched flicker noise can be modeled by AM modulations and output noise is the superposition of up-converted flicker noise.

Noise optimization through simple simulations becomes possible with the proposed model.

Results can be used directly in harmonic mixer design.

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