CMOS POWER DEVICE MODELING AND AMPLIFIER CIRCUITS … · CMOS POWER DEVICE MODELING AND AMPLIFIER...

CMOS POWER DEVICE MODELING AND AMPLIFIER CIRCUITS

BY

DORIS A. CHAN

DISSERTATION

Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering

in the Graduate College of the University of Illinois at Urbana-Champaign, 2010

Urbana, Illinois

Doctoral Committee: Professor Milton Feng, Chair Assistant Professor Yun Chiu Professor Elyse Rosenbaum Professor Jose E. Schutt-Aine

ii

ABSTRACT

A power amplifier (PA) is a key part of the RF front-end in transmitters for a local

broadband network. Today, commercial PAs are made of III-V HEMT and HBT technology

with excellent results. An integrated system-on-chip power amplifier circuit using CMOS

technology for cost-effective and spectrum-efficient high-speed wireless communication

presents major challenges because power amplifiers have been the limiting components in RF

CMOS transmitter integrated circuits (ICs). At high frequencies, the distributed effect and

power device-scaling issues put other constraints on PA design such as the trade-off between

output power (Pout) and power added efficiency (PAE).

Recently, CMOS has become attractive for low-cost and high-level integration due to

the advancement of NMOS performance with ft and fmax > 100 GHz and is available from

commercial CMOS foundries. However, the foundry-provided BSIM-RF model is unable to

accurately predict the I-V characteristics and RF behaviors (ft and fmax) of power devices with

widths of several hundred microns. Therefore, an advanced large-signal model which is able

to predict distributed nonlinear effects is crucial for the successful design of high-frequency

PAs. The microwave lumped and distributed layout parasitic effect in the 130 nm

(BSIM3v3-RF) and 90 nm (BSIM4-RF) models to accurately predict gain, output power, and

harmonic distortions of power MOSFETs at millimeter wave frequencies.

The proposed power device model is verified for single devices as well as for the

integrated power amplifier circuits in S-band and W-band applications. For S-band WiMAX

application, we have developed an accurate modeling with layout parasitic of power CMOS

devices and designed lossless matching networks to achieve single-end PA performance of

31 dB gain, 21.4 dBm output power, and 14.5% PAE at the 1 dB compression point. The

measured maximum output power is 25.5 dBm and the associated PAE is 32%.

For W-band application, a compact two-stage CMOS power amplifier is designed

iii

with gain boosting at the common gate transistor, source degeneration for the cascode

devices and LC short stub matching networks. The amplifier was fabricated and

demonstrated with excellent RF performance of 18 dB gain, 10.8 dBm linear output power,

13.3 dBm saturated power, and 11.8% PAE at 80 GHz with a minimum chip area of 0.35

mm2 in 90 nm CMOS technology. Monolithic power-combining techniques are attractive for

delivering linear power over 20 dBm at W-band range due to the size reduction of the

combiner. A W-band monolithic CPW Wilkinson power combiner of two CMOS power

amplifiers is implemented in 90 nm CMOS technology. The 77 to 83 GHz CMOS PA

achieved the 17 dB small-signal gain, 4.5 GHz 3 dB bandwidth, 10.6 dBm linear output

power, 12.3 dBm saturated power, and 3.9% PAE at 80 GHz.

iv

To my family

v

ACKNOWLEDGMENTS

First, I would like to thank my adviser, Prof. Milton Feng for his guidance throughout

my graduate school career and completion of this work. I greatly benefited from a research

environment that allowed me to broaden my horizons, and the opportunity to work in the

High Speed Integrated Circuits (HSIC) group has been a great privilege. I would like to

thank Prof. Yun Chiu, Prof. Elyse Rosenbaum, and Prof. José Schutt-Ainé for serving on my

doctoral committee and for their advice on this dissertation.

I am grateful to Dr. Henry Pao for providing a Yunni Pao Family Fellowship in my

graduate career. I would also like to thank Prof. Nick Holonyak Jr. for giving some space to

work in his lab. Thanks to United Microelectronics Corp. (UMC) for providing the 130 nm

and 90 nm CMOS foundry process for chip fabrication.

Special thanks to Dr. Richard Chan for technical discussions throughout my career.

Thanks to the past and present circuit design group members, Dr. Giang Nguyen, Mark

Stuenkel, Kurt Cimino, Eric Iverson, Sean Graham, and Huiming Xu. Also, thanks to the

processing group members, Dr. William Snodgrass, Dr. Han-Wui Then, Dr. Forest Dixon,

Adam James, Wayne Wu, Donald Chen, Rohan Bambery, and Fei Tan. All these people

have provided invaluable assistance and friendship.

I am very appreciative of Prof. Milton Feng and Prof. José Schutt-Ainé for my first

industry experiences and the opportunity to work at Xindium Technologies, Inc. I would like

to thank Dr. David Caruth, Dr. Shyh-Chiang Shen, Dr. Gabriel Walter, Jeff Feng, and Aunt

Thu for mentoring in my early industry and graduate career. Also, thanks to Dr. Ken Bower,

Dr. Shahid Yousaf, Dr. Aleksandr Kavetskiy, Galena Yakubova, and Heather Socarras for the

opportunity to work at Trace Photonics, Inc. and providing friendly working experiences.

I am also grateful for the help of Mr. James Hutchinson and Mr. Jerome Colburn with

vi

editing manuscripts throughout the journal and conference proceeding publication process.

I would also like to thank Prof. Yan N. Lwin of Western Illinois University for his

advice and guidance during my undergraduate and graduate career. Above all, I would like

to thank my family and relatives for their endless support. The love and encouragement of

my parents George and Maisie, my sisters and brother Harriet, Theresa, Richard, and Angel

have made all my endeavors possible. I cannot express enough gratitude to my family, and I

dedicate this dissertation to them.

vii

TABLE OF CONTENTS Page 1. INTRODUCTION .........................................................................................................1

1.1. Wireless Communication Technologies .................................................................1 1.2. Linear CMOS Power Amplifiers ............................................................................3 1.3. Organization of this Work ......................................................................................3

2. THEORY AND SPECIFICATION OF POWER AMPLIFIERS..................................6 2.1. Specifications of the Power Amplifier ...................................................................6 2.2. Classes of Linear Power Amplifiers .......................................................................7

3. POWER DEVICE MODELING FOR SCALING POWER MOSFET.........................9 3.1. High-Frequency Power MOSFET Issues ...............................................................9 3.2. Intrinsic and Extrinsic DC/RF Characteristics of a MOSFET Device .................11 3.3. Layout of Parasitic RC Lumped Modeling...........................................................16

4. DISTRIBUTED MODELING OF LAYOUT PARASITIC EFFECTS IN POWER DEVICE.......................................................................................................................21 4.1. Distributed Power Device Model (ICF-D1) .........................................................21 4.2. High-Frequency Scalable Distributed Modeling (ICF-D2)..................................31

5. A 2.5 GHZ CMOS POWER AMPLIFIER FOR WIMAX APPLICATION .............38 5.1. Power Amplifier Circuit Topology.......................................................................38 5.2. Power Inductor Model and Measurements ..........................................................39 5.3. Load-Pull and Source-Pull Simulation with Matching Networks Design............40 5.4. Single-End Power Amplifier Measurement Results ............................................43

6. An 80 to 85 GHz CMOS POWER AMPLIFIER FOR W-BAND APPLICATION ...48

6.1. Overview of W-Band Power Amplifier Design ...................................................48 6.2. A Two-Stage Power Amplifier Circuit Design ....................................................49 6.3. Wilkinson Power Amplifier..................................................................................61

7. CONCLUSIONS ........................................................................................................70 REFERENCES ..................................................................................................................72 AUTHOR’S BIOGRAPHY ...............................................................................................75

1

1 INTRODUCTION

1.1 Wireless Communication Technologies

Broadband wireless access fourth-generation communication systems (4G) enable

innovations that take advantage of much higher data rates, allowing users to seamlessly

reconnect to different networks even within the same session. Using 4G will in principle

allow high-quality transmission systems such as Bluetooth (IEEE 802.15.4), ZigBee (IEEE

802.15.1), UWB (IEEE 802.15.3), WLAN/Wi-Fi (IEEE 802.11), and WiMAX (IEEE

802.16). These standards cover the range of distances illustrated in Fig. 1.1. The WiMAX is

used in last mile wireless broadband access as an alternative to cable and DSL. It will work

with other shorter-range wireless standards, including Wi-Fi, which has taken off as an easy

way to provide Internet access throughout a home or business [1]. For wireless broadband

communication, the power amplifier (PA) is a key part of the RF front-end in any transmitter

(TX) system (Fig. 1.2). The PA is usually the last stage of the transmitter end and boosts the

signal power high enough that it can propagate the required distance over the wireless

medium.

The 4G required for an optimal implementation of the complete system, including

different digital and analog technologies, must be combined in a system-on-chip (SoC)

integration for high-performance wireless. Today, almost all power amplifiers on the market

are manufactured with III-V compound semiconductors because high output power and high

power efficiency are required in various applications. Currently, there is no complete system

for wireless communication with on-package integration because of the RF components. The

power amplifier, RF filters, digital software-defined radio, and antenna are different

technologies [2]. Therefore, an integrated analog power amplifier circuit using CMOS

technology for cost-effective and spectrum-efficient high-speed wireless under the WiMAX

2

2-4 GHzS band

75-110 GHzW band

50-75 GHzV band

1-2 GHzL band

40-60 GHzU band

8-12 GHzX band

12-40 GHzKau band

4-8 GHzC band

Mobile Wireless(2.5 GHz)

SpaceRadar(77 GHz)

1-500MbpsPAN:UWB or Bluetooth

54MbpsWLAN:802.11/WiFi

70MbpsWWAN:802.16/WiMAX

10m 100m 5km

Distance




10m 100m 5km




10m 100m 5km10m 100m 5km

Distance

2-4 GHzS band

75-110 GHzW band

50-75 GHzV band

1-2 GHzL band

40-60 GHzU band

8-12 GHzX band

12-40 GHzKau band

4-8 GHzC band

Mobile Wireless(2.5 GHz)

SpaceRadar(77 GHz)




10m 100m 5km

Distance




10m 100m 5km




10m 100m 5km10m 100m 5km

Distance

Fig. 1.1. Wireless standard application distances.

synth

synthPA

BB

synth

synthPA

BB

Fig. 1.2. Block diagram of wireless TX/RX system.

standard is developed in this dissertation enabling fast local wireless connection to the

network.

Similarly, in W-band applications like phased array radar, wideband communication

systems, and automotive sensors, a power amplifier is the key component in millimeter wave

integrated circuits (MMICs). Usually, power amplifier MMICs with transistors in GaAs, InP,

and HEMT technologies have been published with excellent results at W-band frequencies.

Due to the high losses in silicon at millimeter wavelengths, when combining several

monolithic power amplifier circuits in microstrip modules, it is desirable to obtain high

output power from a single chip [3].

3

1.2 Linear CMOS Power Amplifiers

Wireless technology has created market demand for highly integrated circuits, such as

a transmitter, receiver, and frequency synthesizer on a single chip. Silicon CMOS technology

has made such integration possible with the exception of the power amplifier (PA), which is

still typically implemented in non-CMOS technologies. Ideally, silicon CMOS PAs can be

developed for tight integration with other wireless building blocks.

Power amplifiers involve a balancing of many different parameters, including power-

added efficiency (PAE), linearity, maximum output power, maximum stable gain,

input/output matching, stability, heat dissipation, and breakdown voltage [4]. As with many

RF component designs, these requirements are often in conflict with one another. For

example, achieving good linearity usually comes at a cost in PAE. Linearity is typically

evaluated in terms of output third-order intercept (OIP3), 1 dB compression point (P1dB).

Improved linearity is usually achieved by backing off an amplifier’s output power from its

saturated output level; more DC power will be consumed in order to meet a given linearity

requirement.

Although many such trade-offs face a PA designer, amplifier circuits have been well

researched over the years with many different design approaches. There are many interesting

topologies at a designer’s disposal. Various methods have been used to divide and combine

RF signals, such as on-chip transformers, distributed active transformers (DATs), and the

Doherty, Balanced, and Wilkinson power combiners. In order to explore the possibilities of

PAs fabricated with silicon CMOS, single-end CMOS PAs will be explored, followed by

power-combining Wilkinson CMOS PAs.

1.3 Organization of this Work

The focus of this work is to develop system-on-chip CMOS power amplifiers to be

4

used in WiMAX (S-band) and millimeter wave (W-band) transmitter applications.

Therefore, we model and build an integrated power amplifier circuit using CMOS technology

for cost-effective and system-on-chip integration for high-speed wireless in the WiMAX (2.5

GHz) and millimeter wave W-band (75 to 110 GHz) ranges. The major challenges in CMOS

power amplifiers are nonlinear effects, power gain under stable operating conditions with

minimum amplifier stages, and lossy passive networks on the silicon substrate that cause

power loss at the transmitter output; furthermore, power amplifier design involves providing

accurate active device modeling where CMOS device models are currently inaccurate.

In Chapter 2, we will start with a brief background on the theory and specifications of

linear power amplifiers. In Chapter 3, we will discuss BSIM-RF modelling in power devices.

The theory of MOSFET device extrinsic and intrinsic parasitic characteristics and its small-

signal behavior will be explained. This leads to an Illinois Chan-Feng (ICF) model with the

layout parasitic of power CMOS devices for 1 to 10 GHz application.

Chapter 4 presents a distributed modelling in the high-frequency application. The

effects of distributed power device model optimization and extraction techniques are

incorporated to predict the current gain frequency (ft), power gain frequency (fmax), and

transducer power gain and output power in 130 nm CMOS. The Illinois Chan-Feng

Distributed lumped (ICF-D1) and scalable (ICF-D2) models are developed using small-signal

and large-signal BSIM-RF. The model is verified by comparison with measured power

device results.

In Chapter 5, a 2.5 GHz CMOS power amplifier design for WiMAX application is

discussed. The single-end PA design includes an input driver stage, a second output

cascoded stage, and matching networks. The feedback of the first stage is designed to

stabilize the gain. The impedance-matching networks between stages are designed to

maximize linearity and power delivered to the load. We have designed lossless matching

5

networks to achieve better performance in a single-end PA. Experimental results are

compared with the other published CMOS power amplifiers.

A millimeter wave CMOS power amplifier design for W-band application is

discussed in Chapter 6. A novel two-stage, 80 to 85GHz CMOS power amplifier is designed

with gain boosting at the common gate transistor, source degeneration for cascode device and

LC short stub matching networks. A Wilkinson power divider/combiner is discussed with its

amplifier circuits. The two-stage W-band and Wilkinson amplifiers’ experimental data are

reported and compared with the previous published results to validate the design

methodologies.

6

2 THEORY AND SPECIFICATION OF POWER AMPLIFIERS

2.1 Specifications of the Power Amplifier

In WiMAX application, the power amplifier is designed for a particular frequency and

all the parameters are measured at that frequency. There are two different operating

frequency ranges: 3.3 to 3.8 GHz (International) and 2.3 to 3.7 GHz (North America). The

WiMAX application is focused on 2.5 GHz, 3.5 GHz, and 3.8 GHz [5].

2.1.1 Frequency of 2.5 GHz is utilized.

2.1.2 Output power is the amount of power that needs to be delivered to the load. A WiMAX

power amplifier requires high output power, approximately < 24 dBm, for long-distance

applications [1].

2.1.3 Efficiency of output power is defined as a measure of how efficiently the supply power

is translated to output power.

sourcethefromdrawnPowerloadtodeliveredPower

=η (2.1)

2.1.4 Power added efficiency is a metric used commonly to compare PAs with different input

power levels.

DC

inout

PPP

PAE−

= (2.2)

2.1.5 Power gain/Voltage gain is the ratio of output power/voltage delivered to the load to

the input power/voltage available from the source. The power gain will be equal to the

voltage gain of the amplifier only if the input and output impedances are the same.

2.1.6 Linearity is an important metric of any power amplifier. It is desired that the amplifier

operate with high linearity, i.e., that the output power scale linearly with input power.

Compression of 1 dB and two-tone third-order intercept points are typically used to measure

linearity in Fig. 2.1.

7

One decibel (dB) compression is the input power at which the linear gain of the

amplifier has been compressed by 1 dB. The output referred 1 dB compression point (in

dBm) would then be given by the sum of the input referred 1 dB point (in dBm) and the gain

of the amplifier (in dB)

Pin(dBm)

Pout(dBm)

Pin-1dB

Pout-1dB1dB

-- Ideal

-- Actual

Pin(dBm)

Pout(dBm)

Pin-1dB

Pout-1dB1dB

-- Ideal

-- Actual

(a)

Pin(dBm)

Pout(dBm)

1

3

POIP3

PIIP3

-- Fundamental power

-- IM3 Product power

PIM

Pd

Pin(dBm)

Pout(dBm)

1

3

POIP3

PIIP3

-- Fundamental power

-- IM3 Product power

PIM

Pd

(b)

Fig. 2.1 Nonlinear characteristics measurement. (a) 1 dB compression characteristics. (b) Two-tone third-order intersection point of power amplifier circuit.

The two-tone third-order intercept point is defined as the point where the inter-

modulation (IM3) product power is equal to the fundamental power (PIM = Pd), and it is

independent of the input power levels. Assuming two interferers very close to the desired

frequency, a nonlinear output from the amplifier will generate inter-modulation products.

The most important of the products is the third-order product since it falls directly in the

frequency band of interest. This IM3 product term increases in amplitude on the order of the

cube of the fundamental amplitude and, beyond a certain input power, it can be as significant

as the fundamental tone.

2.2 Classes of Linear Power Amplifiers

In classifying power amplifiers, the most widely used distinction is how a device

handles the trade-off between linearity and efficiency. In amplifiers, the output amplitude of

the signal is a linear function of the input amplitude. In Class A, B, and AB amplifiers, the

output transistor acts as a current source, and the average output impedance during the

operation is relatively high. The current and voltage waveforms through and across the

8

output device are often full or partial sinusoids. Class A, B, AB, and C power amplifiers

depend on bias conditions which are shown in Fig. 2.2.

Class A

Class ABClass B

Class CVGS(V)

ID(mA)

IMAXLinear

SaturationCutoffClass A

Class ABClass B

Class CVGS(V)

ID(mA)

IMAXLinear

SaturationCutoff

Fig. 2.2. Class A, B, AB, and C amplifiers with bias points.

In Class A operation, the amplifier is always (100%) conducting current, which

results in a maximum efficiency (η) of 50%. However, the linearity is excellent as it

preserves the input and output waveforms without any distortion.

In Class B operation, the bias is arranged to shut off the output device for half of

every cycle so that the current conducted is 50% of the input. Therefore, power consumption

is lower than that of the Class A type, while theoretical efficiency is approximately 78%.

In Class AB operation, the amplifier conducts for 50% to 100% of a cycle, depending

on the bias levels chosen. Good linearity can be achieved with devices in this regime, with

efficiency intermediate between the Class A and B amplifiers (50% to 78%).

In Class C operation, the gate bias is arranged to cause the transistor to conduct for

0% to 50% of a cycle, which is very low power consumption, and the efficiency can reach up

to 100%. However, the output power levels will be unsuitably low for most applications.

9

3 POWER DEVICE MODELING FOR SCALING POWER MOSFET

3.1 High-Frequency Power MOSFET Issues

Over the years, power amplifiers (PAs) have been the limiting components in RF

CMOS transmitter integrated circuits (IC) due to the low breakdown voltages and

nonlinearity problems of nano-MOSFETs. At high frequencies, the distributed effect and

power device-scaling issues put other constraints on PA design such as the trade-off between

output power (Pout) and power added efficiency (PAE). The foundry-provided BSIM3v3-RF

model is unable to accurately predict the I-V characteristics and RF behaviors (ft and fmax) of

power devices with widths of several hundred microns as in Fig 3.1. Therefore, an advanced

large-signal model which is able to predict distributed nonlinear effects is crucial for the

successful design of high-frequency PAs. Our proposed approach will use the microwave

distributed effect in the 130 nm model to accurately predict output power and harmonic

distortions of power MOSFETs at high frequencies.

Fig. 3.1. Layout model comparison of device size 115 µm and 1843 µm and its RF prediction and measured results for different devices.

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)

L 120 nm x W Vgs = 0.3 -

BSIM3v3-RF Measured

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)

L 120 nm x W Vgs = 0.3 -

BSIM3v3-RF Measured

Device size L120nm x W7.2x16x1 (115 µm)

Device size L120nm x W7.2x16x1 (1843 µm)

10

MOSFET compact models are developed based on device characteristics at DC or

low frequencies and therefore lack the robust non-quasi-static descriptions needed at high

frequency. Recent modeling approaches, such as the BSIM3v3-RF model [6-7] shown in Fig.

3.2, for RF CMOS applications add lumped components to the DC core model to account for

high-frequency extrinsic parasitics. Such approaches show reasonable DC/RF fitting results

for MOSFETs with gate widths up to 100 microns. However, for a measured power device

with a large gate width of 1843 µm (capable of Pout > 80 mW), there are significant

discrepancies between the measured data and BSIM3v3-RF model results for output drain

current IDS (over-prediction of ~25%) as well as for the current cut-off frequency ft and

maximum frequency of oscillation fmax at high current density (over-prediction of ~50%).

(a)

00.05

0.10.15

0.20.25

0.30.35

0.40.45

0.5

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)

nMOSL=120 nm W=1843 µm

Vg=0.4-0.8V

BSIM-RFMeasured

00.05

0.10.15

0.20.25

0.30.35

0.40.45

0.5

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)


Vg=0.4-0.8V

BSIM-RFMeasuredBSIM-RFMeasured

(b)

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)

nMOSL=120 nmW=1843 µmVg=0.3-0.8 VVd=0.3-1.2 V

BSIM-RFMeasured

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)



(c)

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)


BSIM-RFMeasured0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)



(d)

Fig. 3.2. (a) Schematic of BSIM3v3-RF compact model. (b)–(d) Its DC / RF prediction and measured results for power device with a large gate width of 1843 µm.

Clearly, in the high-frequency region, the effect of parasitics as well as other high-

frequency mechanisms of the power devices become significant, and need to be modeled to

11

describe their dynamic performance accurately. To deliver the required output power, device

widths have to be scaled up, and eventually can be comparable to the wavelengths of the

signals in the high-frequency region. Hence, a distributed large-signal model is a must for PA

design. In addition to the power device scaling issue, precise knowledge of nonlinear

characteristics is also very important since the harmonic distortions determine the error of

predicted PAE derived using maximally-flat-waveform analysis.

3.2 Intrinsic and Extrinsic DC/RF Characteristics of a MOSFET Device

In theory, the DC I-V characteristics of the MOSFET device in the active and triode

regions are defined using Eqs. (3.1) and (3.2).

Active region ( )22 tgs

oxd VV

LWuC

I −⎟⎠⎞

⎜⎝⎛= (3.1)

Triode region ( )[ ]222 dsdstgs

oxd VVVV

LWuCI −−⎟

⎠⎞

⎜⎝⎛= (3.2)

From the DC bias conditions, the small-signal transconductance, intrinsic input of the

resistances, and capacitances can be determined. The transconductance follows from the

standard definition of a MOSFET device as

( )tgsox

m VVL

WuCg −⎟⎠⎞

⎜⎝⎛=

2 (3.3)

The small-signal equivalent circuit of a MOSFET is shown in Fig. 3.3. The intrinsic

elements include gm, Cgs, Cgd, Cds, Rgs, and τi, which are functionally dependent on biasing

conditions. The extrinsic elements include Lg, Rg, Cgp, Ls, Rs, Rd, Cdp, and Ld, which are all

independent of the biasing conditions.

12

ωτjmeg

Fig. 3.3. Determination of the small-signal intrinsic and extrinsic parasitic resistances,

capacitances, and inductances.

From the RF characterization, the input capacitance can be found from a

determination of the maximum current gain frequency, tf , from S-parameter measurements.

Current gain is extrapolated from |H21(ωt)| = 1,

( ) ( )22112112

2121 11

2SSSS

SH+⋅−+⋅

⋅= (3.4)

The unity current gain cut-off frequency, ft, is determined from an extrapolation of H21 versus

frequency.

( )21Hmagfreqft ⋅= (3.5)

The small-signal current gain frequency relative to extrinsic and intrinsic MOSFET

parameters [8-10] is as follows:

( )2/122

111

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+++−

⎥⎥⎦

⎤

⎢⎢⎣

⎡++⎟

⎟⎠

⎞⎜⎜⎝

⎛ +++⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++

=

gs

dgsm

ds

s

ds

s

gs

dgsdm

gs

dpgpdg

ds

sd

gs

m

t

CC

RgRR

RR

CC

RRgC

CCCR

RR

Cg

fπ

(3.6)

For the case 00 == dpgp CandC

( )2/122

111

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+++−

⎥⎥⎦

⎤

⎢⎢⎣

⎡++⎟

⎟⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++

=

gs

dgsm

ds

s

ds

s

gs

dgsdm

gs

dg

ds

sd

gs

m

t

CC

RgRR

RR

CC

RRgCC

RRR

Cg

fπ (3.7)

13

For the case Cgp = 0, Cdp = 0, and ∞=dsR

( ) ( )2/122

11

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡++−

⎥⎥⎦

⎤

⎢⎢⎣

⎡++

=

gs

dgsm

ds

s

gs

dgsdm

gs

m

t

CC

RgRR

CC

RRg

Cg

fπ

(3.8)

For the first-order approximation with Cgp = 0, Cdp = 0, and ∞=dsR

( ) ( ) dgsmds

sdgsd

m

gs

t

CRgRR

CRRgC

f++++= 1

21π

(3.9)

If the parasitic series resistances, inductance, and transmission lines are considered to have

minimal effects at moderate frequencies (2 to 15 GHz), it follows that the high-frequency

current gain is determined from a simple analysis of the remaining elements as follows:

( ) ( )gdgs

m

in

mt CC

gC

gf

+==

ππ 22 (3.10)

Similarly, the unilateral power gain can be calculated from the S-parameter

measurement. The maximum frequency of oscillation of the MOSFET device is extrapolated

at U(ωmax) = 1,

( )12211221

21221

Re221

SSSSkSS

U⋅−⋅

−= (3.11)

where 2112

221122211

222

211

21

SSSSSSSS

k⋅

⋅−⋅+−−=

The maximum current gain frequency is determined from an extrapolation of U versus

frequency.

( )Umagfreqfmax ⋅= (3.12)

14

The maximum power gain is achieved when the device is complex conjugate matched

at both the input and the output. For the simplified small-signal equivalent circuit, the

maximum power gain is given by in

out

in

mmax R

RC

gG ⋅⋅= 22

2

41

ω.

in

outt

in

out

in

mmax R

Rf

RR

Cg

f ⋅⋅=⋅⋅=21

221

π (3.13)

The maximum intrinsic gm and ft occur just when the drain voltage is sufficient to

saturate the electron velocity in Fig. 3.4, because the electric field limited velocity saturated

current and also the mobility decrease at the high apply bias Vgs as shown in Fig. 3.5 (a). The

gm degradation in Fig. 3.5 (b) is the effective channel mobility as a function of increasing

transverse electric field across the gate oxide and the source-drain series resistances [11-12].

The ft follows the intrinsic behavior of the bias dependent and transient delays of both

intrinsic and external resistances and capacitances (gm, Cgs, Cgd, and Rds) in Eq. 3.14. As gate

voltage increases, the gate-to-drain capacitance, Cgd, decreases and the gate-to-source

capacitance, Cgs, increases while the total capacitance (Cgs + Cgd) is dominated by Cgs. The

drain source output resistance, Rds, is only a few times greater than Rd and Rs and cannot be

neglected. Therefore, the parasitics effect modeling in large-scale power devices is

important.

( )2/122

111

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+++−

⎥⎥⎦

⎤

⎢⎢⎣

⎡++⎟

⎟⎠

⎞⎜⎜⎝

⎛ +++⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++

=

gs

dgsm

ds

s

ds

s

gs

dgsdm

gs

dpgpdg

ds

sd

gs

m

t

CC

RgRR

RR

CC

RRgC

CCCR

RR

Cg

fπ (3.14)

( )

gsCRC

Lg

m

gssdgd

ds

sd

sat

g

t gC

RRCR

RRLf

ττ

τ

νπ++⋅+⎟⎟

⎠

⎞⎜⎜⎝

⎛ ++⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=

4434421444 3444 21

12

1 (3.15)

where ( )g

gdgssatm L

CCvg

+=

15

Fig. 3.4. Nonlinear characteristics of the unity current gain (ft), the transconductance, and the gate source capacitance depend on applied gate source voltage.

Fig. 3.5. (a) Measured hole mobility at 300 K and 77 K vs. effective normal field for several substrate doping concentrations [11]. (b) Measured characteristics of transconductance, gm,

depend on applied bias voltage.

0

100

200

300

400

500

600

700

0.2 0.4 0.6 0.8 1.0Vgs (V)

g m (m

S/m

m)

Vds =1.2

Vds =0.5 V

Vds =0.1 V

Vds =0.3 V

Vds =0.7 V

Vds =0.9 eff

satc μ

νε =

( ) sattgsieff

m VVL

WCug ν−⎟

⎠⎞

⎜⎝⎛=

2

⎟⎠⎞

⎜⎝⎛ += id

sieff QQ

311

εξ

Jd (mA/mm)10 100

f t (G

Hz)

10

20

30

40

50

60

70

Cgs

(pF)

1.0

1.5

2.0

2.5

3.0

3.5

4.0

g m (m

S)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4Measured ftCalculated ftMeasured CgsMeasured gm

gs

mt C

gfπ2

≈

Vds =1.2 V Vgs =0.3-0.8

Nonlinear transconductance and nonlinear stored charge

16

3.3 Layout of Parasitic RC Lumped Modeling

For the power device modeling with the core of the BSIM3v3, we add an additional

capacitor connected parallel with Cgs and a series gate resistor, which compensates the error

between model and measured values in [13]. Also, a lumped resistance network, which

includes a gate resistor, a drain-to-body series resistor and capacitor, and a source-to-body

series resistor and capacitor, are used for GHz communication [14]. In our first modeling

approach, we have developed the Illinois Chan-Feng (ICF) model by incorporating the

external extrinsic parameters of overlap capacitances (Cgsx, Cdsx) and wire resistances (Rgx,

Rdx, Rsx) into the BSIM3v3 for accurate DC I-V and RF linearity prediction of a large-width

power CMOS device as shown in Fig. 3.6.

0.30.20.2101.53840340

340

L(nm)

0.2

Rdx

(Ω)

0.60.23.50.61536

Rsx

(Ω)Rgx

(Ω)Cdsx

(pF)Cgsx

(pF)W

(µm)

0.30.20.2101.53840340

340

L(nm)

0.2

Rdx

(Ω)

0.60.23.50.61536

Rsx

(Ω)Rgx

(Ω)Cdsx

(pF)Cgsx

(pF)W

(µm)

Fig. 3.6. Illinois Chan-Feng power device model schematic.

We employed a UMC 130 nm process and triple n-well devices with a wider gate

length of 340 nm in this power amplifier design because the deep n-well contacts improve

current-handling capabilities at the source and drain contacts. We chose devices with widths

of 1536 µm and 3840 µm and characterized the S-parameters to model the external

parameters of the ICF model. Compared to the measured data of an L 0.34 × W 1536 µm

device, the BSIM3v3 model DC I-V results over-predict by ~20% at high current (250 mA),

17

as shown in Fig. 3.7 (b); however, the ICF model predicts measured data well over a wide

bias range.

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 0.5 1 1.5 2 2.5 3VDS (V)

IDS (A

)L 340 nm x W 1536 μm

Vgs = 0.8 V

BSIM3 ICF Measure

Vgs = 1.2 V

Vgs = 1.6 V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 0.5 1 1.5 2 2.5 3VDS (V)

IDS (A

)L 340 nm x W 1536 μm

Vgs = 0.8 V

BSIM3 ICF Measure

BSIM3 ICF Measure

Vgs = 1.2 V

Vgs = 1.6 V

(a) (b)

Fig. 3.7. (a) Power device L 0.34 × W 1536 µm. (b) DC I-V of the driver stage power device for ICF and BSIM3v3 models, and measurement.

J (mA/μm)10-5 10-4 10-3 10-2 10-1 100

ft (G

Hz)

0

5

10

15

20

25

30

fmax

(GH

z)

0

10

20

30

40

50

60ft Measft ICF ft BSIM3v3-RF fmax Measfmax ICFfmax BSIM3v3-RF

Vds = 3.3VVgs = 0.4-1.6 V

L 340 nm x W 1536 μm

J (mA/μm)10-5 10-4 10-3 10-2 10-1 100

ft (G

Hz)

0

5

10

15

20

25

30

fmax

(GH

z)

0

10

20

30

40

50


Vds = 3.3VVgs = 0.4-1.6 V

L 340 nm x W 1536 μm

Fig. 3.8. Frequencies ft and fmax of the driver stage power device for ICF and BSIM3v3 model

simulations, and measurement.

For RF comparison, ft and fmax are extracted at 5 GHz in Fig. 3.8. The BSIM3v3

model’s ft and fmax over-predict by ~20% and 50%, respectively, at the design current, while

the ICF model closely agrees with the measured RF results. Similarly, the DC and RF

comparisons of the larger gate width device 3840 µm are shown in Fig. 3.9 (a) and (b),

respectively.

18

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.5 1 1.5 2 2.5 3VDS (V)

IDS

(A)

L 340 nm x W 3840 μm

Vgs = 0.6 V

BSIM3 ICF Measure

Vgs = 1 V

Vgs = 1.2 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.5 1 1.5 2 2.5 3VDS (V)

IDS

(A)

L 340 nm x W 3840 μm

Vgs = 0.6 V

BSIM3 ICF Measure

BSIM3 ICF Measure

Vgs = 1 V

Vgs = 1.2 V

(a)

J (mA/μm)10-3 10-2 10-1 100 101

ft (G

Hz)

0

5

10

15

20

25

30

fmax

(GH

z)

0

20

40

60

80


Vds = 3.3VVgs = 0.4-1.4 V

L 340 nm x W 3840 μm

J (mA/μm)10-3 10-2 10-1 100 101

ft (G

Hz)

0

5

10

15

20

25

30

fmax

(GH

z)

0

20

40

60

80


Vds = 3.3VVgs = 0.4-1.4 V

L 340 nm x W 3840 μm

(b)

Fig. 3.9. (a) DC I-V of the output stage power device for ICF and BSIM3v3 models, and measurement. (b) Frequencies ft and fmax of the output stage power device for ICF and

BSIM3v3 model simulations, and measurement.

A device nonlinearity model can be analyzed with the Volterra series representation.

The Volterra transfer functions clearly bring out the frequency-dependent nature of transistor

distortion [15-17]. The third-order Volterra kernel appearing in Eq. (3.16) is shown where

the intermodulation distortion of various mixing frequency 211 ωωκ −= , 12 2ωκ = , and

213 2 ωωκ −= , the corresponding output-intercept point is

( ) ( ) ( ) 31

211 ,,, sdbasbasads vGvGvGi ooo ωωωωωω ++= (3.16)

( ) ( )( ) 2/1

2111

2/311

213,4

32ωωω

ωωω

−⋅=−

G

GOIP (3.17)

19

The second derivative of the ft versus Id curve is related to third-order distortion (HD3)—i.e.,

the more linear ft versus Id, the smaller the third-order distortion—the high-frequency

distortion at a DC operating point (Id, Vgs) can be written as depending on the ft,:

⎥⎦

⎤⎢⎣

⎡=

T

TgHDωω

6log20

''

103 , where LR

g210 3−

= and 2

2''

DS

TT I∂

∂=

ωω (3.18)

The calculated HD3 versus measured results are shown in Fig. 3.10 (a). The output intercept

point, OIP3, can be written as a function of ft and estimated from fmax [12]:

0

21

''3'

8

=

=

TT

TOIPω

ωω (3.19)

2

23

DS

max

max

If

fOIP

∂∂

≈ (3.20)

(a) (b)

Fig. 3.10. (a) HD3 and (b) OIP3 of BSIM3v3 model and ICF model simulations, and measurement.

The output intercept characteristic of an nMOS device with a gate length of 340 nm

and 1536 µm width calculated using BSIM3v3 modeled device parameters is compared to

that using measured device data in Fig. 3.10 (b). The complex bias dependence of

( )213 2 ωω −OIP , including the occurrence of distinct peaks, is predicted for the magnitude

and phase of device. The BSIM3v3’s scalability, linearity, and bias current estimation are

-110

-105

-100

-95

-90

-85

-80

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Id (A)

HD

3 (dB

)

BSIM3v3-RF ICF Measure

⎥⎦

⎤⎢⎣

⎡=

T

TgHDωω

6log20

''

103

LRg

210 3−

=2

2''

DS

TT I∂

∂=

ωωwhere and

L 340 nm x W 1536 μm

-110

-105

-100

-95

-90

-85

-80

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Id (A)

HD

3 (dB

)



⎥⎦

⎤⎢⎣

⎡=

T

TgHDωω

6log20

''

103

LRg

210 3−

=2

2''

DS

TT I∂

∂=

ωωwhere and

L 340 nm x W 1536 μm

0

1

2

3

4

56

7

8

9

10

0 0.1 0.2 0.3 0.4 0.5Id (A)

OIP

3 (dB

m)


0

21

''3'

8

=

=

TT

TOIPω

ωω

L 340 nm x W 1536 μm

2max

2max

3

DSIf

fOIP

∂∂

≈

0

1

2

3

4

56

7

8

9

10

0 0.1 0.2 0.3 0.4 0.5Id (A)

OIP

3 (dB

m)



0

21

''3'

8

=

=

TT

TOIPω

ωω

L 340 nm x W 1536 μm

2max

2max

3

DSIf

fOIP

∂∂

≈

20

very inaccurate for wider-power devices, while the ICF model more closely matches

measurement results.

21

4 DISTRIBUTED MODELING OF LAYOUT PARASITIC EFFECTS IN

POWER DEVICE

4.1 Distributed Power Device Model (ICF-D1)

A full illustration of the proposed physical layout of the Illinois Chan-Feng

Distributed (ICF-D1) model, is given in Fig. 4.1. At high frequencies, both the parasitics and

the distributed nature of this large-size power device layout are significant. The foundry-

provided BSIM3v3-RF large-signal model fits well only for small devices with gate width

approximately < 150 µm. Therefore, we have developed the ICF-D1 model by incorporating

external distributed parameters into the BSIM3v3-RF model. In the ICF-D1 model, several

sections of lumped components corresponding to each unit cell of a fixed number of fingers

are proposed to effectively describe the distributed effects. The transistor is then separated

into extrinsic and intrinsic contributions. The intrinsic elements of each unit cell depend on

the bias conditions and geometry of the active area of the device, and thus they are scalable.

Figures 4.1 and 4.2 show the perspective 3D and 2D layouts of a MOSFET, with

circuit elements indicating the parasitic inductances and capacitances due to the input and

output manifolds. These inductances and capacitances model the transmission line behavior

of the manifolds as well as metallization capacitances between the three terminals of the

device. The resistances of the input and output manifolds, which consist of thick metal, are

negligible compared to the gate, source, and drain resistances of the MOSFET.

There are additional extrinsic resistances and capacitances that vary with unit width to

account for high-frequency parasitics, which are also scalable (Fig. 4.3). The outermost

extrinsic inductances and capacitances, due to the input and output manifolds of unit-cell

combining structures, are then added to complete the distributed model (Fig. 4.4). These

structures are typically fixed, and hence are non-scalable. Devices of a 120 nm RF CMOS

22

process have been thoroughly characterized and simulated using ICF-D1 models to illustrate

the model robustness.

RgRs Rd

Cdsx

Cdgx

Cgsx

Cdsix

Cgsix Cgdix

G

S

D

RgRs Rd

Cdsix

Cgsix Cgdix

Lg

Ld

Ls

W

NF

L

M

Wtot=W x NF x M

RgRs Rd

Cdsx

Cdgx

Cgsx

Cdsix

Cgsix Cgdix

G

S

D

RgRs Rd

Cdsix

Cgsix Cgdix

Lg

Ld

Ls

W

NF

L

M

Wtot=W x NF x M

Fig. 4.1. 3D distributed physical layout and schematic view.

Fig. 4.2. Layout of large-size power devices.

Fig. 4.3. Single lump section of the distributed ICF-D1 model.

Fig. 4.4. Schematic of the distributed ICF-D1 model.

23

The inductances associated with the input and output manifold transmission lines are

defined as Lg, Ld, and Ls respectively. The capacitances associated with the manifolds are

lumped together with the gate-source, gate-drain and drain-source metallization capacitances

and are modeled as Cgsx, Cgdx, and Cdsx. The extrinsic values of Lg, Ld, Ls, Cgsx, Cgdx, and Cdsx

will remain constant versus unit width for a fixed number of gate fingers. Figure 4.3

illustrates a “unit-MOSFET” cell. A single-gate unit cell consists of several parallel gate

fingers. Figures 4.2 and 4.4 show parallel unit cells connected together to form a distributed

power device. The device’s total width is equal to the product of the unit finger width, W,

the number of gate fingers, NF, and the multiple cells, M, in Figs. 4.1 and 4.2.

4.1.1 Extrinsic inductances and scalable extrinsic resistances extraction

In order to determine the scalable extrinsic contributions of the gate-source, gate-

drain, and drain-source capacitances, inductances, and resistances, it is reasonable to

accurately de-embed the non-scalable extrinsic MOSFET. At higher frequencies, the

transmission line extrinsic inductor can be determined by measuring the S-parameters of the

MOSFET versus frequency under the bias conductions Vds = 0 V and Vgs > Vbi, where Vbi is

the Shottky diode forward-biased turn-on voltage. Since the MOSFET has no small-signal

gain at Vds = 0 V, this measurement is called a “cold-FET” measurement [18]. To determine

the frequency dependence of the elements in T-topology, such as the circuit in Fig. 4.5, only

cold z-parameters of first-order terms are considered. The inductors Lg, Ld, and Ls can be

calculated from the imaginary part of the z-parameters at high frequencies using the

following equations:

( )sgg

sxgx LLjqInkTRRZ ++++≅ ω11 (4.1)

ssx LjRZZ ω+≅≅ 2112 (4.2)

( )sdsxdx LLjRRZ +++≅ ω22 (4.3)

24

Fig. 4.5. Simplified schematics of extrinsic parasitic using T-model extraction at high

frequency.

The resistances Rg, Rd, and Rs can be calculated from the real part of the z-parameters.

The scalable distributed resistance (Rgx, Rdx, and Rsx) Rix is based on the physical layout

structure and scales as totiix WRR ⋅= with parallel connections from the top of the thick metal

layers and via holes to the bottom of the active device area. The measured resistances scale

in a directly proportional manner to the inverse of total device width, as shown in Fig. 4.6.

From the slopes of the lines, the gate, drain, and source resistances values are Rg = 0.335

Ω*mm, Rd = 0.308 Ω*mm, and Rs = 0.41 Ω*mm.

0

0.5

1

1.5

2

2.5

3

3.5

0 0.002 0.004 0.006 0.008 0.011/Wtot (µm)

Res

ista

nce

(Ω)

RgRdRs

nMOSL=130nmVds=0VVgs=0.8V

0

0.5

1

1.5

2

2.5

3

3.5

0 0.002 0.004 0.006 0.008 0.011/Wtot (µm)

Res

ista

nce

(Ω)

RgRdRs

nMOSL=130nmVds=0VVgs=0.8V

Fig. 4.6. Measured extrinsic resistances vs. inverse of total width for three devices.

25

4.1.2 Scalable and non-scalable extrinsic capacitances extraction

To determine the extrinsic contributions of the gate-source, gate-drain, and drain-

source manifold and metallization capacitances, the total capacitances measured between the

terminals of the devices, Cgst, Cgdt, and Cdst, can be separated into those which are constant

versus the total gate width, Wtot (Cgsx, Cgdx, and Cdsx), and those which scale proportionally to

Wtot (Cgs, Cgd, and Cds ).

The three total capacitances can be determined by measuring the S-parameters of the

MOSFET versus frequency under the bias conditions, Vds = 0 V and Vbd < Vgs < Vp , where

Vbd is the reverse-biased diode breakdown voltage and Vp is the channel pinch-off voltage.

At low frequencies, the impedances of the inductances Lg, Ld, and Ls and resistances Rgx, Rdx,

and Rsx will be negligible compared to the impedance of the capacitances. The simplified

capacitor π topology is shown in Fig. 4.7 and total extrinsic capacitances are extracted at Vgs

= –0.5 V with the following equations:

( ) ( ) gstgsxtotgsix CCWCYY ωω =+=+ 1211Im (4.4)

( ) ( ) gdtgdxtotgdix CCWCY ωω −=+−=12Im (4.5)

( ) ( ) dstdsxtotdsix CCWCYY ωω =+=+ 1222Im (4.6)

Fig. 4.7. Simplified schematic of extrinsic parasitic using π model extraction at low frequency.

26

Cdst = 0.0019Wtot + 0.062

Cgst = 0.0005Wtot + 0.0357

Cgdt = 0.0004Wtot - 0.00940

0.51

1.52

2.53

3.54

0 500 1000 1500 2000Wtot (µm)

Cap

icat

ance

(pF) Cgst (pF)

Cgdt (pF)Cdst (pF)

nMOSL=130nmVds=0VVgs=-0.5V

Cdst = 0.0019Wtot + 0.062

Cgst = 0.0005Wtot + 0.0357

Cgdt = 0.0004Wtot - 0.00940

0.51

1.52

2.53

3.54

0 500 1000 1500 2000Wtot (µm)

Cap

icat

ance

(pF) Cgst (pF)

Cgdt (pF)Cdst (pF)

nMOSL=130nmVds=0VVgs=-0.5V

Fig. 4.8. Measured extrinsic capacitance vs. total width for three devices.

The three total capacitances Cgst, Cgdt, and Cdst of each FET are directly proportional

to total device widths in Fig. 4.8. As shown in Eqs. (4.4)–(4.6), the three y-intercepts of

large-width PA devices determine the parasitic manifold capacitances Cgsx = 36 fF, Cgdx = 9.4

fF, and Cdsx = 62 fF, which are non-scalable extrinsic capacitances. The slopes of the lines

are equal to the normalized scalable extrinsic capacitances along the total width of the finger.

The three scalable capacitor values are Cgsix = 0.5 pF/mm, Cgdix = 0.4 pF/mm, and Cdsix = 1.9

pF/mm.

4.1.3 Experimental validation

High-frequency on-wafer SOLT calibration measurement is carried out with an

E8364 network analyzer and 4142 DC supply. On-wafer SOLT calibration standards are

used in the DC and RF measurements, which allows the measurement reference planes to be

shifted to inside the test set, past the probe tips. The MOSFET devices are measured from

0.5 to 40 GHz with 0.1 GHz steps. The ICF-D1 model is optimized in the Agilent Design

System (ADS). We chose devices with widths of 115 µm, 921 µm, and 1843 µm and

characterized the S-parameters to model the external parameters of the ICF-D1 model.

Detailed DC-IV characteristic results are measured for a 120 nm MOSFET (W = 1843 µm) in

Fig.4.9. Compared to the BSIM3v3-RF model, the ICF-D1 model accurately predicts the DC

27

I-V curves with less than 2% error. From small-signal S-parameter measurements, ft and fmax

predictions are shown in Figs. 4.10 and 4.11. The accuracy of the ICF-D1 model is within

10% across the bias points [19].

00.05

0.10.15

0.20.25

0.30.35

0.40.45

0.5

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)


Vg=0.4-0.8V

BSIM-RF

MeasuredICF-D1

00.05

0.10.15

0.20.25

0.30.35

0.40.45

0.5

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)


Vg=0.4-0.8V

BSIM-RF

MeasuredICF-D1BSIM-RF

MeasuredICF-D1

Fig. 4.9. DC power device I-V characteristics for BSIM3v3-RF and ICF-D1 models vs. measured results.

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)


BSIM-RF

MeasuredICF-D1

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)


BSIM-RF


MeasuredICF-D1

Vd=0.3

Vd=0.6

Vd=0.9

Vd=1.2

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)


BSIM-RF

MeasuredICF-D1

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f t (G

Hz)


BSIM-RF


MeasuredICF-D1

Vd=0.3

Vd=0.6

Vd=0.9

Vd=1.2

Fig. 4.10. Power device ft characteristics for BSIM3v3-RF and ICF-D1 models vs. measured

results.

28

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)


BSIM-RF

MeasuredICF-D1

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)


BSIM-RF


MeasuredICF-D1 Vd=0.3

Vd=0.6

Vd=0.9

Vd=1.2

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)


BSIM-RF

MeasuredICF-D1

0

20

40

60

80

100

120

1 10 100 1000Id/W (μA/μm)

f max

(GH

z)


BSIM-RF


MeasuredICF-D1 Vd=0.3

Vd=0.6

Vd=0.9

Vd=1.2

Fig. 4.11. Power device fmax characteristics for BSIM3v3-RF and ICF-D1 models vs.

measured results.

For large-signal model verification, an Agilent E8364 network analyzer was used to

sweep the input power to the device from –25 to 0 dBm in 1 dB steps at fo = 3.5 GHz. The

output powers into a 50 Ω load at fo and its harmonics were measured using an HP 8565E

spectrum analyzer. The loss between the sweeper and the device input at 3.5 GHz and the

loss between the device output and the spectrum analyzer at 3.5 GHz and its harmonics were

determined and removed from the measurements. A one-tone harmonic balance simulation

was performed at the same bias points using the BSIM3v3-RF and ICF-D1 models for a

device of length 120 nm and width 1843 µm. Figure 4.12 shows the measured and simulated

one-tone results at class A bias point at 3.5 GHz. The power device transducer power gain

comparison is shown in Fig. 4.13. The BSIM3v3-RF model over-predicts by ~ 1.5 dB, and

the ICF-D1 agrees with measurement.

29

4

4.5

5

5.5

6

6.5

7

7.5

-25 -20 -15 -10 -5 0 5 10Pout (dBm)

Gai

n (d

B)

Vg=0.6 VVd=1.2 Vfreq=3.5 GHz

BSIM-RF

MeasuredICF-D1

nMOSL=120 nmW=1843 µm

4

4.5

5

5.5

6

6.5

7

7.5

-25 -20 -15 -10 -5 0 5 10Pout (dBm)

Gai

n (d

B)


BSIM-RF


MeasuredICF-D1MeasuredICF-D1

nMOSL=120 nmW=1843 µm

Fig. 4.12. BSIM3v3-RF and ICF-D1 models, and measured results, of transducer power gain

vs. output power.

At 0 dBm input power, the output power of the measured device shows 4.77 dBm (~3

mW), the BSIM3v3-RF model shows 6.91 dBm (~ 4.91 mW), and the ICF-D1 model shows

5.34 dBm (~ 3.41 mW) in Fig. 4.13. The BSIM3v3-RF model over predicted an ~ 2.4 dBm

error in the fundamental output power. Therefore, the BSIM3v3-RF model error is ~ 63%

and the ICF-D1 model error is ~13% compared to measured results.

-120

-100

-80

-60

-40

-20

0

-28

-24

-20

-16

-12 -8 -4 0

Pin (dBm)

Pout

(dB

m)

f3

f2

f0


BSIM-RF

MeasuredICF-D1

L=120 nmW=1843 µm

-120

-100

-80

-60

-40

-20

0

-28

-24

-20

-16

-12 -8 -4 0

Pin (dBm)

Pout

(dB

m)

f3

f2

f0


BSIM-RF


MeasuredICF-D1MeasuredICF-D1

L=120 nmW=1843 µm

Fig. 4.13. BSIM3v3-RF and ICF-D1 models, and measured results, of output power

harmonics characteristics of power devices (L = 120 nm).

30

Similarly, a device gate length 340 nm comparison of BSIM3v3-RF, ICF, and ICF-D1

models and measurement results are shown in Fig. 4.14. The BSIM3v3-RF model over

predicted for ~ 5 dBm and the ICF-D1 model is close to measurement results. The ICF-D1

model predicts well for fundamental and second harmonics compared to BSIM3v3-RF.

However, the ICF-D1 model did not predict well for the third-order harmonics because the

model did not modify intrinsic parts of the small-signal BSIM3v3-RF model.

-110-100-90-80-70-60-50-40-30-20-10

01020

-28

-26

-24

-22

-20

-18

-16

-14

-12

-10 -8 -6 -4 -2 0

Pin (dBm)

P out

(dB

m)

BSIM

MeasuredICF-D1 ICF

nMOSL=340 nmW=1538 µmVg=1 VVd=3.3 V

f3

f2

f0

-110-100-90-80-70-60-50-40-30-20-10

01020

-28

-26

-24

-22

-20

-18

-16

-14

-12

-10 -8 -6 -4 -2 0

Pin (dBm)

P out

(dB

m)

BSIM

MeasuredICF-D1 ICFBSIM

MeasuredICF-D1 ICF

nMOSL=340 nmW=1538 µmVg=1 VVd=3.3 V

f3

f2

f0

Fig. 4.14. BSIM3v3-RF, ICF-L, and ICF-D1 models, and measured results, of output power

harmonic characteristics of power devices (L = 340 nm, freq = 2.5 GHz).

31

4.2 High-Frequency Scalable Distributed Modeling (ICF-D2)

MOSFET compact models are developed based on the device characteristics at DC or

low frequencies. The extrinsic layout parasitic effect is very important for high frequency RF

MOSFET applications. The scalable ICF-D2 distributed layout parasitic effects model is

extended for W-band amplifier design. The device test structure is shown in Fig. 4.15. The

ICF-D2 model is implemented with the BSIM4-RF model in Fig. 4.15 with scalable and

nonscalable parts. The distributed model of multiple unit cell connection is shown in Fig.

4.16.

Fig. 4.15. A 90 nm MOSFET device (W= 64 µm) and a single unit of the ICF-D2 model integrated with the BSIM4-RF model.

Fig. 4.16. High-frequency distributed ICF-D2 model integrated with the BSIM4-RF model.

32

The device’s total width is equal to the product of the unit finger width, W, the

number of gate fingers, NF, and the multiple cells, M. The parallel multiple unit cells, M, are

connected together to form a high-frequency distributed power device. A single-gate unit

cell consists of several parallel gate fingers. It is separated into the extrinsic device cell

which is scalable with the device’s unit width (UW) and finger (F). The extrinsic schematics

of the capacitances and resistances (Cgsix, Cgdix, Cdsix, Rg, Rd, and Rs) are scalable with the UW

and F in Fig. 4.16. The extrinsic pad capacitances (Cgsx, Cgdx, and Cdsx) are scalable with the

finger and the extrinsic inductances (Lg, Ld, and Ls) are nonscalable with device parameters.

The model parameter equations are the following:

( )( ) fFFUWCC gsigsix ⋅⋅⋅= 05.0 (4.7)

( )( ) fFFUWCC gdigdix ⋅⋅⋅= 05.0 (4.8)

( )( ) fFFUWCC dsidsix 1005.0 +⋅⋅⋅= (4.9)

( )( ) fFFCC gspgsx 2⋅= (4.10)

( )( ) fFFCC gdpgdx 2⋅= (4.11)

( )( ) fFFCC dspdsx 2⋅= (4.12)

( )( ) Ω⋅⋅= FUWRR gig (4.13)

( )( ) Ω⋅= FUWRR sis (4.14)

( )( ) Ω⋅= FUWRR did (4.15)

4.2.1 Experimental model verification from 1 to 50 GHz, V-band, and W-

band

We set up an automatic DC and RF measurement program in Agilent VEE for data

collection. The power devices are measured for S-parameters from 1 to 50 GHz, V-band (50

33

GHz to 75 GHz), and W-band (75 GHz to 110 GHz) with the vector network analyzer (VNA

8510C) and the synthesized sweepers (HP 83651A and HP83621A) as in Figs. 4.17 and 4.18.

HP 8510CVector network

analyzer

HP 83621A45 MHz to 20 GHz

Synthesized sweeper

HP 83651A45 MHz to 50 GHz

Synthesized sweeper

HP 85106AMillimeter wave

controller

HP 85104A1-50 GHz50-75 GHz

75-110 GHzmm wave test set

HP 4142BModular DC

source

Device under test

GSG / V-band / W-band

probe

GSG / V-band / W-band

probe

LO

LO

RF

RF

DC DC

RF

LO

LO

RF

HP 85104A1-50 GHz

50-75 GHz75-110 GHz

mm wave test set

1-mm cable 1-mm cable

Fig. 4.17. S-parameters measurement setup (1 to 50 GHz, V-band, and W-band).

8510C

Mixer Mixer

8510C

Mixer Mixer

Fig. 4.18. S-parameters measurement setup (1 to 50 GHz, V-band, and W-band).

Calibration for VNA can be carried out with the “on-wafer” SOLT calibration standard

which is on the same substrate as in Fig. 4.19. The standards have identical pad structures to

the devices measured, which allows the measurement reference planes to be shifted from

inside the S-parameter test set in Fig. 4.20. The coplanar waveguide (CPW) transmission

line (L = 400 µm) in Fig. 4.21 is measured at three separate frequencies bands for the

34

verification of the calibration and measurement systems. The CPW insertion loss is less than

–1 dB and isolation is better than –15 dB in Fig. 4.22.

Fig. 4.19. On-wafer calibration standards.

Fig. 4.20. Measurement reference planes after

on-wafer calibration.

Fig. 4.21. CPW test structure (W = 10 µm, G = 5 µm, L = 400 µm).

The resulting S-parameters are created for the distributed two-port models of the power

devices and transmission lines. High-frequency distributed model parameters are measured

and extracted in physically based intrinsic and extrinsic parameters from 1 to 110 GHz. The

BSIM4-RF model, ICF-D2 model, and measurement comparison is shown in Fig. 4.23. The

BSIM4-RF model over predicted the 2.5 dB gain compared to measured S-parameters. The

ICF-D2 model agrees with measured S-parameters for all three band (1 to 50 GHz, V-band,

and W-band) measurements.

Measurement Reference Planes

Short Open Load Thru

35

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-40

-35

-30

-25

-20

-15

-45

-10

freq (Hz)

S11

and

S22

(dB

)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-1.0

-0.8

-0.6

-0.4

-0.2

-1.2

0.0

freq (Hz)

S12

and

S21

(dB

)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-100

0

100

-200

200

freq (Hz)

S11

and

S22

(deg

ree)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-120

-100

-80

-60

-40

-20

-140

0

freq (Hz)

S12

and

S21

(deg

ree)

W band(75-110 GHz)

V band(50-75 GHz)

(0.5-50 GHz)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-40

-35

-30

-25

-20

-15

-45

-10

freq (Hz)

S11

and

S22

(dB

)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-1.0

-0.8

-0.6

-0.4

-0.2

-1.2

0.0

freq (Hz)

S12

and

S21

(dB

)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-100

0

100

-200

200

freq (Hz)

S11

and

S22

(deg

ree)

1.0E10

2.0E10

3.0E10

4.0E10

5.0E10

6.0E10

7.0E10

8.0E10

9.0E10

1.0E11

0.0

1.1E11

-120

-100

-80

-60

-40

-20

-140

0

freq (Hz)

S12

and

S21

(deg

ree)

W band(75-110 GHz)

V band(50-75 GHz)

(0.5-50 GHz)

Fig. 4.22. S-parameter measurement of coplanar waveguide transmission line (400 µm) after

on-wafer calibration in three separate frequency bands.

1.0E102.0E10

3.0E104.0E10

5.0E10

6.0E107.0E10

8.0E109.0E10

1.0E11

0.0

1.1E11

-202468

1012

-4

14

freq (Hz)

S21

(dB)

1.0E102.0E10

3.0E104.0E10

5.0E10

6.0E107.0E10

8.0E109.0E10

1.0E11

0.0

1.1E11

-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0

-4.0

0.5

freq (Hz)

S11

(dB)

1.0E10

2.0E103.0E10

4.0E105.0E10

6.0E10

7.0E108.0E10

9.0E101.0E11

0.0

1.1E11

-8.0-7.5-7.0-6.5-6.0-5.5-5.0-4.5

-8.5

-4.0

freq (Hz)

S22

(dB)

1.0E10

2.0E103.0E10

4.0E105.0E10

6.0E10

7.0E108.0E10

9.0E101.0E11

0.0

1.1E11

-45

-40

-35

-30

-25

-20

-15

-50

-10

freq (Hz)

S12

(dB)

BSIM4-RF modelICF-D2 modelMeasured

Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V




1.0E102.0E10

3.0E104.0E10

5.0E10

6.0E107.0E10

8.0E109.0E10

1.0E11

0.0

1.1E11

-202468

1012

-4

14

freq (Hz)

S21

(dB)

1.0E102.0E10

3.0E104.0E10

5.0E10

6.0E107.0E10

8.0E109.0E10

1.0E11

0.0

1.1E11

-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0

-4.0

0.5

freq (Hz)

S11

(dB)

1.0E10

2.0E103.0E10

4.0E105.0E10

6.0E10

7.0E108.0E10

9.0E101.0E11

0.0

1.1E11

-8.0-7.5-7.0-6.5-6.0-5.5-5.0-4.5

-8.5

-4.0

freq (Hz)

S22

(dB)

1.0E10

2.0E103.0E10

4.0E105.0E10

6.0E10

7.0E108.0E10

9.0E101.0E11

0.0

1.1E11

-45

-40

-35

-30

-25

-20

-15

-50

-10

freq (Hz)

S12

(dB)


Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V

Vd = 1.2VVg = 1 V




Fig. 4.23. Comparison of BSIM4-RF model, ICF-D2 model, and measured S-parameters of device size (L 90 nm x W 2 x NF 32 x M1)

36

The measured DC-IV curve comparison plot is shown in Fig. 4.24 and measured

results agree with both BSIM4-RF and ICF-D2 models. For high-frequency amplifier

operation, the RF characteristic of the device models is significant. The measured maximum

ft = 90 GHz, and maximum fmax = 120 GHz, as shown in Figs. 4.25 and 4.26. The BSIM4-RF

model prediction is ft ~ 130 GHz, which is >30% of the measured ft = 90 GHz. The BSIM4-

RF model predicts fmax = 220 GHz, which is 90% off the measured fmax = 120 GHz. On the

other hand, the ICF-D2 model predicts well on both ft and fmax, within 10% across the biased

current range, as shown in Fig. 4.25 and 4.26 respectively.

0

5

10

15

20

25

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)

Vg=0.4-1 V

BSIM-RF

MeasuredICF-D2

nMOSL=90 nmW=64 µm

0

5

10

15

20

25

0 0.2 0.4 0.6 0.8 1 1.2Vds (V)

I ds (m

A)

Vg=0.4-1 V

BSIM-RF

MeasuredICF-D2

nMOSL=90 nmW=64 µm

Vg=0.4-1 V

BSIM-RF


MeasuredICF-D2

nMOSL=90 nmW=64 µm

Fig. 4.24. DC-IV comparison of the BSIM4-RF model, ICF-D2 model, and measured device

characteristics.

0

20

40

60

80

100

120

140

0.001 0.01 0.1 1Id/W (mA/μm)

f t (G

Hz)

nMOSL=90 nmW=64 µmVg=0-1 VVd=0.3-1.2 V

BSIM-RF

MeasuredICF-D2

Vd

0

20

40

60

80

100

120

140

0.001 0.01 0.1 1Id/W (mA/μm)

f t (G

Hz)


BSIM-RF


MeasuredICF-D2

Vd

Fig. 4.25. BSIM4-RF and ICF-D2 models vs. measured results of the ft characteristic.

37

0

40

80

120

160

200

240

0.001 0.01 0.1 1Id/W (mA/μm)

f max

(GH

z)


BSIM-RF

MeasuredICF-D2

Vd

0

40

80

120

160

200

240

0.001 0.01 0.1 1Id/W (mA/μm)

f max

(GH

z)


BSIM-RF

MeasuredICF-D2

0

40

80

120

160

200

240

0.001 0.01 0.1 1Id/W (mA/μm)

f max

(GH

z)


BSIM-RF


MeasuredICF-D2

Vd

Fig. 4.26. BSIM4-RF and ICF-D2 models vs. measured results of the fmax characteristic.

The measured 90 nm devices are summarized in Table 4.1. The measured threshold

voltage is 0.38 V, subthreshold slope (S) is 108 mV/dec, drain induced barrier lowering

(DIBL) is 133 mV/V, and Ion/Ioff is ~ 4 x 103. Those DC characteristics are approximately the

same for the different gate width devices. However, for the RF characteristics, ft increases

with device unit gate width and fmax decreases with total device gate width 256 µm. For

MMIC power amplifier design, we can choose different size devices depending on the

measured RF characteristics of the current gain, ft, and power gain, fmax, for the driver gain

stage and the output power stage.

TABLE 4.1 Summary of 90 nm device mesured DC/RF characteristics

100

145

120

95

ft (GHz)

1403862133110.90.38L90W2x32x2(128 µm)

904299133110.40.38L90W8x32x1(256 µm)

1204652133107.40.38L90W4x32x1(128 µm)

1204407133108.20.38L90W2x32x1 (64 µm)

fmax (GHz)Ion/IoffDIBL (mV/V)S (mV/dec)Vth (V)Device

100

145

120

95

ft (GHz)

1403862133110.90.38L90W2x32x2(128 µm)

904299133110.40.38L90W8x32x1(256 µm)

1204652133107.40.38L90W4x32x1(128 µm)

1204407133108.20.38L90W2x32x1 (64 µm)

fmax (GHz)Ion/IoffDIBL (mV/V)S (mV/dec)Vth (V)Device

38

5 A 2.5 GHZ CMOS POWER AMPLIFIER FOR WIMAX

APPLICATION

5.1 Power Amplifier Circuit Topology

Class AB single-end power amplifier driver and output stages are designed for a

stable input with high output power. In this frequency range, a CMOS common-source

driver stage is unstable, and an RC feedback network, shown schematically in Fig. 5.1, is

added to get stable inputs. The RC feedback network is optimized to provide unconditionally

stable device operation at the design frequency. We use ADS simulation to find the resistance

and capacitance of the feedback network that are maximized for higher gain and stable

operation. The driver-stage power device uses a W = 1536 µm nMOS, and its drain current

is approximately 95 mA.

The output stage uses the cascode device topology to increase the gain, power, and

breakdown voltage of the output power device. Since the cascoded amplifier stage is stable,

an RC feedback network is not required. The W = 3840 µm nMOS is used for delivering the

required output power, and its bias current is 200 mA. The driver and output stages consume

0.98 W of power from a 3.3 V DC supply.

2inΓ 2outΓ1inΓ 1outΓ 2sΓ1sΓ 2lΓ1lΓ Fig. 5.1. Schematic of driver and output cascoded stages.

39

5.2 Power Inductor Model and Measurements

Custom power inductors are designed for the drain voltage supply, inter-stage

matching, and output stage matching networks. The power inductors are key components of

high-performance PAs. High Q values are optimized at design frequency, and low DC

resistance is required in order to minimize supply drop. This can be achieved by increasing

the metal width and using parallel multi-layer metals to increase thickness. An ADS

momentum simulation is used to design the maximum width of the top three metal layers at

20 μm for the passive device model. Inductance and quality factors are calculated from S-

parameter measurements using the following equations:

)1()1(50

in

ininZ

Γ−Γ+

= (5.1)

( )ω

inZL

Im= (5.2)

( )( )in

in

ZZ

QReIm

= (5.3)

The thick metal inductor model is shown in blue, and the measurement results are

shown red in Fig. 5.2. The inductor’s model and measured calculation values at 2.5 GHz are

shown in Table 5.1. The inductance percentage error is 0.13% to 7.87% and the quality factor

percentage error is 6.5% to 20%. The measured quality factor data are higher than the

momentum model simulation at design frequency.

TABLE 5.1 Summary of inductor model and measurement at 2.5 GHz Lmodel (nH) Lmeas(nH) Qmodel Qmeas

0.95 1.02 9.1 12.99 1.56 1.66 10.32 15.5 1.84 1.83 11.02 13.92 2.36 2.28 10.77 11.14

40

(a)

0

2

4

6

8

10

12

14

1 2 3 4 5 6freq (GHz)

Q

2

2.2

2.4

2.6

2.8

3

3.2

3.4

L (n

H)

Q modQ measLmodLmeas

(b) Fig. 5.2. (a) Inductor 2.2 nH. (b) Measured and model comparison of 2.25 nH inductor’s

quality factor and inductance.

5.3 Load-Pull and Source-Pull Simulation with Matching Networks Design

The purpose of using matching in the amplifier design is to obtain the highest gain

and return loss at the design frequency. If there is mismatch between the amplifier source

and input, some of the power will be reflected back to the source; therefore, the input signal

power will not be amplified. Also, mismatch between the load and output of a power

amplifier causes gain reduction. Therefore, a simultaneous complex conjugate match is

obtained on both sides of the transistor to get maximum gain.

The optimum load for a power amplifier is different from the maximum conjugate

gain load for a small-signal amplifier. Real loads are rarely purely resistive, and the effect of

variable load impedance on power delivered will vary. Load impedance at the fundamental

frequency can be swept with its amplitude and phase. The output cascoded-stage transistors’

output reflection coefficients are characterized through load-pull analysis to select impedance

for the maximum linear power delivered to the load at 2.5 GHz. Using 15 dBm input power

with the different load impedances, the contour plots for maximum delivered power of 26.7

to 24.6 dBm are shown as thin dark blue lines in Fig. 5.3 (a). From load-pull optimization,

the complex conjugate of the output cascoded-stage impedance (Zout2 = 9.19 – j12.92) is

41

matched to the source (ZO = 50 Ω) in Fig. 5.3 (b) using a ZY Smith chart. One possible

solution for the matching network is shown in Fig. 5.3 (b) with series C and shunt L

networks. The motion is in a counterclockwise direction along a constant-resistance circle zC

= j0.41, and a constant-conductance circle gives the shunt inductor admittance (yL = –j2.12).

From the normalized impedance and admittance values at 2.5 GHz, the capacitance (3.1 pF)

and the inductance (1.51 nH) are plotted with thick dark gray and thick bright pink curves,

respectively, in Fig. 5.3 (a). Similarly to interstage output matching of the PA, the output of

the driver stage is optimized with load-pull simulation to match a 50 Ω load in Fig. 5.3 (b).

Output MN2

3.1 pF

1.51 nH

Zo=50

2outΓ

*2outΓ

= 9.19-j1.24*2outZ

Pdel = 26.7 - 24.6 dBm@ Pin = 15 dBm

- Pdel contour- Series C- Shunt L

Output MN2

3.1 pF

1.51 nH

Zo=50

2outΓ

*2outΓ

= 9.19-j1.24*2outZ = 9.19-j1.24*2outZ

Pdel = 26.7 - 24.6 dBm@ Pin = 15 dBm


(a)

Output MN1

2.47 pF

2.5 nH

Zo=50

2outΓ

*2outΓ

= 19.03-j5.06*2outZ

Pdel = 16.7 - 14.6 dBm@ Pin = 1 dBm


Output MN1

2.47 pF

2.5 nH

Zo=50

2outΓ

*2outΓ

= 19.03-j5.06*2outZ = 19.03-j5.06*2outZ

Pdel = 16.7 - 14.6 dBm@ Pin = 1 dBm


(b)

Fig. 5.3. (a) Load-pull and LC matching network using a ZY Smith chart for the output cascoded stage. (b). Load-pull and LC matching network using a ZY Smith chart for the

driver stage.

42

The driver stage’s input reflection coefficients are characterized through source-pull

analysis to select an impedance to give the maximum linear power delivered to the source at

2.5 GHz. From source-pull analysis with 1 dBm input power, contour plots for maximum

delivered power of 15.7 to 13.7 dBm are shown as thin dark blue lines in Fig. 5.4 (a). The

driver stage input gets maximum power at the input impedance 12.4 – j12.92. Using the

complex conjugate of the normalized impedance of the driver stage, the LC matching

network is designed as in the output cascoded stage. The output matching network’s series

capacitance is 7.32 pF and its shunt inductance is 1.81 nH as shown in Fig. 5.4 (a).

Input MN 1

7.35 pF 1.81 nH

Zo=50

1inΓ

*1inΓ

= 12.4-j12.92*1inZ

Pdel = 15.7 – 13.7 dBm@ Pin = 1 dBm


Input MN 1

7.35 pF 1.81 nH

Zo=50

1inΓ

*1inΓ

= 12.4-j12.92*1inZ = 12.4-j12.92*1inZ

Pdel = 15.7 – 13.7 dBm@ Pin = 1 dBm


(a)

Input MN 2

15.9 pF 0.94 nH

Zo=50

1inΓ

*1inΓ

= 3.99-j9.56*1inZ

Pdel = 26.7 – 14.7 dBm@ Pin = 15dBm


Input MN 2

15.9 pF 0.94 nH

Zo=50

1inΓ

*1inΓ

= 3.99-j9.56*1inZ = 3.99-j9.56*1inZ

Pdel = 26.7 – 14.7 dBm@ Pin = 15dBm


(b)

Fig. 5.4. (a) Source-pull and LC matching network using ZY Smith chart for driver stage. (b) Source-pull and LC matching network using ZY Smith chart for input cascoded stage.

43

Similarly for interstage input matching of the PA, the input of the cascoded stage is

also optimized with source-pull simulation, and LC matching networks [20] between them

are designed for maximum power as shown in Fig. 5.4 (b).

5.4 Single-End Power Amplifier Measurement Results

The single-end PA was implemented with 340 nm gate length in the UMC 130 nm RF

CMOS process. The single-end power amplifier and fabricated PA chip occupies an area of

2.6 mm × 1.2 mm, including RF and DC pads, as shown by the superimposed schematic

diagram in Fig. 5.5. At the drain gate voltage of 3.3 V, the top cascode nMOS gate is biased

at 3.3 V, and the second gate is biased at 1 V; both gates draw drain currents of 295 mA.

High-frequency on-wafer SOLT calibration and S-parameter measurement are carried

out with an Agilent 8364 network analyzer and an Agilent 8565 power spectrum analyzer as

illustrated in Fig. 5.6 (a). Collected data is de-embedded to remove all losses of the cable and

RF pads. The power amplifier is designed for a 2.5 GHz WiMAX application, and the

frequency is shifted to 2.3 GHz because of the 10% process variation of the custom inductor

Fig. 5.5. A single-end Class AB (first feedback driver and second cascode output) power

amplifier schematic and chip photo.

44

model from simulation. The measured and simulated results of S-parameters are plotted in

Figs. 5.7 and 5.8. Measured and simulated input and output matching networks are better

than –10 dB. The device achieves –3 dB bandwidth of 400 MHz, and the small-signal gain

maximum is 32 dB. The isolation is better than –40 dB.

Fig. 5.6. High-frequency S-parameter measurement setup.

PNAHP 836410Mz to 50 GHz

HP 4142BModular DC

source

Device under test

GSG probe

RF

DC DC

RF

GSG probe

-40

-35-30

-25-20

-15

-10-5

0

0

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

Freq (GHz)

S11

(dB

)

-80

-70-60

-50-40

-30

-20-10

0

S12 (dB)

S11 measS11 simS12 measS12 sim

-40

-35-30

-25-20

-15

-10-5

0

0

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

Freq (GHz)

S11

(dB

)

-80

-70-60

-50-40

-30

-20-10

0

S12 (dB)


Fig. 5.7. Power amplifier S11 and S12 parameter models and measurements.

45

At design frequency, 2.5 GHz, on-wafer SOLT and one-port power calibration

measurements are carried out with an Agilent 8364 network analyzer and an Agilent 8565

power spectrum analyzer as illustrated in Fig. 5.9. A single-tone power measurement plot is

shown in Fig. 5.10. The solid lines are simulations with the thick metal inductor model, and

the symbol shapes correspond to measurements. The measured output power at 1 dB

compression is >21.4 dB at –8 dBm input power, and it shows very good agreement with the

simulation. The large-signal gain is 31 dB, and PAE is 14.5% at 1 dB compression.

Fig. 5.9. Single-tone power calibration and measurement setup.

PNAHP 836410Mz to 50 GHz

HP 4142BModular DC

source

Device under test

RF

DC DC

RF

GSG probe

GSG probe

Spectrum Analyzer

8565E

-30

-20

-10

0

10

20

30

40

0

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

Freq (GHz)

S21

(dB

)

-25

-15

-5

5

15

25

S22 (dB)


-30

-20

-10

0

10

20

30

40

0

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

Freq (GHz)

S21

(dB

)

-25

-15

-5

5

15

25

S22 (dB)


Fig. 5.8. Power amplifier S22 and S21 parameter models and measurements.

46

The measured performance of the Class AB PA is summarized in Table 5.2 with other

published results. The two-stage, on-chip, fully integrated power amplifier demonstrates

higher power gain (31 dB) and maximum output power (25.5 dBm) compared to that of [21].

Compared to off-chip integrated PAs, the fabricated power amplifier has smaller form factor,

higher gain with better linearity, and excellent linear output power.

The parasitic (RC) incorporation of large-width nMOS is demonstrated and excellent

agreement is achieved with measurement results. The design and fabrication of a single-end

0

5

10

15

20

25

30

35

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0

Pin (dBm)

Gai

n (d

B) a

nd P

out (

dBm

)

0

5

10

15

20

25

30

35

40

PAE

(%)

Gain

Symbol – measureLine – simulation

Pout

PAE

0

5

10

15

20

25

30

35

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0

Pin (dBm)

Gai

n (d

B) a

nd P

out (

dBm

)

0

5

10

15

20

25

30

35

40

PAE

(%)

Gain

Symbol – measureLine – simulation

Pout

PAE

Fig. 5.10. Single-end power amplifier, single-tone measurement vs. simulation.

TABLE 5.2Performance summary and comparison with previously published work

[21] [22] [23] This work CMOS process 250 nm 180 nm 180 nm 130 nm Class/stages AB/2 AB&B/2 AB/1 AB/2 Gain (dB) 6 38 19 31 P1dB (dBm) 21 20.5 20.2 21.4 Pmax (dBm) 24.1 23.5 23 25.5 PAE1dB (%) 26 17 30.2 14.5 PAEmax (%) 40 45 35 32 Freq (GHz) 2.45 2.4 2.4 2.5 Vdd (V) 2 2.4 3.3 3.3 Integration Off-chip Off-chip On-chip On-chip

47

PA for 2.5 GHz WiMAX applications based on load- and source-pull analysis to match load

and source impedances simultaneously are demonstrated with a low-loss on-chip LC

matching network. Using Wilkinson power-combining techniques in Fig. 5.11 (a), the single-

end PA can be used in WiMAX applications, and the projected PA can achieve output power

>24 dBm at 1 dB gain compression point, as shown in Fig. 5.11 (b).

(a) (b)

Fig. 5.11. (a) Wilkinson power amplifier schematics. (b) Simulation results of Wilkinson power-combining technique to use with single-end power amplifiers.

0

5

10

15

20

25

30

-20 -15 -10 -5 0 5Pin (dBm)

Gai

n (d

B) a

nd P

out (

dBm

)02468101214161820

PAE

(%)

oZ

oZ

oZoZ2

4/λ

oZ2

01111 == +− PSP

21

12

212

++− ==

PPSP

21

12

313

++− ==

PPSP

48

6 An 80 to 85 GHZ CMOS POWER AMPLIFIER FOR W-BAND

APPLICATION

6.1 Overview of W-Band Power Amplifier Design

The power amplifier is the key component in monolithic millimeter wave integrated

circuits (MMWICs) applications such as phased array radar, wideband communication

systems and automotive sensors. Today, MMW amplifiers are made of III-V HEMT and

HBT technology with excellent results at millimeter wave frequencies. Recently, CMOS has

become attractive for low-cost and high-level integration due to advancement of nMOS

performance with ft and fmax > 100 GHz and is available from commercial CMOS foundries.

However, the W-band CMOS amplifier design remains as a major challenge due to lack of

accurate device modeling, low breakdown voltage, and high losses in silicon substrate at

millimeter wave frequency. Recently, 90 nm CMOS amplifiers have been demonstrated with

good gain (> 10 dB) but with low linear output power (<10 dBm) and low power added

efficiency (PAE <10%) at W-band frequency [24-28]. For millimeter wave application, as

above two-stage and Wilkinson amplifiers are discussed with the experimental results. A

compact two-stage CMOS power amplifier is designed with gain boosting at the common

gate transistor, source degeneration for the cascode device, and LC short stub matching

networks. Since the similar circuit topology is used in this circuit, only one stage is

discussed more in detail.

CMOS transceivers are typically implemented as differential circuits to reduce

susceptibility to commonmode noise. A generic single-end two-stage PA is integrated using

on-chip power-combining techniques. This design approach also improves the power gain at

low input power level compared to the single-transistor stage, and it still needs to improve the

power divider/combiner. A Wilkinson PA is essentially two single-end PAs in parallel, and

49

an additional gain stage is implemented to account for the power divider and combiner loss.

The design has been employed with a cascode topology. The cascode approach reduces the

gate-drain capacitance (Cgd) Miller multiplication effects and provides added isolation

between the input and output ports, improving amplifier stability without using feedback.

6.2 A Two-Stage Power Amplifier Circuit Design

In high-frequency applications, a cascode connection consists of a common-source

stage driving a common gate stage. The cascode derives its advantage at high frequencies

from the fact that the load for common source transistors is the low input impedance of the

common gate. The common gate transistor operates as a current buffer and does not contain

a feedback capacitance from drain to source to cause the Miller effect. Its useful

characteristic is a small amount of reverse transmission and good isolation that is required in

high-frequency amplifier circuits. Another characteristic of a cascode cell is its high output

resistance, which reduces the conversion power loss to the output load resistor.

Power gain of a common source circuit is approximately calculated from the small

signal equivalent circuit model in the Eq. (6.1) and Fig. 6.1 (a). Similarly, the small signal

equivalent circuit of a cascode cell model is shown in the Fig. 6.1 (b). The main advantage of

the cascode device is to increase ideally double the output impedance of a single common

source device. The output voltage of a cascode device is equal to the output voltage of each

active device. Therefore, the cascode device has higher gain [29] than a common source

transistor and is more attractive for power matching. For optimal power operation, additional

series capacitance at the gate of transistor T2 is required to avoid early power saturation [30].

Using the small signal equivalent model of the optimized cascode device Eq. (6.2), the output

power of the cascode device is twice that of the common source device in Eq. (6.3).

50

(a)

(b)

Fig. 6.1. (a) Schematic of the theoretical common source device and its small-signal model. (b) Schematic of the theoretical cascode device and its small-signal model.

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅=

ZV

VgVPout dsgsmdscs Re

21

, where ( )⎟⎟⎠

⎞⎜⎜⎝

⎛+= ds

ds

CjR

Z ω1 (6.1)

( ) ( ) ( )⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+

++⋅⋅+=ZVV

VVgVVPout dsdsgsgsmdsdscas 22

1Re21 21

2121 (6.2)

,where dsoptdsds VVV == 21 , gsoptgsgs VVV == 21 , and ( )⎟⎟⎠

⎞⎜⎜⎝

⎛+= ds

ds

CjR

Z ω1

cs

dsoptgsoptmdsoptcas

Pout

ZV

VgVPout

⋅=

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅⋅=

2

2Re21

(6.3)

G

D

S

1gsmVg1gsV

gsCdsCdsR1dsV

2gsmVg2gsV

gsCdsCdsR2dsV

gsmVggsV

gsCdsCdsR

dsV

51

A Class A two-stage CMOS amplifier is designed for a stable input with high gain

and compact area. The cascode device topology is chosen to increase the high gain and

breakdown voltage of the amplifier device. In the W-band frequency range, a MOSFET

cascode stage is unstable. A source degeneration CPW line is added to stabilize the input as

shown in the schematic of Fig. 6.2. The source degeneration CPW lines are designed

between the common source transistor and the common gate transistor to achieve the

maximum stable gain.

The CMOS process has inherent limitations to realize millimeter wave circuits.

Extrinsic and intrinsic parasitic elements of the CMOS process also cause the gain to become

even lower. Furthermore, gain is decreased by the lossy silicon substrate. A CPW

inductance length, Lg, is designed at the common gate transistor for gain boosting [31] and

[32]. From small-signal analysis, a conventional common gate amplifier of cascode gain is

shown in Eq. (6.4) and a common gate amplifier with positive feedback network cascode

gain is shown in Eq. (6.5) [30].

( )dsLds

ms

out RRR

gV

V //1⎟⎟⎠

⎞⎜⎜⎝

⎛+= (6.4)

( )dsLdsgsg

m

s

out RRRCL

gV

V//1

1 2 ⎟⎟⎠

⎞⎜⎜⎝

⎛+

−=

ω (6.5)

The small-signal gain is boosted to be higher than one of a conventional common gate

amplifier when the operating frequency of the common gate amplifier is lower than

gsgCL1 . Figure 6.3 shows the simulated gain curves with a different length Lg. We

compare and choose Lg of 100 µm for higher gain at 77 GHz.

52

Fig. 6.2. Cascode device with source degeneration and gain boosting schematic.

76 78 80 82 84 86 88 90 92 94 96 9874 100

-3

-2

-1

0

1

2

-4

3

freq, GHz

Gai

n (d

B)

Vg=1VVd=3V

100 µm40 µm0 µm

76 78 80 82 84 86 88 90 92 94 96 9874 100

-3

-2

-1

0

1

2

-4

3

freq, GHz

Gai

n (d

B)

Vg=1VVd=3V

100 µm40 µm0 µm

Vg=1VVd=3V

100 µm40 µm0 µm

Fig. 6.3. Cascode device with gain boosting characteristic curve using different gate line lengths (Lg = 0 to 100 µm).

For power matching, load-pull simulations of different size devices are simulated at

the design frequency. The load-pull simulation of the cascode CMOS device (W = 64 µm) is

shown in Fig. 6.4. The constant output power contours (blue) from 7.4 to 9.41 dBm and the

constant PAE contours (red) from 1.9% to 14% are plotted with different output impedances.

The output power of 9.41 dBm with PAE of 14% of the designed amplifier can be achieved

with the output impedance of 12.27 + j29.03.

53

Pdel=9.41 dBm

Pdel=7.4 dBm

PAE = 1.9%

PAE = 14%

Vds=2.4 VVgs=1 VFreq=77 GHz

Z=12.27+j29.03PAE=14.01%Pin=0 dBmPout=9.41 dBm

Pdel=9.41 dBm

Pdel=7.4 dBm

PAE = 1.9%

PAE = 14%

Vds=2.4 VVgs=1 VFreq=77 GHz

Z=12.27+j29.03PAE=14.01%Pin=0 dBmPout=9.41 dBm

Fig. 6.4. Load-pull simulation of cascode device: L 90nm x W 64 µm.

The input and output impedance-matching networks are designed to maximize the

power gain delivered to the load with the coplanar waveguides (CPW) in Fig. 6.5. Short stub

LC impedance matching networks [33-34] are designed at the input and the output of the

cascode cells, and the output short stub impedance matching network simulation result is

shown for each matching step in Fig. 6.6.

Fig. 6.5. LC short stub matching network.

54

Z*out

LC short stub MN

LC main line MN

Short TL line

Zload

Zm

Output Matching Network

Z*out

LC short stub MN

LC main line MN

Short TL line

Zload

Zm

Output Matching Network Fig. 6.6. LC short stub output impedance matching network simulation.

A single-stage schematic diagram is shown in Fig. 6.7, and it is designed and

simulated in ADS with the momentum CPW model. The simulation result of the output

voltage waveform is shown in Fig. 6.8 (a) for the first stage and (b) for the second stage.

Different input and output nodes are defined in the schematic. The amplifier is simulated

with input power –25 dBm to 5 dBm and bias at Vd = 2.4V and Vg = 1V. The two-stage W-

band amplifier uses an nMOS device width of 64 µm, and its drain current is approximately

25 mA for each stage.

Fig. 6.7. Schematic diagram of a one-stage amplifier.

RFin RFout

Vinc

Vin

Vout1

Vout2

Voutc

55

Fig. 6.8. Simulation of (a) first stage amplifier and (b) second stage amplifier output waveforms at each node.

6.2.1 Experimental results

The amplifier is implemented with the UMC 90 nm (gate length) RF CMOS 9-metal-

layers process. The chip occupies an area of L 0.5 mm × W 0.7 mm, including RF and DC

pads, as shown by the superimposed schematic diagram in Fig. 6.9. The DC bias supplies are

connected through matching networks. High-frequency on-wafer SOLT calibration

measurements are carried out with a vector network analyzer 8510C, and measurement setup

is shown in Fig. 6.10. The drain voltage and top cascode nMOS gate are biased at 2.4 and 3

V, and the second gate is biased at 1 V. The measured total drain currents are 51 and 61 mA

for 2.4 and 3 V, respectively.

2 4 6 8 10 12 14 16 18 20 22 240 26

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-0.5

3.5

time, psec

ts(X

5.Vi

nc),

Vts

(X5.

Vin)

, Vts

(X5.

Vout

1), V

ts(X

5.Vo

ut2)

, Vts

(X5.

Vout

c), V

Second stage

2 4 6 8 10 12 14 16 18 20 22 240 26

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-0.5

3.5

time, psec

ts(X

5.Vi

nc),

Vts

(X5.

Vin)

, Vts

(X5.

Vout

1), V

ts(X

5.Vo

ut2)

, Vts

(X5.

Vout

c), V

Second stage

2 4 6 8 10 12 14 16 18 20 22 240 26

0.0

0.5

1.0

1.5

2.0

2.5

-0.5

3.0

time, psec

ts(X

3.Vi

nc),

Vts

(X3.

Vin)

, Vts

(X3.

Vout

1), V

ts(X

3.Vo

ut2)

, Vts

(X3.

Vout

c), V

First stage

2 4 6 8 10 12 14 16 18 20 22 240 26

0.0

0.5

1.0

1.5

2.0

2.5

-0.5

3.0

time, psec

ts(X

3.Vi

nc),

Vts

(X3.

Vin)

, Vts

(X3.

Vout

1), V

ts(X

3.Vo

ut2)

, Vts

(X3.

Vout

c), V

First stage

56

Fig. 6.10. W-band measurement setup with waveguide GSG probe and fabricated chip.

The power amplifier is designed for a W-band application, and the maximum gain

occurs at 80 GHz because of BSIM4 model variation and the custom CPW model from the

momentum simulation. The ICFD2 model and measured results of the S-parameter are

plotted in Fig. 6.11. The measured input and output matching networks are better than –10

dB. The amplifier achieved –3 dB bandwidth of 1.5 GHz, and the small-signal gain

maximum is 18 dB. The reverse isolation is better than –26 dB [35].

Fig. 6.9. Two-stage W-band amplifier schematics and fabricated chip.

57

-36-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

S pa

ram

eter

s (d

B)

S11

S21

S22

Vg= 1VVd= Measured 2.4V Vd= Measured 3VVd= ICF-D2 model 2.4V

-36-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

S pa

ram

eter

s (d

B)

S11

S21

S22



Fig. 6.11. S-parameters measurement results of a two-stage W-band amplifier.

For different process corners of slow (ss), fast (ff), and typical (tt), MOSFET devices

are measured for RF characteristics with maximum ft ~ 90 GHz, 100 GHz, and 110 GHz

respectively, while fmax ~ 125 GHz is approximately the same. As shown in Fig. 6.12, the

amplifier gains are > 16 dB. The slow-to-fast process corners alter the impedance matching

characteristics, shifting the peak gain frequency and increasing the bandwidth. The measured

maximum gain varies with applied gate bias voltages from 0.8 to 1.2 V and fixed drain bias

voltages of 2.4 V (red) and 3 V (blue) for three different amplifiers in Fig. 6.13. The small-

signal gain increases from 14.5 to 17.5 dB, and from 16 to 18.8 dB for drain source voltages

2.4 and 3 V, respectively, in Fig. 6.13.

58

-36-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

Gai

n (d

B)

Vg=1VVd=2.4V

ttffss

-36-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

Gai

n (d

B)

Vg=1VVd=2.4V

ttffss

Vg=1VVd=2.4V

ttffss

Fig. 6.12. Small-signal gain comparison of a two-stage W-band amplifier with three different

process corner devices: typical (tt), fast (ff), and slow (ss).

14

15

16

17

18

19

0.8 0.9 1 1.1 1.2Vg (V)

Gai

n (d

B)

Freq=80GHzVg=1VVd=3VVd=2.4V

A1A2A3

14

15

16

17

18

19

0.8 0.9 1 1.1 1.2Vg (V)

Gai

n (d

B)

Freq=80GHzVg=1VVd=3VVd=2.4V

A1A2A3

A1A2A3

Fig. 6.13. Maximum gain measurement with different applied voltages. Comparison of three

different amplifier circuits with same process corner (tt).

A single-tone large-signal power measurement is carried out with an 8510C source.

Output power is measured with an external harmonic mixer, W-band attenuator, and 8565E

power spectrum analyzer. High-frequency on-wafer SOLT and one-port power calibration

59

are performed in Fig. 6.14. A single-tone power measurement of the two-stage CMOS

amplifier plot is shown in Fig. 6.15. The measured amplifier at 80 GHz has demonstrated

gain, Ga > 18 dB, output power at 1 dB compression, P1dB =10.8 dBm, saturated power, Psat =

13.3 dBm, and PAE = 11.8% with amplifier biased at Vd = 3 V and Vg =1 V. The gain

peaking is due to the common gate inductance gain boosting as shown in Fig. 6.15.

Fig. 6.14. A W-band amplifier single tone power measurement at 80 GHz.

-5

0

5

10

15

20

25

-22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0Pin (dBm)

Gai

n (d

B) &

Pou

t (dB

m)

0

2

4

6

8

10

12

14

16

PAE

(%)

PoutGainPAE

Vg=1VVd=3Vfreq=80GHz

-5

0

5

10

15

20

25

-22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0Pin (dBm)

Gai

n (d

B) &

Pou

t (dB

m)

0

2

4

6

8

10

12

14

16

PAE

(%)

PoutGainPAE


Fig. 6.15. A W-band amplifier single-tone power measurement at 80 GHz.

The measured performance of our W-band amplifier compared well with other state-

of-the-art published results, as summarized in Table 6.1. The compact two-stage on-chip fully

Amp

Spectrum Analyzer

Harmonics MixerCPW CPW Att

0 dB10dB

8510C

Amp

Spectrum Analyzer

Harmonics Mixer

Spectrum Analyzer

Harmonics MixerCPW CPW Att

0 dB10dB

Att0 dB10dB

8510C

60

integrated W-band amplifier demonstrates high power gain (> 18 dB) with smaller chip area.

This W-band power amplifier also achieves the highest linear and saturated power with the

highest PAE at 80 GHz.

We reported a compact area for the cascode of the CMOS power amplifier, using

inductance gain boosting, and short stub matching to match load-pull and source-pull

impedances simultaneously: the amplifier circuit is demonstrated with a low-loss LC short

stub on-chip CPW matching network. The measured compact two-stage power amplifiers

demonstrated SOA results of minimum area of 0.35 mm2, Ga = 18.8 dB, and Psat > 13 dBm

with PAE > 11.8%. Also, we showed that the variation in different process corner devices

altered the maximum gain, bandwidth, and matching frequency.

TABLE 6.1Performance summary and comparison of W-Band CMOS PA

Tech. CMOS

Stages freq (GHz

)

Vdd (V)

Id (mA)

Gain (dB)

BW (GHz)

P1dB (dBm)

Psat (dBm)

Pdc (mW)

PAE (%)

Size(mm2)

[24] 90 nm 4-stage common source

77 1.2 118.5 8.5 ~ 5 4.7 6.3 142 - 0.98

[25] 90 nm 5-stage common source

80 1 176 12.2 ~25 7.5 10.3 176 4.5 0.56

2.4 75 15 20 7 10 180 5 [26] 90 nm 3-stage cascode Balanced PA

94 3 123 17 17 8 12 370 4.8

0.4

0.7 76 17.4 ~ 3 0.9 5.8 53 7.1 [27] 90 nm 3-stage common source

77 1 92 20.6 ~ 2 5 9.4 92 9.6

0.53

68-80 2.4 - 17.6 12 > 7 > 10.8 - - [28] 90 nm 3-stage cascode Broadside Coupler 68-83 3 - 18 15 > 8.3 > 11.8 - -

0.656

2.4 51 17 1.5 8.65 12.3 122 13.8 This work

90 nm 2-stage cascode 80 3 60 18 1.5 10.8 13.3 180 11.8

0.35

61

6.3 Wilkinson Power Amplifier

The W-band (75 to 110 GHz) power amplifier (PA) is a challenge in CMOS

technology because of the low breakdown voltage and high losses in silicon at millimeter

wavelengths. In 2008, a cascode-balanced CMOS PA demonstrated high performance at 94

GHz with 17 dB gain, P1dB = 8 dBm, and Psat = 12 dBm with PAE = 4.8% [26]. However,

most of the W-band PA output power level is limited to P1dB < 14 dBm [31]. Hence, the

monolithic power-combining techniques of PAs are attractive for delivering P1dB > 20 dBm

due to the size reduction of the combiner operated at the W-band. In 2009, a balanced and

wideband matching approach to a cascode CMOS PA covering 68 to 83 GHz reported

outstanding power performance at Psat = 12 dBm and P1dB = 9 dBm at 80 GHz [28]. The The

Wilkinson power combiner is another attractive technique; it was used in a V-band power

amplifier at 60 GHz to achieve outstanding P1dB = 18.2 dBm and Psat = 20 dBm [36]. A W-

band monolithic coplanar waveguide (CPW) Wilkinson power combiner with two CMOS

power amplifiers in 90 nm CMOS technology is discussed in the following section. The 77 to

83 GHz CMOS PA achieved 17 dB small-signal gain, BW3dB of 4.5 GHz (from 78 to 82.5

GHz), 10.6 dBm linear output power, 12.3 dBm saturated power, and 3.9% PAE at 80 GHz.

6.3.1 Passive device CPW models

Passive CPWs of different sizes are designed to reduce parasitic capacitance and

resistance using ADS momentum simulation. The CPW line can be characterized by

characteristic impedance Z0 and phase velocity vp.

CvCLZ eff

po

ε10 == , where

opv

εμ00

1= (6.6)

62

From momentum S-parameter simulation, the effective dielectric constants εeff and Z0 are

calculated and the results are 77.30

==CC

effε andeff

cLengthελ4

= (6.7)

The CPW transmission lines are designed for a 50 Ω load with 10 µm width, 5 µm gap, and 3

µm thickness in the metal 9 layer of the UMC 90 nm RF CMOS 9-metal-layer process. The

measured loss in passive CPW lines is less than –0.5 dB for a 150 µm line length in Fig. 6.16

(b) and less than –1 dB for a 400 µm line length.

A Wilkinson power combiner and divider can be used for a power-combining device.

It was designed with a 70.71 Ω quarter-wavelength CPW transmission line to minimize loss

and a 100 Ω resistor to match the 50 Ω CPW line. The 70.71 Ω CPW was designed with the

ADS momentum simulation with the signal line width of 14 µm, and the gap between signal

and ground plane at 14 µm. The power divider [33-34] of RF input port 1 and output ports 2

and 3 can be measured from the S-parameters from Eqs. (6.8) to (7.0).

01111 == +− PSP (6.8)

CPW

L = 150 µm -5

-4.5-4

-3.5-3

-2.5-2

-1.5-1

-0.50

75 80 85 90 95 100 105 110freq (GHz)

S-pa

ram

eter

(dB

)

-30-28-26-24-22-20-18-16-14-12-10

S12S21

S11S22

-5-4.5

-4-3.5

-3-2.5

-2-1.5

-1-0.5

0

75 80 85 90 95 100 105 110freq (GHz)

S-pa

ram

eter

(dB

)

-30-28-26-24-22-20-18-16-14-12-10

S12S21

S11S22

(a) (b)

Fig. 6.16. (a) CPW test structure. (b) Measured CPW transmission line 150 µm measurement.

63

21

12

212

++− ==

PPSP (6.9)

21

12

313

++− ==

PPSP (6.10)

The test structure of port 1 to port 2 with port 3 is terminated with 50 Ω, as shown in Fig.

6.17 (a). The measured Wilkinson power combiner loss S21 is approximately –3.25 dB (1/2

of –6.5 dB for measured S21) in Fig. 6.17 (b). The input and output of the combiner are

matched to 50 Ω with S22 = –10 dB in Fig. 6.17 (b). The total power loss in the combiner

and divider is 6.5 dB from the measured results. Future improvement of the loss toward –3

dB may be realized.

Fig. 6.17. (a) Wilkinson power combiner/divider test structure. (b) S-parameters momentum model simulation and measured results comparison.

6.3.2 Circuit design and experimental results

In the W-band power amplifier circuit design, the cascode connection consists of a

common-source stage driving a common-gate stage. The power gain of the cascode circuit is

approximately twice that of the common-source amplifier. Cascode circuits have a small

reverse transmission and good isolation, which are desired properties in high-frequency

oZoZ

oZoZ2

4/λ

oZ2

-20-18-16-14-12-10

-8-6-4-20

75 80 85 90 95 100Freq (GHz)

S12

& S

22 (d

B)

S12 measuredS22 measuredS12 modelS22 model

(a) (b)

64

amplifier circuits. Another characteristic of the cascode cell is its high output resistance,

which can reduce the conversion power loss to the output matching network. The Wilkinson

power amplifier in Fig. 6.18 is designed with the driver cascode gain stage, and then two

cascade power stages are designed with the Wilkinson power-combining technique to

increase linear power [7].

oZ

oZoZ2

4/λ

oZ2

01111 == +− PSP

21

12

212

++− ==

PPSP

21

12

313

++− ==

PPSP

oZ

Fig. 6.18. Schematics of Wilkinson power combiner with two W-band, two-stage CMOS power amplifiers.

A Class A power amplifier design is chosen for stable input with high gain and a

gain-boosting technique with short transmission line at a common-gate transistor. Also, a

source degeneration CPW line is designed between the common-source and common-gate

transistor stages in Fig. 6.18. The optimum device width of 2 µm with 32 fingers is chosen in

the 90 nm CMOS device. The short stub LC matching networks are designed at the input and

output of the cascode device. The DC bias supplies are connected through the impedance-

matching networks. The cascoded and cascaded amplifiers use a 64 µm width nMOS, and the

drain current is approximately 25 mA for each stage.

The Wilkinson amplifier has been implemented/fabricated with 90 nm gate lengths in

the UMC 90 nm RF CMOS 9-metal-layer process. The chip occupies an area of 1.3 mm ×

65

0.95 mm, including RF and DC pads, as shown by the superimposed block diagram in Fig.

6.19. High-frequency on-wafer SOLT calibration measurements were carried out with a

vector network analyzer 8510C.

oZ

oZ

oZoZ2

4/λ

oZ2

01111 == +− PSP

21

12

212

++− ==

PPSP

21

12

313

++− ==

PPSP

Fig. 6.19. Fabricated W-band CPW Wilkinson power amplifier and its associated block

diagram.

The drain voltage and top cascode NMOS gates are biased at 2.4 and 3 V, and the

second gate is biased at 1 V. The measured total drain currents are 130 and 150 mA for 2.4

and 3 V, respectively. The power amplifier is designed for a W-band application, and the

maximum gain occurs at 80 GHz. The measured results of the S-parameters are plotted in

Fig. 6.20. The measured input and output matching networks are better than –10 dB. The

power amplifier has measured bandwidth (at –3dB) of 4.5 GHz (78 to 82.5 GHz), and the

maximum small-signal gain is 17.8 dB. The measured gain varies with applied gate bias

voltages from 0.8 to 1.2 V and drain bias voltage 2.4 V (red) and 3 V (blue) for three

66

different amplifiers with the same typical (tt) device in Fig. 6.21. The small-signal gain

increases from 13.8 dB to maximum 17.8 dB at 80 GHz [37].

-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

S pa

ram

eter

s (d

B)

S11

S21

S22

Vg= 1VVd= Measured 2.4V Vd= Measured 3VVd= ICF-D2 model 2.4V -32

-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

S pa

ram

eter

s (d

B)

S11

S21

S22



Fig. 6.20. S-parameters measurement and ICF-D2 model of Wilkinson power amplifier

comparison.

13

14

15

16

17

18

0.8 0.9 1 1.1 1.2Vg (V)

Gai

n (d

B)

A1A2A3

Freq=80 GHz

Vd=3VVd=2.4V

13

14

15

16

17

18

0.8 0.9 1 1.1 1.2Vg (V)

Gai

n (d

B)

A1A2A3

A1A2A3

Freq=80 GHz

Vd=3VVd=2.4V

Fig. 6.21. A Wilkinson PA maximum gain measurement with different applied gate and drain voltages for three different PA circuits.

RF characteristics are measured for different process corners—slow (ss), fast (ff), and

typical (tt)—MOSFET devices as in Fig. 6.22. Maximum ft values are 90 GHz, 100 GHz,

67

and 110 GHz for slow, typical, and fast devices, and fmax = 120 GHz. The Wilkinson

amplifier maximum gain is 18 dB, as shown in Fig. 6.22. The slow-to-fast process corners

alter the matching network characteristics, altering the peak gain frequency as well as

increasing the bandwidth. For the slow device PA (green), the center frequency is around 80

GHz and bandwidth increases from 78 to 81 GHz. For the typical device PA (red), the center

frequency is around 80.5 GHz with a bandwidth increase from 78 to 82.5 GHz. For the fast

device PA (blue), the center frequency is around 82 GHz and bandwidth increases from 79 to

85 GHz.

-32-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

Gai

n (d

B)

Vg=1VVd=2.4V

Measured ttMeasured ffMeasured ssICF-D2 model-32

-28-24-20-16-12

-8-4048

121620

75 77 79 81 83 85 87 89 91Freq (GHz)

Gai

n (d

B)

Vg=1VVd=2.4V

Measured ttMeasured ffMeasured ssICF-D2 model

Vg=1VVd=2.4V

Measured ttMeasured ffMeasured ssICF-D2 model

Fig. 6.22. S-parameter measurement results of the slow (ss), typical (tt), and fast (ff)

Wilkinson power amplifiers.

A single-tone power measurement was set up with an 8510C vector network analyzer,

a harmonic mixer, a W-band wave guide attenuator, and an 8565 power spectrum analyzer.

One-port power calibration was performed and removed all losses. A single-tone power

measurement with a 3 V voltage supply is shown in Fig. 6.23. The measured output power

68

gain is approximately 20 dB, saturated power is 12.3 dBm, and PAE is approximately 3.9%

for 3 V supplies. The measured performance of the CPW Wilkinson PA is summarized in

Table 6.2 with other published results. Using Wilkinson power-combining techniques, the PA

has higher linear output power (9.6 dBm and 10.6 dBm) and compared well with published

W-band amplifiers. Further improvement in CPW combiner loss, the output stage layout, and

the matching network can improve output power toward the desirable level of 20 dBm.

-5

0

5

10

15

20

25

-22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0Pin (dBm)

Gai

n (d

B) &

Pou

t (dB

m)

0

1

2

3

4

5

PAE

(%)

Pout GainPAE


-5

0

5

10

15

20

25

-22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0Pin (dBm)

Gai

n (d

B) &

Pou

t (dB

m)

0

1

2

3

4

5

PAE

(%)

Pout GainPAE


Fig. 6.23. A Wilkinson amplifier single-tone power measurement at 80 GHz.

69

In this work, a parasitic device modeling ICF-D2 was developed to accurately predict

RF behavior at a high-frequency amplifier design. A Wilkinson power-combining amplifier

used a cascode device topology in a 90 nm nMOS and was designed with gain boosting, short

stub matching to the power match load, and source impedances simultaneously using on-chip

CPW. Also, variation in different process corner devices altered the maximum gain,

bandwidth, and matching frequency. For the MMW power amplifier application, the CPW

Wilkinson power divider and combiner techniques to increase the power gain to 20 dB, the

linear output power to 10.6 dBm, and saturated power to 12.3 dBm were demonstrated in

CMOS technology.

TABLE 6.2Performance summary and comparison of CMOS power amplifier

Tech. CMOS

Stages freq (GHz

)

Vdd (V)

Id (mA)

Gain (dB)

BW (GHz)

P1dB (dBm)

Psat (dBm)

Pdc (mW)

PAE (%)

Size (mm2)

2.4 75 15 20 7 10 180 5 [24] 90 nm 3-stage cascode Balanced PA

94 3 123 17 17 8 12 370 4.8

0.4

68-80 2.4 76 17.6 12 > 7 > 10.8 ~184 6.5 [26] 90 nm 3-stage cascode Broadside Coupler 68-83 3 84 18 15 > 8.3 > 11.8 ~252 6

0.656

1.8 159 26.1 16 10.5 14.5 286 10.2 [27] 90 nm 3-stage cascode 4 DAT combiner

55-713 ~ 172 26 - 14.5 18 ~ 517 12.2

0.64

[31] 90 nm 4 way Wilkinson PA

60 1.2 ~ 568 20 ~ 5 18.2 19.9 ~ 682 14.2 1.75

2.4 130 16 4.5 9.6 11.8 312 4.8 This work

90 nm 3-stage cascode Wilkinson PA

77-833 150 17 4.5 10.6 12.3 450 3.9

1.23

70

7 CONCLUSIONS

The impact of external parasitic distributed effects on the performance of a CMOS power

transistor has been discussed with the extrinsic scalable and non-scalable parasitic extraction

methods. It has been shown that including distributed effects is important for predicting the

correct ft, fmax, transducer power gain, and output power. The proposed distributed ICF-D1

model is validated by comparing the DC, S-parameters, and one-tone measurements of the

scaled CMOS power devices. The scalable distributed ICF-D2 modeling method is extended

to the power CMOS devices for millimeter wave application. The power devices are

measured for S-parameters from 1 to 50 GHz, V-band (50 to 75 GHz), and W-band (75 to

110 GHz) with the vector network analyzer. The resulting S-parameters are created for

distributed two-port models of the power devices and transmission lines. Distributed model

parameters are measured and extracted in physical layout-based intrinsic and extrinsic

parameters from 1 to 110 GHz.

For the model verification, we compared the lumped and distributed models with the

experimental results of MMIC power amplifiers in S-band and W-band applications. The

lumped parasitic (RC) incorporation of the large width nMOS is demonstrated and excellent

agreement is achieved with the measured results. The design and measured results of a

single-end PA for 2.5 GHz WiMAX applications based on load- and source-pull analysis to

match load and source impedances simultaneously are demonstrated with a low-loss on-chip

LC matching network. We proposed a Wilkinson power-combining technique; the single-

end PA can be used in power amplifier applications, and the projected PA can achieve output

power >24 dBm at 1 dB gain compression point.

A parasitic device modelling, ICF-D2, is developed to accurately predicte RF

behavior at millimeter wave amplifier designs. We reported a compact area of a cascode cell

71

with the two-stage cascode CMOS power amplifier, using the inductance gain boosting, and

short stub matching to match load- and source-pull impedances simultaneously. The

amplifier circuit is demonstrated with a low-loss LC short stub on-chip CPW matching

network. The measured compact two-stage power amplifiers were demonstrated excellent

results with a minimum area of 0.35 mm2. For the MMW power amplifier application, the

Wilkinson MMW amplifier used a cascode device topology in a 90 nm nMOS, and was

designed with two (two-stage) amplifiers and a driver amplifier with CPW Wilkinson power

divider/combiner techniques. The Wilkinson linear power gain is increased compared to the

two-stage power amplifier. Due to higher loss from silicon and inter-stage and output stage

saturation, Wilkinson saturated output power is lower than the two-stage amplifier. Also,

variation in different process corner devices altered the maximum gain, bandwidth, and

matching frequency in both W-band power amplifiers.

Our preliminary work shows that CMOS power amplifier technologies have great

potential for system-on-chip integration with low cost and minimum area. Further

development of low-loss power-combining techniques can improve the output power of >

100 mW, gain > 20 dB, wide bandwidth and PAE > 10% Wilkinson MMWICs. Further

research in MMW amplifiers can be explored in 65 and 45 nm technology nodes.

72

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[34] D. M. Pozar, Microwave Engineering, 2nd ed. New York, NY: John Wiley & Sons, 1998.

[35] D. Chan and M. Feng, “A compact W-Band CMOS power amplifier with gain boosting and short stub matching for high power and high efficiency operation,” Microwave Wireless and Component Letters, submitted for publication.

[36] C. Y. Law and A. V. Pham, “A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOS,” in IEEE Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010, pp. 426-427.

[37] D. Chan and M. Feng, “W-band monolithic CPW Wilkinson CMOS power amplifier,” in IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, January 2011, submitted for publication.

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AUTHOR’S BIOGRAPHY

Doris A. Chan was born in Mawlamyine, Myanmar (formally known as Burma). She

started her undergraduate studies at Western Illinois University in 1997 and transferred to the

University of Illinois at Urbana-Champaign in 1999. She received the B.S. and M.S. degrees

in electrical engineering from the University of Illinois at Urbana-Champaign in 2001 and

2003, respectively. Her master’s thesis focused on the design of a differential voltage-

controlled oscillator for 2.4 GHz and 5.2 GHz WLAN applications.

She was with Xindium Technologies, Inc. from 2002 to 2004, where she joined in the

test development of InP (SHBTs) PIN diodes and transimpedance amplifiers (TIAs), and

double heterojunction bipolar transistor (DHBTs) power amplifier devices. She also

fabricated InP DHBTs devices for power amplifier applications. From 2004 to 2008, she was

with Trace Photonics, Inc., where she was involved in the development of Radio Isotope

Micro Source (RIMS) power conversion, and designed solar cell controlled circuits for

military GSM transmitters.

Her Ph.D. dissertation developed a characterization and modeling of RFCMOS power

devices, and designed MMIC power amplifiers for WiMAX and W-band applications. Her

research work on parasitics distributed power device modeling with a MMIC power amplifier

achieved state-of-the-art results of output saturated power at 13.3 dBm with PAE 11.8% with

a minimum area of 0.35 mm2. She received her Ph.D. in electrical engineering in 2010 in the

area of radio frequency integrated circuit design. She is a recipient of a DOE Energy

Research Undergraduate fellowship and a Yunni Pao’s fellowship. She is the author or

coauthor of seven journal and conference proceeding publications.

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