CMOS Logic Design Using Cadence Virtuoso
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CMOS Logic Design using Cadence Virtuoso Presentation by SANDEEP MISHRA PhD Scholar P14EC001 Dept. of ECE NIT Meghalaya Under the Esteemed Guidance of Dr. Anup Dandapat
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Cadence Virtuoso is a tool used for designing full-custom integrated circuits. Processes like Schematic Entry, Behavioural Modelling (Verilog-AMS), Circuit Simulation, Custom Layout, Physical Verification, Extraction can be done using it.
Transcript of CMOS Logic Design Using Cadence Virtuoso
CMOS Logic Design using
Cadence Virtuoso
Presentation by
SANDEEP MISHRAPhD ScholarP14EC001
Dept. of ECENIT Meghalaya
Under the Esteemed Guidance ofDr. Anup Dandapat
INTRODUCTION
DESIGN LIBRARY & SCHEMATIC DESIGN
DESIGN ENVIRONMENT
VISUALIZATION and ANALYSIS
SYMBOL CREATION
CIRCUIT DESIGN USING SYMBOL
LAYOUT DESIGN
CONTENTS
DESIGN RULE CHECKING (DRC)
LVS and RCX
TESTING LAYOUT
CONCLUSION
CADENCE VIRTUOSO
Cadence Virtuoso is a tool used for designing full-custom integrated circuits.
Schematic Entry
Behavioral Modeling (Verilog-AMS)
Circuit Simulation
Custom Layout
Physical Verification
Extraction
Some Important Sub-tools present in Cadence Virtuoso are
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Virtuoso Layout Suite
Virtuoso Visualization and Analysis
INTRODUCTION
DESIGN LIBRARY
A library contains all the design files (Schematic, Symbol, Layout, Configuration etc.) related to a circuit or to a technology. Users can create their own complete library or can attach their custom library to an existing technology library.
DESIGN LIBRARY & SCHEMATIC DESIGN
For the user defined library a cell view is created for schematic design and is opened with the Schematic Editor.Some Shortcuts used for the Design are
DESIGN LIBRARY & SCHEMATIC DESIGN
KEY FUNCTION
i Add Instance
q Edit Instance
u Undo
U Redo
w Add wire
Shift Z Zoom out
Ctrl Z Zoom in
[ ] Zoom in and Zoom Out
r Rotate
Esc No Selection
c Copy
p Add Pin
f Fit to Screen
m Move
l Label Wire
Arrow Keys Move Around Window
ADDING INSTANCE
DESIGN LIBRARY & SCHEMATIC DESIGN
ADDING INSTANCE & PIN
DESIGN LIBRARY & SCHEMATIC DESIGN
INVERTER SCHEMATIC
DESIGN LIBRARY & SCHEMATIC DESIGN
Analog Design Environment
It sets the standard in fast and accurate design verification.It has a variety of built-in analog analysis tools.
Steps:
Set the Model Libraries (180/90/45)
Choose the Analyses (Transient, DC, AC)
Select the Design Variables (Transistor Parameters)
Select the outputs to be plotted (INPUTS/OUTPUTS/SUPPLIES)
Select the outputs to be saved (Save All)
Save the current state for further use
Run Simulation
DESIGN ENVIRONMENT
DESIGN ENVIRONMENT
VISUALIZATION and ANALYSIS
Calculation of Delay, Power and Current
VISUALIZATION and ANALYSIS
VISUALIZATION and ANALYSIS
S.NO. PARAMETER VALUE
1 Avg. Power 60 uW
2 Avg. nm0 Power 56.69 uW
3 Avg. pm0 Power 3.055 pW
5 Supply Current (20 nS) 50 nA
6 Supply Current (25 ns) 50 nA
7 Supply Current (39.95 ns) 50 nA
8 Supply Current (39.96 ns) 15 uA
9 Supply Current (39.97 ns) 70 uA
10 Supply Current (39.98 ns) 110 uA
11 Supply Current (39.99 ns) 140 uA
12 Supply Current (40 ns) 190 nA
SYMBOL CREATION Symbol of a Design is created for
Using it as an Instance Designing the Layout of it
SYMBOL CREATION
SYMBOL CREATION
CIRCUIT DESIGN USING SYMBOL
CIRCUIT DESIGN USING SYMBOLHALF ADDER USING NAND ONLY
CIRCUIT DESIGN USING SYMBOL
HALF ADDER USING NAND ONLY TRANSIENT RESPONSE
LAYOUT DESIGNSome key Parameters in the Layout Design:
Must follow a technology rule
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top (Design Becomes Simpler)
All gates should include well and substrate contacts
VDD and GND should about Standard Height
Same layer types cannot overlap with each other
Different layers types must be connected through Via
Schematic and Layout Must Match
Steps:
Open the Cellview for which the layout to be designed
In Connectivity Generate all from sources
Set the Height and Width of all the Pins given at the symbol level
Create the basic layout containing MOS and Pins
Connect all the layers as per Schematic
In must overlapping case use different kinds of metal (Metal2 or Metal3) using Via.
In the Assura tab Set the technology (180/90/45) and Run DRC (Design Rule Check)
Resolve all the errors present in the DRC Run by editing the Layout and Rerun DRC.
If No error is present then Run LVS (Layout Versus Schematic)
Then run RCX (Assura Parasitic Extraction) for extracting parasitic elements from the
physical design
LAYOUT DESIGN
LAYOUT DESIGN
KEY FUNCTION
m Move
f Fit to Screen
u Undo
U Redo
l Create Label
s Stretch
c Copy
q Properties
k Create Ruler
K Delete Ruler
o Create Contact
Space Create Via
LAYOUT OF NAND GATELAYOUT DESIGN
LAYOUT DESIGNLAYOUT OF NAND GATE
LAYOUT DESIGN
DESIGN RULE CHECKING (DRC)
LVS and RCX
LVS and RCX
LVS and RCX
TESTING LAYOUT Steps:
From Library Create a configurationSet the template nameSet Instance ViewWhile opening the Configuration, Schematic Editor appears and all the setting further are similar to that of Schematic testing.
TESTING LAYOUT
TESTING LAYOUT
LAYOUT DESIGN USING MULTIPLE SYMBOLS
LAYOUT DESIGN USING MULTIPLE SYMBOLS
CONCLUSION Cadence Virtuoso is an Effective EDA tool designed with Virtually Real
Parameter values, true analysis algorithms and All kinds of Analysis.
Supports all levels of IC Design with Customization.
Design is Complex than Open Source Tools but meets the real requirements.
Every kinds of Analysis of the output response are present but Interpretation
with the Sub parametric values needs lots of knowledge.
Rule Checking is optimized but the area of design need to be optimized in the
user level.
Tool requires additional libraries and sample components should have the
option of editing.
