CMOS Inverter - upload.wikimedia.org · 4/6/2016 · Inverter (2B) 4 Young Won Lim 4/6/16...
Transcript of CMOS Inverter - upload.wikimedia.org · 4/6/2016 · Inverter (2B) 4 Young Won Lim 4/6/16...
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Young Won Lim4/6/16
CMOS Inverter
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Young Won Lim4/6/16
Copyright (c) 2011-2016 Young W. Lim.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
Please send corrections (or suggestions) to [email protected].
This document was produced by using OpenOffice and Octave.
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Inverter (2B) 3 Young Won Lim4/6/16
Operation Modes
VDSn
IDSn
nLIN
nOFF
nSAT nLIN
nSAT
nOFF
I ds ∝ V ds
I ds = const
I ds = 0
G
S
D
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Inverter (2B) 4 Young Won Lim4/6/16
Operation Modes and Bias Voltages
nLIN
nSAT nOFF
I ds ∝ V ds
I ds = c
I ds = 0
V dsV gs
V dsV gs
V dsV gs
V dsV gs
nOFF
I ds = 0
G
S
D
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Inverter (2B) 5 Young Won Lim4/6/16
nMOS Bias https://en.wikipedia.org/wiki/CMOS
nLINnOFF
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Inverter (2B) 6 Young Won Lim4/6/16
pMOS Bias
N N
N Np p
pp
https://en.wikipedia.org/wiki/CMOS
pLINpOFF
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Inverter (2B) 7 Young Won Lim4/6/16
Pinch-Of
+ +
––+–
+
––
––-
++
++
More reverse biasedMore reverse biased
Most of Vds
https://en.wikipedia.org/wiki/CMOS
nSAT
Most of Vds
nSAT
Constant flowing capacity
To prevent forward biased junction
nLIN
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Inverter (2B) 8 Young Won Lim4/6/16
Notation
IDSp
IDSn
VDSp
–
+
VDSn
+
–
Current Notation
Voltage Notation
S
S
DD
G
G
S
S
DD
G
G
S
S
DD
G
G
https://en.wikipedia.org/wiki/CMOS
V i n = V GSp + V dd = V GSn
V out = V DSp + V dd = V DSn
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Inverter (2B) 9 Young Won Lim4/6/16
Input Voltage
IDSn VDSn
+
–
VDSp
+
–
Vin=
Vin=
IDSp
V GSn = V Gn − V Sn
V SGp = V Sp − V Gp
+
– VGSn= V in − V ss
= V dd − V i n
S
S
DD
G
G
S
S
DD
G
G
–
+VGSp
V GSp = V Gp − V Sp
= V in − V dd
V i n = V GSp + V dd
= V GSn
https://en.wikipedia.org/wiki/CMOS
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Inverter (2B) 10 Young Won Lim4/6/16
Output Voltage
VDSp
–
+
VDSn
+
–
VQ VQ
V Q = V DSp+ V Sp
= V DSp + V dd
V Q = V DSn+ V S
= V DSn + V ss
S
S
DD
G
G
S
S
DD
G
G
S
S
DD
G
G
= V DSn
V out = V DSp + V dd = V DSn
https://en.wikipedia.org/wiki/CMOS
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Inverter (2B) 11 Young Won Lim4/6/16
Characteristic Curves
VDSn
IDSn
VDSp
IDSp
IDSn VDSn
+
–
Vin=
+
– VGSn
S
S
DD
G
G
VDSp
+
–
Vin=
IDSp
S
S
DD
G
G
–
+VGSp
https://en.wikipedia.org/wiki/CMOS
negative
negative
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Inverter (2B) 12 Young Won Lim4/6/16
Flip up pMOS curves
VDSn
IDSn
VDSp
– IDSp
IDSn VDSn
+
–
Vin=
+
– VGSn
S
S
DD
G
G
VDSp
+
–
Vin=
S
S
DD
G
G
–
+VGSp
– IDSp
https://en.wikipedia.org/wiki/CMOS
(-1) * IDSp
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Inverter (2B) 13 Young Won Lim4/6/16
Shift right pMOS curves
VDSn
IDSn
VDSp + Vdd
-IDSp
VDSn
+
–
Vin=
+
– VGSn
S
S
DD
G
G
VDSp
+
–
Vin=
S
S
DD
G
G
–
+VGSp
V Q = V DSp + V dd
V Q = V DSn
https://en.wikipedia.org/wiki/CMOS
VDSp + Vdd
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Inverter (2B) 14 Young Won Lim4/6/16
Overlay pMOS & nMOS curves
VDSn
IDSn
VDSp + Vdd
IDSn VDSn
+
–
Vin=
+
– VGSn
S
S
DD
G
G
VDSp
+
–
Vin=
- IDSp
S
S
DD
G
G
–
+VGSp
V i n = V GSp + V dd = V GSn
V out = V DSp + V dd = V DSn
-IDSp
https://en.wikipedia.org/wiki/CMOS
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Inverter (2B) 15 Young Won Lim4/6/16
[Ids–Vgs], [Ids–Vds] Characteristic Curves
IDSn
VDSn
VDSp + Vdd
-IDSp
IDSn
V GSn = 1
V GSn = 2
V GSn = 3
V GSn = 4
V GSn = 5
1 2 3 4 5 VGSn
-IDSp
1 2 3 4 5 V GSp + V dd
V GSp = −1
V GSp = −2
V GSp = −3
V GSp = −4
V GSp = −5
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Inverter (2B) 16 Young Won Lim4/6/16
Vin : L → H
V i n = V GSp + V dd = V GSn
V out = V DSp + V dd = V DSn0 1 2 3
-5 -4 -3 -2
0 1 2 3
4 5
-1 0
4 5V i n
V GSp
V GSn
V dd
V ssV i n
V GSp V GSnV
in=
+
– VGSn
S
S
DD
G
G
–
+VGSp
VDSp
–
+
VDSn
+
–
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Inverter (2B) 17 Young Won Lim4/6/16
Intersect Points
IDSnIDSn IDSn
IDSnIDSn IDSn
V i n =+0V GSp =−5V GSn =+0
V i n =+1V GSp =−4V GSn =+1
V i n =+2V GSp =−3V GSn =+2
V i n =+3V GSp =−2V GSn =+3
V i n =+4V GSp =−1V GSn =+4
V i n =+5V GSp =−0V GSn =+5
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Inverter (2B) 18 Young Won Lim4/6/16
Intersect Points in [Ids–Vgs], [Ids–Vds] Curves
VDSn
IDSn
VDSp + Vdd
-IDSp
0
-1-2-3
-4
-5
0
123
4
5
VGSnIDSn
V GSn
-IDSp
VGSp + V dd
0
-1-2-3
-4
-5
0
123
4
5
VGSp
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Inverter (2B) 19 Young Won Lim4/6/16
Mode Changes
0 1 2 3
-5 -4 -3 -2
0 1 2 3
4 5
-1 0
4 5V i n
V GSp
V GSn
pLIN
nSAT
pLINnSATpLIN
nLINpSAT pSAT pOFF
nLIN nLIN
IDSn
1 2 3 4 5 VGSn
V GSp+V ddnOFF
pLIN
nSAT
pLINnSATpLIN
nLINpSAT pSAT pOFF
nLIN nLINnOFF
VDSn
IDSn
-IDSp
0
123
4
5
VGSnIDSn
VDSp + Vdd
-IDSp
0
-1-2-3
-4
-5
VGSp
pOFF pSAT pSAT pLIN pLIN pLIN nLIN nLIN nLIN nSAT nSAT nOFF
IDSn
-IDSp
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Inverter (2B) 20 Young Won Lim4/6/16
Resistance and Mode Changes
nSAT nSAT nLIN nLIN nLINnOFF
pLIN pLIN pLIN pSAT pSAT pOFF
VDSn
IDSn
VDSp + Vdd
-IDSp
0
-1-2-3
-4
-5
0
123
4
5
VGSnVGSp
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Inverter (2B) 21 Young Won Lim4/6/16
Abruptly Changing Region
nSAT nSAT nSAT nLIN nLINnOFF
pLIN pLIN pSAT pSAT pSAT pOFF
pLINnOFF
pSATnSAT
pOFFnLIN
VIL
VIH
VOL
VOH
VDSn
IDSn
-IDSp
0
-1-2-3
-4
-5
0
123
4
5
VGSnVGSp
IDSn
V GSn
-IDSp
VGSp + V dd
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Inverter (2B) 22 Young Won Lim4/6/16
Input Switching 1 → 0
time
vin
vin
vout
nOFF
vout
nSAT
nLIN
time
H H
L L
Decreasinginput voltage
Increasing output voltage
Increasing output voltage
Decreasing input voltage
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Inverter (2B) 23 Young Won Lim4/6/16
Input Switching 0 → 1
time
vin
vin
vout
nOFF
vout
nSAT
nLIN
time
HH
LL
Increasinginput voltage
Decreasing output voltage
Decreasing output voltage
Increasing input voltage
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Inverter (2B) 24 Young Won Lim4/6/16
[VIL, VIH] & [VOL, VOH]
can be considered as a logic “L” input
can be considered as a logic “H” input
the worst case output when the worst “L” input is applied
the worst case output when the worst “H” input is applied
pLINnOFF
pSATnSAT
pOFFnLIN
VIL
VIH
VOL
VOH
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Inverter (2B) 25 Young Won Lim4/6/16
Noise Margin
VOL
VOH
VIH
VIL
NMH
NML
VOH
VOL
VIH
VIL
Noise
can be considered as a logic “L” input
can be considered as a logic “H” input
pLINnOFF
pSATnSAT
pOFFnLIN
VIL
VIH
VOL
VOH
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Inverter (2B) 26 Young Won Lim4/6/16
Simple Transistor Model
Cutoff, subthreshold, or weak-inversion mode
When VGS
< Vt:
Triode mode or linear region (the ohmic mode)
When VGS
> Vt and V
DS < ( V
GS – V
t )
Saturation or active mode
When VGS
> Vt and V
DS ≥ ( V
GS – V
t )
I d = k 'WL [(v gs − v t)v ds −
12
vds2 ]
I d =12
k 'WL
(v gs − v t)2
I d = 0
https://en.wikipedia.org/wiki/CMOS
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Inverter (2B) 27 Young Won Lim4/6/16
Linear and Saturation Models
I d = k 'WL [(v gs − v t)v ds −
12
vds2 ]
I d =12
k 'WL
(v gs − v t)2
linear region
When VGS
> Vt and V
DS < ( V
GS – V
t )
Saturation or active mode
When VGS
> Vt and V
DS ≥ ( V
GS – V
t )
https://en.wikipedia.org/wiki/CMOS
VDS
IDS
2(vgs − v t)
(vgs − v t)
VDS
IDS
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Inverter (2B) 28 Young Won Lim4/6/16
Bias Conditions
Cutoff V
GS < V
t:
Linear region V
GS > V
t
VDS
< ( VGS
– Vt )
Saturation V
GS > V
t
VDS
> ( VGS
– Vt )
VDS
VGS
IDS
https://en.wikipedia.org/wiki/CMOS
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Inverter (2B) 29 Young Won Lim4/6/16
Characteristic Curve
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Young Won Lim4/6/16
References
[1] http://en.wikipedia.org/[2] http://www.allaboutcircuits.com/[3] W. Wolf, “Modern VLSI Design : Systems on Silicon[4] N. Weste, D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”[5] J. P. Uyemura, “Introduction to VLSI Circuits and Systems”[6] https://en.wikiversity.org/wiki/The_necessities_in_SOC_Design[7] https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design[8] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design[9] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Architecture[10] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Organization[11] https://en.wikiversity.org/wiki/Verilog_programming_in_plain_view