CMOS CELLULAR RECEIVER FRONT-ENDS

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AUTOMATIC CALIBRATION OF MODULATEDFREQUENCY SYNTHESIZERS

CMOS CELLULAR RECEIVERFRONT-ENDS

From Specification to Realization

by

Johan JanssensKU Leuven, Belgium

and

Michiel SteyaertKU Leuven, Belgium

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

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voor Ons Ann

Preface

During the last decade, the world of mobile communications has experienced an enormousgrowth. To a great extent, this growth has been made possible by the migration from the originalall-analog mobile phones to handsets using digital technology. Another important enabler hasundoubtedly been the rapid progress in silicon IC technology, which made it possible to squeezeever more digital functions onto a single chip, reducing both the total terminal cost and the formfactor.

Whereas today’s mobile phones already feature a highly-integrated digital back-end, the ar-chitectures for the radio-frequency transceiver front-end generally still rely on external compo-nents to realize the most critical functions. Since the need for external components is tightlycoupled to the architecture of the front-end, there is a strong drive towards more advanced,highly-integrated architectures that rely less on this class of external components, leading tosignificant cost savings. In addition, the high-frequency front-end is mostly still implemented ina relatively expensive technology instead of in a cheap CMOS process (as e.g. the digital part).By also integrating the high-frequency analog front-end in CMOS technology, the cost can bereduced further. In the end, this might lead to a mobile phone on a single CMOS IC.

The presented work deals with the design of the receive path of a highly-integrated CMOStransceiver front-end for mobile communications. It covers the whole design trajectory startingfrom documents describing the standard down to the systematic development of CMOS ICswhich are measured to be compliant to the standard. In addition, it tackles CMOS receiverdesign at all abstraction levels: from architecture level, via circuit level, down to the devicelevel, and the other way around. The DCS-1800 standard — better known as GSM-1800 —is used as the demonstration vehicle throughout this work. In parallel to the application-driventrajectory, special attention is given to the fundamentals and the fundamental limits of radio-frequency CMOS design. This material forms the basis of a systematic design methodology forhigh-performance low-noise amplifiers.

In this work, two highly-integrated low-IF receive paths have been described which are em-bedded in a single-chip CMOS DCS-1800 transceiver. These ICs demonstrate the feasibility ofmeeting the performance requirements of today’s high-end cellular standards in a mainstreamsubmicron CMOS technology. In addition, the limits of RF CMOS design have been exploredby the realization of a high-performance low-noise amplifier (LNA) for the Global PositioningSystem. This LNA proves that CMOS can offer an extremely low noise figure and a large powergain, at the same power consumption as commercially available GaAs LNAs.

The outline of the work is illustrated in the figure below. After the introducing chapter,Chapter 2 introduces some general aspects of the radio-part of the DCS-1800 cellular system.Next, Chapter 3 compares different cellular receiver architectures with respect to integratability,

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ix

achievable performance and required building block specifications. After choosing the architec-ture which best suits our needs, the requirements of the DCS-1800 standard are translated into aset of specifications on the receiver as a whole. Eventually, the specifications are allocated to thedifferent building blocks.

In Chapter 4 and Chapter 5, we make a steep descent from the architecture level down tothe device level. In these chapters, the dynamics of elementary specifications are analyzed asa function of transistor parameters, boundary conditions and several non-idealities. In addition,these chapters cover the fundamentals, the peculiarities and the fundamental limits of RF CMOSdesign. In Chapter 6, the gathered knowledge is further refined and applied to the systematicdesign of CMOS LNAs.

Chapter 8, Chapter 7 and Chapter 9 present the design and measurement results of the mostimportant ICs that have been realized as a consequence of this work: a high-performance CMOSLNA for GPS, and two highly-integrated CMOS receiver front-ends for DCS-1800. Specialattention is given to the sizing procedures to design these topologies systematically for a set ofspecifications.

Acknowledgements

I am very grateful to my close colleagues Bram De Muer, Marc Borremans and Nobuyuki Itohfor the fruitful collaboration we had during the design of the different CMOS transceivers. PaulLeroux deserves special mention for the collaboration we had on CMOS low-noise amplifiers.In addition, I wish to thank Augusto Marques, Enzo Peluso and Koen Mertens for the manystimulating discussions we had on all aspects of analog design. Of course, I would also like toacknowledge Jan Crols, Jan Craninckx and Peter Kinget for bringing RF CMOS into the MICASresearch group.

Finally, I would like to express my gratitude to Dr. Shimizu and Dr. Iwai from Toshiba Cor-poration for providing us with their CMOS technology and for their confidence in our designteam.

Johan Janssens,Heverlee, September 2001.

Contents

Preface

Acknowledgements

Table of Contents

List of Symbols and Abbreviations

vii

xi

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xix

1 Introduction1.1 The Explosive Growth of Mobile Communications . . . . . . . . . . . . . . .1.2 The Need for Cost Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3 Cost Reduction through Integration . . . . . . . . . . . . . . . . . . . . . . . . .1.4 Research in the World: Transceivers from Past to Present . . . . . . . . . . . . .1.5 Research Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

113357

2 The DCS-1800 Communication System2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 Frequency Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3 Modulation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 MSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3.2 GMSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Receiver Architecture and Specifications3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2 Cellular Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 The Super-Heterodyne Architecture . . . . . . . . . . . . . . . . . . . . . 3.2.1.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.2 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 The Zero-IF and Low-IF Architecture . . . . . . . . . . . . . . . . . . . 3.2.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2.2 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Other Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3 A Low-IF Receive Path for a DCS-1800 Transceiver . . . . . . . . . . . . . .3.4 From DCS Standard to Receiver Specifications . . . . . . . . . . . . . . . . . .

3.4.1 From Bit-error Rate to Signal-to-noise Ratio . . . . . . . . . . . . . .

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4

5

3.5

3.63.73.8

Dee4.14.24.34.44.5

RF5.15.2

5.3

5.4

5.5

5.6

3.4.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.4.3 Image Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.4.4 LO Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.4.5 Intermodulation Performance . . . . . . . . . . . . . . . . . . . . . . . .3.4.6 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.4.7 Spurious Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .From Receiver Specifications to Circuit Specifications . . . . . . . . . . . . . . . .3.5.1 The Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5.2 Quadrature Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5.3 VGA –Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5.4 A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5.5 Overall Quadrature Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . .Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DCS- 1800 versus GSM-900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

p Submicron CMOS TransistorsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Hand Calculation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Transconductance and Transconductance Efficiency . . . . . . . . . . . . . . . .Distortion and Intermodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS Design for Analog DesignersIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Impedance-, Power- and Noise Matching . . . . . . . . . . . . . . . . . . . . . .5.2.1 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.2.2 Impedance Matching versus Power Matching . . . . . . . . . . . . . . . .5.2.3 Noise Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MOS Power Matching by Inductive Source Degeneration . . . . . . . . . . . . .5.3.1 Matching Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.3.2 Effective Transconductance and Power-to-Current Conversion . . . . . .5.3.3 Analysis of the Power Flow . . . . . . . . . . . . . . . . . . . . . . . .The Non-Quasi Static Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.4.1 Origin of the Non-Quasi Static Effect . . . . . . . . . . . . . . . . . . .5.4.2 First Order Non-Quasi Static Model . . . . . . . . . . . . . . . . . . . .5.4.3 Importance of the Non-Quasi Static Effect in the Low GHz Range . . . .Optimum MOS Power Matching . . . . . . . . . . . . . . . . . . . . . . . . . .5.5.1 Indirect Matching Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5.2 How Leaving Out the Matching Network M Affects the PCC . . . . . . .5.5.3 Fundamental Power Matching Limit . . . . . . . . . . . . . . . . . . . . .Noise Sources in MOS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .5.6.1 Classical Channel Thermal Noise . . . . . . . . . . . . . . . . . . . . . .5.6.2 Non-Quasi Static Gate Noise Current . . . . . . . . . . . . . . . . . . . . .5.6.3 Exotic and Parasitic Noise Sources . . . . . . . . . . . . . . . . . . . . .

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5.6.4 Performing Advanced Noise Simulations in a Classical Simulator . . . .5.7 The Noise Figure of an Input-Matched MOS Device . . . . . . . . . . . . . . . . .

5.7.1 Noise Figure under Noise Matching Conditions . . . . . . . . . . . . . . .5.7.2 Noise Figure under Source Matching Constraints . . . . . . . . . . . . . .5.7.3 Impact of the Source Matching Scheme on Noise Figure and PCC . . . .5.7.4 Some Early Considerations on Noise Optimization . . . . . . . . . . . . .

5.8 The IP3 of an Input-Matched MOS Device . . . . . . . . . . . . . . . . . . . . .5.8.1 Impact of Feedback on Linearity . . . . . . . . . . . . . . . . . . . . . . .5.8.2 Case Study: The of an Input-Matched MOS Device . . . . . . . . . .

5.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Systematic CMOS LNA Design6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.2 Narrow-band Low Noise Amplifier Topologies . . . . . . . . . . . . . . . . . . .6.3 Cascode Low Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . .6.4 Gain and Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1 From PCC to Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.4.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Impact of Input Capacitance on Matching, PCC and NF . . . . . . . . . . . . . .6.5.1 Impact on Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5.2 Impact on PCC and Noise Figure . . . . . . . . . . . . . . . . . . . . . . .6.5.3 A Low-Cp Bondpad Structure with a High Q-factor . . . . . . . . . . .

6.6 Impact of Cgd and M on Matching, PCC and NF . . . . . . . . . . . . . . . .6.7 LNA Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.8 The Design of the Cascode Device . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.1 Optimization of the Cascode Pole . . . . . . . . . . . . . . . . . . . . .6.8.2 Optimization of the Overall Noise Figure . . . . . . . . . . . . . . . . .6.8.3 Unwanted Side-effects Initiated by the Cascode . . . . . . . . . . . . . .

6.9 Systematic LNA Design: A Case Study . . . . . . . . . . . . . . . . . . . . . . . . .6.9.1 Target Specifications, Boundary Conditions and Constraints . . . . . . .6.9.2 Analysis of the Specification Dynamics . . . . . . . . . . . . . . . . . . . .6.9.3 Contour-Based Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Impact of the Source Resistance on Power Consumption . . . . . . . . . . . . .6.11 Fallacies and Pitfalls of LNA Noise Figure Dynamics . . . . . . . . . . . . . . .

6.11.1 The Actual Importance of the Non-Quasi Static Gate Noise . . . . . . . .6.11.2 The Tricky Relation between NF, and Current Consumption . . . . . .

6.11.2.1 The First Pitfall: NF versus for a Fixed LNA (Fixed W/L) . .6.11.2.2 The Second Pitfall: NF versus at a Fixed . . . . .6.11.2.3 Predicting the NF dynamics along an Arbitrary Trajectory . . . . .

6.12 Impact of a Finite ' on LNA Performance . . . . . . . . . . . . . . . . . . . . .6.12.1 Impact of a Finite on PCC and NF . . . . . . . . . . . . . . . . . . . .

6.12.1.1 Main Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . .6.12.1.2 Mathematical Explanation . . . . . . . . . . . . . . . . . . . . .

6.12.2 Impact of a Finite on and . . . . . . . . . . . . . . . . . . . .6.12.3 Intrinsically Unmatched Input Structures . . . . . . . . . . . . . . . . .

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6.12.3.1 Series Resonant Input Structure . . . . . . . . . . . . . . . . .6.12.3.2 Parallel Resonant Input Structure . . . . . . . . . . . . . . . .

6.13 Systematic LNA Design: The Case Study Revisited . . . . . . . . . . . . . . . .6.13.1 From a Match to a Match. . . . . . . . . . . . . . . . . . . .6.13.2 Direct Connection between the Source and the Input . . . . .

6.14 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 A CMOS Receiver Prototype for DCS–1800 Cellular Communications7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.2 Receiver Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.2.2 Down-converter with Active Inductor LO Interface . . . . . . . . . . . .

7.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.3.1 Down-converter and Active Inductor LO Interface . . . . . . . . . . . . . .7.3.2 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 A 0.8 dB NF, ESD-protected CMOS LNA8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.2 The GPS Frequency Plan in a Nutshell . . . . . . . . . . . . . . . . . . . . . .8.3 GPS Power Levels and LNA Requirements . . . . . . . . . . . . . . . . . . . .8.4 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.5 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8 ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.8.1 Measured ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . .8.8.2 Expected ESD Performance with an On-chip Clamp . . . . . . . . . .

8.9 Discussion and Comparison with Existing CMOS LNAs . . . . . . . . . . . . .8.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 A 2V CMOS DCS–1800 Receiver Front-End9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.2 Receiver Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3 The Down-Conversion Mixer and the Filter/VGA . . . . . . . . . . . . . . . . .

9.3.1 Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3.1.1 Conversion Gain . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3.1.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3.1.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3.1.4 DC offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.3.1.5 VGA input impedance . . . . . . . . . . . . . . . . . . . . . .9.3.1.6 VGA stability . . . . . . . . . . . . . . . . . . . . . . . . . .

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9.3.2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.4 The Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.1 Selection of the LNA Input Impedance . . . . . . . . . . . . . . . . . . .9.4.2 Optimization of the Coupling Capacitor . . . . . . . . . . . . . . . . . .9.4.3 Design Trajectory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.4.4 Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Noise Figure of Receiver SystemsA. 1 Sensitivity, Noise Factor and Noise Figure . . . . . . . . . . . . . . . . . . . .A.2 Noise Figure of Receiver Building Blocks . . . . . . . . . . . . . . . . . . . .

A.2.1 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A.2.2 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3 Noise Figure of Receiver Systems . . . . . . . . . . . . . . . . . . . . . . . . .A.3.1 Single-Path Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . .A.3.2 Quadrature Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B and IMx Ratios based on Taylor Expansion of

C Essentials of Two-port Noise Theory

Bibliography

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243

245

List of Symbols and Abbreviations

AbbreviationsA/D Analog to Digital ConverterAGC Automatic Gain ControlBER Bit Error RateBiCMOS Bipolar Complementary Metal Oxide SemiconductorCAD Computer Aided DesignCDMA Code Division Multiple AccessCMFB Common Mode FeedbackCMOS Complementary Metal Oxide SemiconductorDCS Digital Cellular SystemDIV Frequency DividerDSB Double Side-BandDSP Digital Signal ProcessorEDGE Enhanced Data Rates for GSM EvolutionESD Electro-Static DischargeETSI European Telecommunications Standard InstituteFDMA Frequency Division Multiple AccessGMSK Gaussian Minimum Shift KeyingGPRS General Packet Radio ServiceGPS Global Positioning SystemGSM Global System for Mobile CommunicationsHBM Human Body ModelHBT Hetero-junction Bipolar TransistorIF Intermediate FrequencyIMRR Image Rejection RatioLDD Lightly Doped DrainLF Low FrequencyLNA Low Noise AmplifierLO Local OscillatorMCM Multi-Chip ModuleMSK Minimum Shift KeyingnMOS n-channel MOSFETNQS Non-Quasi StaticOTA Operational Transconductance Amplifier

xx List of Symbols and Abbreviations

PA Power AmplifierPCN Personal Communication NetworkPCS Personal Communications ServicePDC Personal Digital CellularPLL Phase Locked LooppMOS p-channel MOSFETPFD Phase-Frequency DetectorPSD Power Spectral DensityQAM Quadrature Amplitude ModulationRF Radio FrequencyRX ReceiverSAW Surface Acoustic WaveSMS Short Message ServiceSNR Signal-to-Noise RatioSSB Single Side-BandTDMA Time Division Multiple AccessTX TransmitterUMTS Universal Mobile Communications SystemVCO Voltage-Controlled OscillatorVGA Variable-Gain AmplifierVLSI Very Large Scale IntegrationWAP Wireless Access Protocol

Symbols

Defined asApproximately equals (in case of an expression)Approximately equals (in case of a value)Proportional toSpecification is metSpecification is not metNode numbers

i ith bitBW BandwidthCVG Conversion gain of a mixerc Correlation coefficient between drain noise and gate noise

Parasitic parallel input capacitanceetc. Device capacitances

Equivalent input noise voltageF Noise factor

Eigen noise factor (noise factor without the noise of the source)Noise contribution of the classical drain noise currentNoise contribution of the correlated part of the gate noise currentNoise contribution of the uncorrelated part of the gate noise current

xxi

Minimum noise factor, corresponding to a noise matchOptimum noise factor when constraints are imposedUnity current gain frequency and pulsation

GBW Gain-bandwidth productTransconductance of a MOS transistorBulk transconductanceEffective transconductanceOutput conductance of a MOS transistorTransducer power gainConductance associated with the uncorrelated part of

h(t) Impulse response of a filterSecond-order and third-order harmonic distortion ratioPart of that is correlated toPart of that is uncorrelated toDrain currentSecond-order and third-order intermodulation ratio

IMRR Image rejection ratioEquivalent input noise currentDrain noise currentNon-quasi static gate noise currentNon-quasi static bulk noise currentSecond-order and third-order intercept pointTransconductance parameter of a nMOS, pMOS transistor

k Boltzmann’s constantL, W Channel length and width of MOS transistor

Gate and source inductancem FM modulation indexM Miller amplification factorn Factor modeling the bulk effectNF Noise figure

System noise figureq Elementary chargeQ Quality factor of a network

Available powerPCC Power-to-current conversion

Dissipated signal powerDC power consumptionInput powerNoise power in the lower side-bandNoise power in the upper side-band

PVC Power-to-voltage conversionResistance of the back-gateResistance of the gate fingersNon-quasi static gate resistanceInput resistance

xxii List of Symbols and Abbreviations

Resistance associated with the equivalent input noise voltageEquivalent parallel resistance of a passive elementSource resistanceSource resistance, as seen by the inductive matching networkEquivalent source resistance, as seen by the transistorCharacteristic impedance of a local reference planeRelative amount of velocity saturationForward gain and input reflectionSelectivity of a filter at a frequency offsetTime-varying power spectral density

T Absolute temperatureBit period (inverse of the bit rate)DC Gate-source over-drive voltage, i.e.Drain to source and gate to source voltagesDrain to source saturation voltageSaturation speed of an electron in a high electric fieldTransit voltage between strong inversion and velocity saturationThreshold voltage of a MOS transistorCorrelation admittance (ratio between andSource admittance corresponding to a noise matchSource admittanceTerminating, characteristic and source impedanceInput impedanceRatio between the device capacitances andInverse of nCurrent factor of a MOS transistorParameter modeling the gate noise currentSmall phase differenceExcess noise factorReflection coefficientElmore constant of the channelParameter modeling the channel length modulationMobility and effective mobilityInstantaneous phaseParameters modeling the mobility degradationReflection coefficient when the matching network is omittedOperating frequency (or in fact the corresponding pulsation)Bit pulsationCenter frequency (or in fact the corresponding pulsation)

i i Instantaneous frequencyMaximum and minimum instantaneous frequency