CMOS and TTL Techmologies
Transcript of CMOS and TTL Techmologies
CMOS and TTL Technologies
Z. Jerry ShiDepartment of Computer Science and EngineeringDepartment of Computer Science and Engineering
University of Connecticut
CSE2300W:Digital Logic Design
Physical states representing bits
Technology State Representing Bit
0 10 1
Relay logic Circuit open Circuit closed
CMOS logic 0-1.5V 3.5-5V
Transistor-transistor logic 0-0.8V 2-5V
Fiber optics Light off Light on
Dynamic memory Capacitor discharged Capacitor charged
Nonvolatile, erasable memory Electrons trapped Electrons released
Bipolar read-only memory Fuse blown Fuse intactBipolar read only memory Fuse blown Fuse intact
Magnetic tape or disk Flux direction N Flux direction S
Read-only compact disc No pit Pit
Writeable compact disc (CD-R) Dye in crystalline state Dye in noncrystalline state
CMOS logic levels
• Undefined region is inherent• Switching threshold varies with voltage temp process phase of the moon• Switching threshold varies with voltage, temp, process, phase of the moon
– Need “noise margin”– The average weekly count of failure in Q in Los Alamos Lab is 47.1
• The more you push the technology, the more “analog” it becomes– Logic voltage levels decreasing with process– 5 3.3 2.5 1.8 V
Noise margins
Low voltage CMOS logic
Metal-Oxide-Semiconductor (MOS) Transistors
Voltage-controlled resistance
PMOSPMOS
NMOS
CMOS Inverter
Inverter
Inverter behavior
CMOS NAND gate
CMOS NOR gate
Example of LS-TTL gates: 2-input NAND
TTL Logic Levels and Noise Margins
• Asymmetric, unlike CMOS
• CMOS can be made compatible with TTL– “T” CMOS logic familiesT CMOS logic families
CMOS vs. TTL Levels
TTL Levels
CMOS with TTL Levels -- HCT, FCT, VHCT, etc.
TTL features
• TTL families7400 series– 74 (standard), 74H(high speed), 74L(low-power), 74S(Schottky),
74LS(low-power Schottky), 74AS(Advanced Schottky), 74ALS (Advanced low-power Schottky), 74F(Fast)
• Unused gate inputs can be left unconnected, but should be connected to be safe– An output of other gates– 1 or 0 through pull-up or pull-down resistorsg p p p
• Output– Totem pole
Tri state– Tri-state – Open-collector
CMOS features
• CMOS families: – 4000 series4000 series– 7400 series:
• 74HC (high-speed CMOS), 4 C ( i h d C OS ibl )• 74HCT(High-speed CMOS, TTL compatible)
• 74AC(Avanced CMOS)• 74ACT(Advanced CMOS, TTL compatible)• 74FCT(Fast CMOS, TTL compatible) • 74FCTT(Fast CMOS, TTL compatible with TTL VOH)
• Do not leave unused gate inputs unconnected• Do not leave unused gate inputs unconnected• Output
– Regular, Tri-state, Open-draing , , p
Chip density for various scales of integration
Timing specifications
• Maximum: the longest delay a circuit may have– The delay of the path is never longer than the maximum– What does never mean?
• Depends on manufacturers and logic families• 74LS: VDD = 5V, T = 25ºC, no capacitive load
f ll i l d d l d f• 74ACT: full operating voltage and temperature range and a load of 50pF
• Typical: what you see from a device that was manufactured on a good day and i ti d id l ditiis operating under near-ideal conditions
• Minimum: The smallest delay that a path will ever exhibitM t ll d i d i it k if th i i d l i 0– Most well-designed circuits work even if the minimum delay is 0
– Needs to be considered in some circuits• Help designers to meet the hold-time requirements
Propagation delay of selected 5-V CMOS and TTL SSI parts
In nanoseconds
MSI parts
In nanoseconds
Fan-in and Fan-out
• A logic family’s fan-in is the number of inputs that a gate can have– More inputs more resistors in series long delay– Faster to cascading multiple gates
• Fan-out refers to the number and type of device inputs and other loads that are connected to a given output– Large fan-out more load long delayLarge fan out more load long delay– Large load inadequate noise margins