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Embedded Systems Exercise 1 - FS 20187.3.2018Rehan Ahmed

Institut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Rehan Ahmed 7.3.2018 1

Corrections

• Task 1.2: Add the following assumption:It is assumed that the multiplexer is dual channel (a single multiplexer can be usedto select both BL and BL).

• Task 2 (b): Change 48 KHz to 48 MHz.


Task 1.1: Memory

(a) How many different addresses are available for peripherals?

(b) How many different addresses are available for ports?

(c) Suppose an LED is connected to Port 2, Pin 5. Determine the memory address ofPort 2, and value which has to be written to this address, to turn the LED on.

(d) How many Bytes can be written in the ROM region. How many 32 bit words can bewritten in the ROM region?


Task 1.2: Memory. SRAM Design

Determine the optimal partitioning of SRAM address bits into row select (used to selectword lines) and column select (used to select bit lines) bits. The objective is to minimizethe area of the SRAM. Use the follow data for your computations:u: Number of bits to select a word linew : Number of bits to select a bit line

u + w = 8

Area of 1 memory cell: Amem = 6

Area of 2-1 mux: Amux = 4

Area of 2-input AND gate: AAND = 1

Area of Invetrer: ANOT = 1

Awires = 0

Area 1 bit sense-amp: Asense = 5


SRAM Architecture

Components that contribute to area of memory:

Area of memory cells.

Amem = 6

Area of decoder for activating word lines.

Area of multiplexer for selecting bit-lines.

Amux = 4

Area of sense amplifiers.

Asense = 5


SRAM Architecture

Components that contribute to area of memory:

Area of memory cells. Amem = 6

Area of decoder for activating word lines.

Area of multiplexer for selecting bit-lines. Amux = 4

Area of sense amplifiers. Asense = 5


Decoder construction

I0 O0

O1

=> I0 decoder(1)O0

O1

2-bit decoder can be constructed using two 1-Bit decoders and 4 AND gates:

I0 decoder(1)

I1 decoder(1)

O0

O1

O2

O3

=>I0I1

decoder(2)

O0O1O2O3


Multiplexer construction

2-to-1 multiplexer is represented using:

S0 multiplexer(1)

I1 I0

O

4-to-1 multiplexer can be constructed using 3x 2-to-1 multiplexers:

S0 multiplexer(1)

I3 I2

multiplexer(1)

I1 I0

multiplexer(1)

O

S1


Task 1.1 Solution

(a) Peripherals addresses have the following range [0x4000_0000, 0x5FFF_FFFF].Total addressable locations = 0x5FFF_FFFF - 0x4000_0000 + 1 = 0x2000_0000 or229.

(b) Port addresses have the following range [0x4000_4C00, 0x4000_4FFF]. Totaladdressable locations = 0x4000_4FFF - 0x4000_4C00 + 1 = 0x0400 or 210.

(c) Port 2 address = 0x4000_4C00 + 0x0003 = 0x4000_4C03Following binary value should be written to this address: 001000002.

(d) ROM addresses have the following range [0x0200_0000, 0x020F_FFFF]. Totaladdressable locations = 0x020F_FFFF - 0x0200_0000 + 1 = 0x010_0000 or 220

Bytes → 1 Mega Byte.Number of 4 Byte words: 220/4 words = 256 Kilo words.


Task 1.1 SolutionArea of memory cells: 28 · Amem = 1536

Area of sense amplifiers:S(w) = 2w · Asense

k bit decoder can be constructed using:

2 Decoders of sizes:– { k

2 , k2 } if k is even.

– { k−12 , k+1

2 } if k is odd.2k 2-Input AND gates.

D(k ) =

ANOT = 1 if k = 1

2 · D( k2 ) + AAND · 2k if k > 1 and k is even

D( k−12 ) + D( k+1

2 ) + AAND · 2k if k > 1 and k is odd


Task 1.1 SolutionArea of memory cells: 28 · Amem = 1536Area of sense amplifiers:

S(w) = 2w · Asense

k bit decoder can be constructed using:

2 Decoders of sizes:– { k

2 , k2 } if k is even.

– { k−12 , k+1

2 } if k is odd.2k 2-Input AND gates.

D(k ) =

ANOT = 1 if k = 1


D( k−12 ) + D( k+1



Task 1.1 SolutionArea of memory cells: 28 · Amem = 1536Area of sense amplifiers:

S(w) = 2w · Asense

k bit decoder can be constructed using:2 Decoders of sizes:

– { k2 , k

2 } if k is even.– { k−1

2 , k+12 } if k is odd.

2k 2-Input AND gates.

D(k ) =

ANOT = 1 if k = 1


D( k−12 ) + D( k+1



Task 1.2 Solution2l -to-1 multiplexer can be constructed using:

Two 2l−1-to-1 multiplexers.One 2-to-1 multiplexer.

Area of multiplexer with k select lines:

M(k ) =

Amux = 4 if k = 1

2 · M(k − 1) + Amux otherwise

u w Decoder Multiplexer Sense Amp Total

0 8 0 1020 1280 23001 7 1 508 640 11492 6 6 252 320 5783 5 15 124 160 2994 4 28 60 80 1685 3 53 28 40 1216 2 94 12 20 1267 1 171 4 10 2238 0 312 0 5 317


Task 2: CommunicationSuppose that a sender and a receiver exchange data via UART with followingconfiguration: Baudrate = 115200 bits/s; 1 start bit, 2 stop bits, 8 data bits, 1 parity bit;16 clock periods used for sampling 1 bitAnswer the following questions:

(a) What is the required clock frequency?

(b) Suppose a 48 MHz clock. What is a suitable division factor?

(c) How long does it take to transfer 10 MBytes of data?(d) Suppose that we use division factor as computed in part b. The sender has a basic

clock frequency of 48 MHz. What is the range of clock frequencies of the receiversuch that:

– all symbols are correctly recognized.– signal is stable between 1 period before and after the sampling time.


Task 2 Solution

(a) clock frequency = 115200 · 16 = 1.8432MHz.

(b) division factor = 48×106

1.8432×106 = 26.04167 => 26

(c) 1 Byte uses 1 + 2 + 8 + 1 = 12 symbols. Total payload = 10 × 106 · 12 symbols.Time taken to transmit the payload:

T =10 × 106 · 12 symbols

115200 symbols/s= 1041.67s


Task 2 Solution(d) Sender’s transmission rate:rs = 48×106

26 .Receiver’s reception rate: rr = Fr

26 . Fr =?.

start ... ...

start of parity bit

stop 1 ...stop 2

10/rs 12/rs

10.5/rr 11.5/rr

For correct reception of all bits, we have the following two conditions:– If receiver is slower, the second stop bit must be sampled no later than 12

rs− 1

rr ·16 .– If receiver is faster, the first stop bit must be sampled no earlier than 10

rs+ 1

rr ·16 .

Time when receiver samples the {first, second} stop bit: {10.5rr

, 11.5rr

}. Therefore:11.5

rr≤ 12

rs− 1

rr ·16 => Fr ≥ 46.25MHz.10.5

rr≥ 10

rs+ 1

rr ·16 => Fr ≤ 50.1MHz.

46.25MHz ≤ Fr ≤ 50.1MHz


Task 2 Solution(d) Sender’s transmission rate:rs = 48×106

26 .Receiver’s reception rate: rr = Fr

26 . Fr =?.

start ... ...

start of parity bit

stop 1 ...stop 2

10/rs 12/rs10.5/rr 11.5/rr

For correct reception of all bits, we have the following two conditions:– If receiver is slower, the second stop bit must be sampled no later than 12

rs− 1

rr ·16 .– If receiver is faster, the first stop bit must be sampled no earlier than 10

rs+ 1

rr ·16 .

Time when receiver samples the {first, second} stop bit: {10.5rr

, 11.5rr

}. Therefore:11.5

rr≤ 12

rs− 1

rr ·16 => Fr ≥ 46.25MHz.10.5

rr≥ 10

rs+ 1

rr ·16 => Fr ≤ 50.1MHz.

46.25MHz ≤ Fr ≤ 50.1MHzInstitut für Technische Informatikund KommunikationsnetzeComputer Engineering andNetworks Laboratory Rehan Ahmed 7.3.2018 13

Task 3: Interrupt and PollingAn external event is sensed using polling with period P. It takes 100 cycles to processthe event. Processor frequency is 48 MHz. Before starting a new period, the previouspolling task should have finished. The relative deadline for processing an event is 10µs.

(a) Determine the range of feasible polling periods?(b) Suppose now that an unrelated interrupt may occur and the interrupt has higher

priority than the code for processing the polling event. Including all overhead, ittakes 40 cycles to process the interrupt. The minimum time between twosubsequent interrupts is T . Suppose that T is larger than 140 cycles. Determinethe range of feasible polling periods.

(c) What is the minimum feasible time between two interrupts (T ) and thecorresponding feasible polling period P?


Task 3(a) Solution

Computation time = C = 10048×106 = 2.0833µs

Maximum response time:

External event

P C

Response time

Worst-case response time = P + CResponse time must not exceed deadline: P + 2.0833µs ≤ 10µsPolling period must not be less than computation time: P ≥ 2.0833µsTherefore: 2.0833µs ≤ P ≤ 7.9167µs


Task 3(a) Solution



External event

P C

Response time

Worst-case response time = P + C

Response time must not exceed deadline: P + 2.0833µs ≤ 10µsPolling period must not be less than computation time: P ≥ 2.0833µsTherefore: 2.0833µs ≤ P ≤ 7.9167µs


Task 3(a) Solution



External event

P C

Response time

Worst-case response time = P + CResponse time must not exceed deadline: P + 2.0833µs ≤ 10µs

Polling period must not be less than computation time: P ≥ 2.0833µsTherefore: 2.0833µs ≤ P ≤ 7.9167µs


Task 3(a) Solution



External event

P C

Response time

Worst-case response time = P + CResponse time must not exceed deadline: P + 2.0833µs ≤ 10µsPolling period must not be less than computation time: P ≥ 2.0833µs

Therefore: 2.0833µs ≤ P ≤ 7.9167µs


Task 3(a) Solution



External event

P C

Response time

Worst-case response time = P + CResponse time must not exceed deadline: P + 2.0833µs ≤ 10µsPolling period must not be less than computation time: P ≥ 2.0833µsTherefore: 2.0833µs ≤ P ≤ 7.9167µs


Task 3(b) Solution

Time taken for processing one interrupt: 4048×106 = 0.833µs.

There can be at-most one interrupt within the processing of one polling request(because of 140 cycles between subsequent interrupts).Making worst-case assumption that whenever a polling request is processed, 40 cyclesare spent in interrupt processing.2.0833µs + 0.8333µs + P ≤ 10µsP ≥ 2.08µs + 0.8333µsTherefore: 2.9167 ≤ P ≤ 7.0833µs


Task 3(c) Solution

E = 100 + 40 · kE = Total computations in one polling period, k= the maximum number of interrupts within one polling period.

Feasibility conditions: (a)P + E48×106 ≤ 10µs (b) E

48×106 ≤ PMaximizing E to maximize k : E = P · 48 × 106 (inequality (b)). Therefore:2 · E

48×106 ≤ 10µs => E ≤ 240 cyclesk ≤ 240−100

40 = b3.5c k ≤ 3.Time taken for processing one event and three interrupts: 100+40·3

48×106 = 4.583µs.Minimum feasible value of T = 4.583

3 = 1.528µsFeasible range for polling period: 4.583µs ≤ P ≤ 5.417µs


Task 3(c) Solution



48×106 ≤ P

Maximizing E to maximize k : E = P · 48 × 106 (inequality (b)). Therefore:2 · E

48×106 ≤ 10µs => E ≤ 240 cyclesk ≤ 240−100





Task 3(c) Solution




48×106 ≤ 10µs => E ≤ 240 cyclesk ≤ 240−100

40 = b3.5c k ≤ 3.

Time taken for processing one event and three interrupts: 100+40·348×106 = 4.583µs.

Minimum feasible value of T = 4.5833 = 1.528µs

Feasible range for polling period: 4.583µs ≤ P ≤ 5.417µs


Task 3(c) Solution




48×106 ≤ 10µs => E ≤ 240 cyclesk ≤ 240−100


48×106 = 4.583µs.

Minimum feasible value of T = 4.5833 = 1.528µs

Feasible range for polling period: 4.583µs ≤ P ≤ 5.417µs


Task 3(c) Solution




48×106 ≤ 10µs => E ≤ 240 cyclesk ≤ 240−100





Questions?

Rehan AhmedETZ [email protected]


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