CKM Data Source System CKM Electronics Group July 2003.
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Transcript of CKM Data Source System CKM Electronics Group July 2003.
CKM Data Source System
CKM Electronics Group
July 2003
Module DAQ System
Event Builder(Switch)
DATACombiner
CLKSys.
DATACombiner
PC Farm
No-op
Reset/Sync.
CLK
TS10
TS32
Digitizer
Serial Links, Optic fiber or LVDS pairs
From Simulation (1)
MC8%
BTSM0%
UMS20%
KRICH5%
KEAT7%
BIVS8%
VVS14%
DMS3%
ETP0%
PRICH3%
FVS24%
MVS8%
CVP0%HVS0%
50 GB/spill
From Simulation (2)
0 0.5 1 1.5 2 2.5 3 3.5 4
BTSMUMS
KRICHKEATBIVSVVSDMSETP
PRICHFVSMVSCVPHVS
MB/spill/ch
From Simulation (3)1
8824
3135
6114
114
10135
12
0 20 40 60 80 100 120
BTSMUMS
KRICHKEATBIVSVVSDMSETP
PRICHFVSMVSCVPHVS
Number of Links Needed
From Simulation (4)512.0
146.5295.8
138.642.935.7
331.4512.0
260.031.444.6
512.050.0
0.0100.0200.0300.0400.0500.0600.0
BTSMUMSKRICHKEATBIVSVVSDMSETPPRICHFVSMVSCVPHVS
Ch/linkNumber of detector channels Served by 1 of the 400 data links.
Multiplexers Needed
1GE
1GE
300
chan
nels
30 c
hann
els 1GE
1GE
One Size Fits All--Building Block
• Similar as the PCI card Bill H. designed for clock system.
• Possible Configuration:– 8 data ports ( RJ-45,
1Gb/s ea.)– 2 clock ports (RJ-45,
1Gb/s ea.)– 2 GE ports (fiber,
1Gb/s ea.)FPGA
RAM
Information Traffic Assignment
Macro Slices
CLK/SYCCLK return
CLK/SYCCLK return
Macro Slices
CLK/SYCCLK return
Centenaries Slow ControlSlow Monitoring
Slow Control Slow Monitoring
5V, 3.3VDetector ChannelMonitoring
FPGA
RAM
Macro Slices
Usage Example (DMS)TDC
16 CH
TDC16 CH
TDC16 CH
TDC16 CH
TDC16 CH
TDC16 CH
TDC16 CH
TDC16 CH
Data from up to 512 Channels
FPGA
RAMSafety Factor:S1 > 1
Safety Factor:= 8 * S1
250 MB RAMSafety Factor= 2.8(3 sec spill)
Usage Example (FVS)
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
ADCTDC8 CH
Data from 32 Channels
Data from 32 Channels
FPGA
RAM
Safety Factor:= 4 * S1
Safety Factor:S1 > 1
250 MB RAMSafety Factor= 1.8
Using an Old PC as Crate
Data to DAQSwitch
CLK Link toNext Card
CLK Link
Ethernet100 Mb/s
FPGA
RAM
FPGA
RAM
FPGA
RAM
FPGA
RAM
Zero Cost PC’s: Old and Current Farms
Site 38
Cost
Item Qty. Ea. Total
PCI cards 300-400 $500 $200K
PC’s and Ethernet Cards
80-100 $0 (Site 38) $0
$200K
Summary
• The Data Source System groups data from front end cards into balanced data streams feeding into DAQ switch.
• It also distributes timing reference (clock) to the front end cards.
• It also handles slow control, monitoring functions. (There is no separate slow control system – we hope)
FPGA
RAM
Using an New PC as Crate
Data to DAQSwitch
CLK Link toNext Card
CLK Link
Gigabit Ethernet Card
Software DrivenPCI Data Flow
Cost (2)
Item Qty. Ea. Total
PCI cards 400 $500 $200K
PC’s and Ethernet Cards
400 $1000 $400K
$600K
Parallel Data to Gigabit Ethernet
http://atlas-tdaqtalks.web.cern.ch/ATLAS-TDAQtalks/colmar_papers/B33.pdf
GE Port
Data PortAltera FLEX 10K50A