Circuito Integrado 24LC16 8K/16K2.5VSPIOBusSerial EEPROM - Manual Sonigate

M

24LC08B/16B MODULES

8K/16K I

2

C

™

Serial EEPROMs in ISO Micromodules

FEATURES

• ISO 7816 compliant contact locations• Single supply with operation from 2.5-5.5V• Low power CMOS technology

- 1 mA active current typical- 10 µA standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I2C compatible• Schmitt trigger inputs for noise suppression• Output slope control to eliminate ground bounce• 100 kHz (2.5V) and 400kHz (5V) compatibility• Self-timed write cycle (including auto-erase)• Page-write buffer for up to 16 bytes• 2 ms typical write cycle time for page-write• ESD protection > 4,000V• 1,000,000 ERASE/WRITE cycles guaranteed• Data retention > 200 years• Temperature range

DESCRIPTION

The Microchip Technology Inc. 24LC08B/16B are 8Kand 16K bit Electrically Erasable PROMs in ISO mod-ules for smart card applications. The device is orga-nized as four or eight blocks of 256 x 8-bit memory witha 2-wire serial interface. The 24LC08B and 24LC16Balso have a page-write capability for up to 16 bytes ofdata.

ISO MODULE LAYOUT

BLOCK DIAGRAM

- Commercial (C): 0˚C to +70˚C

VSS

SDASCL

VDD

HV GENERATOR

EEPROM ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMPR/W CONTROL

MEMORYCONTROL

LOGIC

I/OCONTROL

LOGIC

SDA SCL

VCC

VSS

1997 Microchip Technology Inc. DS21224A-page 1

I2C is a trademark of Philips Corporation.

24LC08B/16B MODULES

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

VCC...................................................................................7.0VAll inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0VStorage temperature ..................................... -65˚C to +150˚CAmbient temp. with power applied................. -65˚C to +125˚CSoldering temperature of leads (10 seconds) ............. +300˚CESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this specification is not implied. Exposure to maximum ratingconditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

VSS Ground

SDA Serial Data

SCL Serial Clock

VCC +2.5V to 5.5V Power Supply

TABLE 1-2 DC CHARACTERISTICS

All Parameters apply across the speci-fied operating ranges unless otherwise noted.

Commercial (C): Tamb = 0˚C to +70˚C, VCC = 2.5V to 5.5V

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:High level input voltage VIH 0.7 VCC V (Note)

Low level input voltage VIL 0.3 VCC V (Note)

Hysteresis of Schmitt trigger inputs VHYS 0.05 VCC — V Vcc ≥ 2.5V (Note)

Low level output voltage VOL 0.40 V IOL = 3.0 mA, VCC = 4.5VIOL = 2.1 mA, VCC = 2.5V

Input leakage current ILI -10 10 µA VIN = VCC or VSS

Output leakage current ILO -10 10 µA VOUT = VCC or VSS

Pin capacitance (all inputs/outputs) CIN, COUT

— 10 pF VCC = 5.0V (Note)Tamb = 25˚C, f = 1 MHz

Operating current ICC Write — 3 mA VCC = 5.5V, SCL = 400 kHz

ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz

Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC

Note: This parameter is periodically sampled and not 100% tested.

DS21224A-page 2 1997 Microchip Technology Inc.

24LC08B/16B MODULES

TABLE 1-3 AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the specified operat-ing ranges unless otherwise noted.

Vcc = 2.5V to 5.5VCommercial (C): Tamb = 0°C to +70°C

Parameter Symbol

Vcc = 2.5V - 5.5VSTD MODE

Vcc = 4.5V - 5.5VFAST MODE Units Remarks

Min. Max. Min. Max.

Clock frequency FCLK — 100 — 400 kHzClock high time THIGH 4000 — 600 — nsClock low time TLOW 4700 — 1300 — nsSDA and SCL rise time TR — 1000 — 300 ns (Note 1)SDA and SCL fall time TF — 300 — 300 ns (Note 1)START condition hold time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generatedSTART condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated

START conditionData input hold time THD:DAT 0 — 0 — ns (Note 2)Data input setup time TSU:DAT 250 — 100 — nsSTOP condition setup time TSU:STO 4000 — 600 — nsOutput valid from clock TAA — 3500 — 900 ns (Note 2)Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can start

Output fall time from VIH

minimum to VIL maximumTOF — 250 20 +0.1

CB

250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression(SDA and SCL pins)

TSP — 50 — 50 ns (Notes 1, 3)

Write cycle time TWC — 10 — 10 ms Byte or Page modeEndurance 1M — 1M — cycles 25°C, VCC = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT TSU:STO

THD:STATBUFTAATAA

TSP

THD:STA

SCL

SDAIN

SDAOUT


24LC08B/16B MODULES

2.0 PAD DESCRIPTIONS

2.1 SDA (Serial Data)

This is a Bi-directional pin used to transfer addressesand data into and data out of the device. It is an opendrain terminal, therefore the SDA bus requires a pull-upresistor to VCC (typical 10Ω).

For normal data transfer SDA is allowed to change onlyduring SCL low. Changes during SCL high arereserved for indicating the START and STOP condi-tions.

2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer fromand to the device.

3.0 FUNCTIONAL DESCRIPTIONThe 24LC08B/16B supports a Bi-directional 2-wire busand data transmission protocol. A device that sendsdata onto the bus is defined as transmitter, and adevice receiving data as receiver. The bus has to becontrolled by a master device which generates theserial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions, while the24LC08B/16B works as slave. Both, master and slavecan operate as transmitter or receiver but the masterdevice determines which mode is activated.

4.0 BUS CHARACTERISTICSThe following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have beendefined (Figure 5-2).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition.All commands must be preceded by a START condi-tion.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations must be ended with a STOP condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.

The data on the line must be changed during the LOWperiod of the clock signal. There is one clock pulse perbit of data.

Each data transfer is initiated with a START conditionand terminated with a STOP condition. The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited, although only the last 16will be stored when doing a write operation. When anoverwrite does occur it will replace data in a first in firstout fashion.


24LC08B/16B MODULES

4.5 Acknowledge

Each receiving device, when addressed, is obliged togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. During reads, a master must signal an end ofdata to the slave by NOT generating an acknowledgebit on the last byte that has been clocked out of theslave. In this case, the slave (24LC08B/16B) will leavethe data line HIGH to enable the master to generate theSTOP condition.

5.0 DEVICE ADDRESSINGA control byte is the first byte received following thestart condition from the master device. The control byteconsists of a 4-bit control code, for the 24LC08B/16Bthis is set as 1010 binary for read and write operations.The next three bits of the control byte are the blockselect bits (B2, B1, B0). They are used by the masterdevice to select which of the eight 256 word blocks ofmemory are to be accessed. These bits are in effect thethree most significant bits of the word address.

The last bit of the control byte defines the operation tobe performed. When set to one a read operation isselected, when set to zero a write operation is selected.Following the start condition, the 24LC08B/16B moni-tors the SDA bus checking the device type identifierbeing transmitted, upon a 1010 code the slave deviceoutputs an acknowledge signal on the SDA line.Depending on the state of the R/W bit, the 24LC08B/16B will select a read or write operation.

FIGURE 5-1: CONTROL BYTE ALLOCATION

FIGURE 5-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24LC08B/16B does not generate anyacknowledge bits if an internal program-ming cycle is in progress.

OperationControl Code

Block Select R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

SLAVE ADDRESS

1 0 1 0 B2 B1 B0

R/W A

START READ/WRITE

(A) (B) (D) (D) (A)(C)

STARTCONDITION

ADDRESS ORACKNOWLEDGE

VALID

DATAALLOWED

TO CHANGE

STOPCONDITION

SCL

SDA


24LC08B/16B MODULES

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, thedevice code (4 bits), the block address (3 bits), and theR/W bit which is a logic low is placed onto the bus bythe master transmitter. This indicates to the addressedslave receiver that a byte with a word address will followafter it has generated an acknowledge bit during theninth clock cycle. Therefore the next byte transmitted bythe master is the word address and will be written intothe address pointer of the 24LC08B/16B. After receiv-ing another acknowledge signal from the 24LC08B/16Bthe master device will transmit the data word to be writ-ten into the addressed memory location. The 24LC08B/16B acknowledges again and the master generates astop condition. This initiates the internal write cycle,and during this time the 24LC08B/16B will not generateacknowledge signals (Figure 6-1).

6.2 Page Write

The write control byte, word address and the first databyte are transmitted to the 24LC08B/16B in the sameway as in a byte write. But instead of generating a stopcondition the master transmits up to 16 data bytes tothe 24LC08B/16B which are temporarily stored in theon-chip page buffer and will be written into the memoryafter the master has transmitted a stop condition. Afterthe receipt of each word, the four lower order addresspointer bits are internally incremented by one. Thehigher order seven bits of the word address remainsconstant. If the master should transmit more than 16words prior to generating the stop condition, theaddress counter will roll over and the previouslyreceived data will be overwritten. As with the byte writeoperation, once the stop condition is received an inter-nal write cycle will begin (Figure 6-2).

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

S P

BUS ACTIVITYMASTER

SDA LINE

BUS ACTIVITY

START

STOP

CONTROLBYTE

WORDADDRESS DATA

ACK

ACK

ACK

S P

BUS ACTIVITYMASTER

SDA LINE

BUS ACTIVITY

START

CONTROLBYTE

WORDADDRESS (n) DATA n DATA n + 15

STOP

ACK

ACK

ACK

ACK

ACK

DATA n + 1


24LC08B/16B MODULES

7.0 ACKNOWLEDGE POLLINGSince the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (this feature can be used to maximize busthroughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling canbe initiated immediately. This involves the master send-ing a start condition followed by the control byte for awrite command (R/W = 0). If the device is still busy withthe write cycle, then no ACK will be returned. If thecycle is complete, then the device will return the ACKand the master can then proceed with the next read orwrite command. See Figure 7-1 for flow diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING FLOW

8.0 READ OPERATIONSRead operations are initiated in the same way as writeoperations with the exception that the R/W bit of theslave address is set to one. There are three basic typesof read operations: current address read, randomread, and sequential read.

8.1 Current Address Read

The 24LC08B/16B contains an address counter thatmaintains the address of the last word accessed, inter-nally incremented by one. Therefore, if the previousaccess (either a read or write operation) was toaddress n, the next current address read operationwould access data from address n + 1. Upon receipt ofthe slave address with R/W bit set to one, the24LC08B/16B issues an acknowledge and transmitsthe 8-bit data word. The master will not acknowledgethe transfer but does generate a stop condition and the24LC08B/16B discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to accessany memory location in a random manner. To performthis type of read operation, first the word address mustbe set. This is done by sending the word address to the24LC08B/16B as part of a write operation. After theword address is sent, the master generates a start con-dition following the acknowledge. This terminates thewrite operation, but not before the internal addresspointer is set. Then the master issues the control byteagain but with the R/W bit set to a one. The 24LC08B/16B will then issue an acknowledge and transmits the8-bit data word. The master will not acknowledge thetransfer but does generate a stop condition and the24LC08B/16B discontinues transmission (Figure 8-2).

8.3 Sequential Read

Sequential reads are initiated in the same way as a ran-dom read except that after the 24LC08B/16B transmitsthe first data byte, the master issues an acknowledgeas opposed to a stop condition in a random read. Thisdirects the 24LC08B/16B to transmit the next sequen-tially addressed 8 bit word (Figure 8-3).

To provide sequential reads the 24LC08B/16B containsan internal address pointer which is incremented byone at the completion of each operation. This addresspointer allows the entire memory contents to be seriallyread during one operation.

8.4 Noise Protection

The 24LC08B/16B employs a VCC threshold detectorcircuit which disables the internal erase/write logic ifthe VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filtercircuits which suppress noise spikes to assure properdevice operation even on a noisy bus.

SendWrite Command

Send StopCondition to

Initiate Write Cycle

Send Start

Send Control Bytewith R/W = 0

Did DeviceAcknowledge(ACK = 0)?

NextOperation

NO

YES


24LC08B/16B MODULES

FIGURE 8-1: CURRENT ADDRESS READ

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

S P

BUS ACTIVITYMASTER

SDA LINE

BUS ACTIVITY

START

STOP

CONTROLBYTE DATA n

ACK

NO ACK

S PS

BUS ACTIVITYMASTER

SDA LINE

BUS ACTIVITY

START

STOP

CONTROLBYTE

ACK

WORDADDRESS (n)

CONTROLBYTE

START

DATA (n)

ACK

ACK

NO ACK

P

BUS ACTIVITYMASTER

SDA LINE

BUS ACTIVITY

STOPCONTROL

BYTE

ACK

NO ACK

DATA n DATA n + 1 DATA n + 2 DATA n + X

ACK

ACK

ACK


24LC08B/16B MODULES

9.0 SHIPPING METHODThe micromodules will be shipped to customers inclear plastic trays. Each tray holds 150 modules, andthe trays can be stacked in a manner similar to shippingdie in waffle packs. A tray drawing with dimensions isshown in Figure 9-1.

FIGURE 9-1: TRAY DIMENSIONS

SMART CARD MODULES14

.000

[35

5.60

]

12.0

40 [

305.

82]

9.374 [238.09]

0.50

0 [1

2.70

]

0.98

0 [2

4.89

] T

YP

0.86

0 [2

1.84

] T

YP.

0.61

7 [1

5.68

]

0.90

5 [2

2.99

]

R 0

.300

[7.

62]

TY

P

R 0

.270

[6.

86]

TY

P

8.145 [206.88]

ANTISTATIC


24LC08B/16B MODULES

FIGURE 9-2: MODULE DIMENSIONS

0.46

5 ±

0.00

2[1

1.80

± 0

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0.41

9 ±

0.00

2[1

0.63

± 0

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AA

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MA

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0.23

2 ±

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2[5

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50]

(4X

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0 [2

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2[3

.71

± 0.

05]

0.17

4 ±

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2[4

.42

± 0.

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0.20

9 ±

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.31

± 0.

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TY

P.

DE

VIC

E S

IDE

CO

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AC

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0.28

5 [7

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X

VIA

HO

LE

S (8

x)I.

D. ¯

0.0

26 [

0.66

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0.0

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LD

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ASH

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004

[0.1

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AX

.

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ASE

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7 [0

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mIN

mIN

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5 [0

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MA

X.

0.02

35 [

0.60

] M

AX

.


24LC08B/16B MODULES

24LC08B/16B MODULES PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Package: MT = Micromodules in trays

Temperature Range:

Blank = 0˚C to +70˚C

Device: 24LC08B 8K bit 2.5V I2C Serial EEPROM in ISO Module24LC16B 16K bit 2.5V I2C Serial EEPROM in ISO Module

24LC08B/16B — /MT

Data SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1. Your local Microchip sales office.2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.


Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation orwarranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or otherintellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with expresswritten approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarksof Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21224A-page 12

1997 Microchip Technology Inc.

M

All rights reserved. © 1997, Microchip Technology Incorporated, USA. 9/97 Printed on recycled paper.

AMERICAS

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Technical Support:

602 786-7627

Web:

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8/29/97

W

ORLDWIDE

S

ALES

& S

ERVICE

Circuito Integrado 24LC16 8K/16K2.5VSPIOBusSerial EEPROM - Manual Sonigate

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