Circuit-Oriented Treatment of Nonlinear Capacitances in Switched-Mode Power Supplies

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TPEL.2014.2313611, IEEE Transactions on Power Electronics

1

Circuit-Oriented Treatment of NonlinearCapacitances in Switched-Mode Power Supplies

Daniel Costinett, Member, IEEE, Dragan Maksimovic, Senior Member, IEEE,and Regan Zane, Senior Member, IEEE

Abstract—Nonlinear, voltage-dependent capacitances of powersemiconductor devices are capable of having significant impacton the operation of switched-mode power converters. Partic-ularly at high switching frequency, these nonlinearities playa significant role in determining switching times, losses, andconverter dynamics during switching transitions. In order toaccommodate the well established design and analysis techniquescommonly used for linear circuits, this paper examines thenonlinear voltage-dependence of switching device capacitancesand proposes a circuit-oriented analysis technique that allowsthe parasitic capacitances to be replaced with linear equivalents.The multitude of developed equivalents are verified through fullnonlinear simulation in both Matlab/Simulink and SPICE, aswell as through experimental results.

Index Terms—Parasitic capacitance, Nonlinear circuits, Equiv-alent circuits, Power semiconductor devices, Linearization tech-niques

I. INTRODUCTION

TRENDS in power converter design have led to increasedswitching frequencies, motivated by improvements in

achievable passive component size, control bandwidth, andEMI reduction. However, as switching frequencies approachthe feasible limits of current devices, previously negligiblecharacteristics of switching transitions become crucial com-ponents of the converter design and analysis. These switchingcharacteristics include, e.g. switching loss, time-duration ofthe switching transition, and converter dynamics during theswitching transition, all of which depend heavily on theintrinsic capacitances of the switching devices used in thecircuit.

The incorporation of nonlinear capacitances has been ad-dressed in various ways in prior studies. Most commonly,in power converter analysis, the effect of device capacitanceson circuit operation is largely ignored, with switching lossescalculated later for hard switched converters, or neglectedin ZVS converters so long as the appropriate device currentpolarity is present at the switching instant [2]–[4]. In eithercase, this leads to the assumption that the contribution ofswitching intervals to converter dynamics is sufficiently small

This work has been sponsored through the Colorado Power ElectronicsCenter (CoPEC) This work was presented at the IEEE Workshop on Controland Modeling of Power Electronics in 2012 [1]

Daniel Costinett is with the Department of Electrical Engineering andComputer Science, University of Tennessee, Knoxville, TN, 37996 USA e-mail: [email protected]

Dragan Maksimovic is with the Department of Electrical, Computer, andEnergy Engineering, University of Colorado, Boulder, CO, 80309 USA

Regan Zane is with the Department of Electrical and Computer Engineering,Utah State University, Logan, UT, 84322 USA

such that they may be approximated as instantaneous. Thisleads to significant discrepancy at high switching frequencyand low power, where the time required to discharge thecapacitor may be significant in comparison to the switchingperiod.

Works such as [5]–[8] have replaced the nonlinear capacitorwith a linear equivalent, but have rarely detailed or formal-ized the method by which the equivalent capacitance waschosen. Further, many studies have used a single equivalentlinear capacitance to model multiple characteristics of circuitbehavior. It is clear analytically and shown experimentally,e.g. in [9], that the nonlinearity cannot be modeled correctlyin terms of time, energy, and charge simultaneously by asingle linear capacitor. The voltage dependence of a nonlinearcapacitor can be modeled in its entirety in circuit simulators[10], [11]. Often, such simulations have been carried out with asimplified empirical fit to the MOSFET nonlinear capacitanceCoss, either through a simple polynomial [12] or a curve fitof the form

Coss(vds) =C0(

1 + vdsV0

)m , (1)

commonly with m = 1/2. Equation (1) is sufficiently accuratefor simple devices [13], [14], but errant for more complex,modern devices, including superjunction devices [15] as wellas varying structures of GaN [16]–[18] and SiC [19], [20]switching devices. Further, this analysis approach remainsoverly cumbersome for any hand analysis [11], [15], [21]. Solong as the output capacitor remains nonlinear, the circuit anal-ysis methods traditionally used in power electronics circuitscannot be applied directly. Thus, it is useful to create a clearand consistent framework for treating nonlinear capacitors inswitching power converzters by replacing them with linearequivalents. Such an approach has been attempted previouslyfor singular applications [10], [22]–[24], but has not beengeneralized to address the various parameters on which alinear equivalent may be based. Once an appropriate linearsubstitution has been made, traditional, well-developed linearcircuit analysis techniques can be employed to solve theoperating characteristics of power converters.

The nature of analysis including nonlinear capacitors isaddressed in Secion II, with hand analysis presented in Sec-tion III. Techniques for the simulation of nonlinear capaci-tances are reviewed in Section IV and experimental verificationis presented in Section V. Section VI concludes this work.



2

+ GS

D

+

depletion regionCds

Vgs≈0V

Vds>0VCgd

Cgs,p

Cgs,n

Cgs,m

n+ n+p+ n+ n+p+

n–

n+

Fig. 1. Origin of various parasitic capacitances shown in a cross sectionof a vertical power MOSFET in cutoff. Hatched regions indicate metalizedcontacts while shaded regions indicate electrically- insulating oxide layers.

II. CIRCUIT ANALYSIS WITH NONLINEAR CAPACITORS

Device capacitances are inherently present due to the un-derlying structure of semiconductor switching devices, andare generally deemed parasitic in nature. These include oxidecapacitances as well as P-N junction capacitances acrossthe depletion regions generated when reverse biased. Forconcision, analysis will focus on the nonlinear MOSFEToutput capacitance, with straightforward applications to diodejunction capacitance or any other voltage-dependent capacitor.The physical origin of the various parasitic capacitances isshown for a generic vertical power MOSFET in Fig. 1. Ofprimary concern for power converter design is the MOSFEToutput capacitance Coss = Cds+Cgd, which must be chargedor discharged by the converter power stage with each switchingaction. Note that both Cgd and Cds span the depletion region,and therefore will vary accordingly with its width, whichin turn increases with applied voltage Vds [25], [26]. Thevarying width of the capacitor formed between the drainand the equipotential gate and source nodes gives rise tothe nonlinear voltage dependence of the output capacitanceCoss = Coss(Vds). Additional complexities are introducedwhen advanced topologies, such as trench gate or superjunc-tion devices are considered, as well as alternate materials, e.g.as in wide bandgap devices.

In order to clarify equations throughout this paper, thevoltage-dependence will be expressed with notation

Coss(Vds) = Coss∣∣VDS

, (2)

where the vertical bar indicates the value of the capacitanceevaluated at the specified voltage.

To further demonstrate the variation in Coss among a varietyof devices, materials, and fabrication processes, a number ofexample curves are shown in Fig. 2. This data is extractedfrom device datasheets by visually fitting discrete points to thecurve, then interpolating to a higher resolution. If datasheets donot contain sufficient data, a simple impedance analyzer withDC bias is capable of producing the Coss curves, though moreprecise methods exist [20], [27]–[30]. It is desired to develop

0 50 100 150 2000

100

200

300

400

500

600

700

800

C oss [

pF]

VDS [V]

FDMC2610

EPC2012EPC1010

FQB19N20LIRF7450

CMF10120D

Fig. 2. Examples of differing Coss voltage dependencies for three silicondevices, two GaN devices, and one SiC device.

linear equivalents directly based on this data, so that circuitdesigners may compare the merits of many different devicesprior to circuit construction and testing. Further, because theshapes of the curves for differing devices vary widely, it isdesired to avoid empirical fit formulas such as that of (1), andinstead develop a method that remains valid for arbitrarilyshaped Coss-Vds data.

Given a curve containing Coss-Vds data, it must be under-stood in what sense the plots of Coss model the behavior of thedevice in a circuit. Coss can be understood as a small-signalequivalent capacitance, such that

ic = Coss

∣∣∣Vds

dvdsdt

(3)

holds true at any DC bias voltage VDS , assuming a small-signal perturbation vds VDS . This definition is derived fromthe method by which the Coss data in these plots is measured,which often consists of using an impedance analyzer or similarto measure the ids which results from an applied perturbationvds on top of a DC bias VDS . This definition can also beintegrated over a time interval dt to be viewed in terms ofcapacitor charge qc as

dqC = Coss

∣∣∣Vds

dvds, (4)

which is distinct from the incorrect large-signal interpretation,

qc 6= Coss

∣∣∣VDS

VDS , (5)

which neglects the voltage dependence of Coss in (3). Theemployed Coss data, by definition, considers only the behaviorof the capacitor in a small window surrounding a certain DCbias, and does not contain information on charge accumulationover the entire range 0 ≤ Vds ≤ VDS .

It is further important to consider how the nonlinear analysisdiffers from the traditional knowledge base developed forlinear capacitors. Due to the presence of a nonlinear element,traditional linear analysis techniques such as superposition will



3

Ceq

Coss Vds2

+

–

Vds2

ic2

+

–

Vds1

ic1

+–VA

Coss Vds1

+

–

Vsw

Fig. 3. Example circuit containing two identical nonlinear capacitors withvoltage-dependent capacitance Coss. Ceq is the AC-equivalent nonlinearcapacitor at the port defined by Vsw .

Vsw

Cap

acita

nce

0 VA

Coss Vds2

Coss Vds1

Ceq

Fig. 4. Plot of the nonlinear capacitances associated with Fig. 3.

not hold [31]. Charging and discharging behaviors of circuitscontaining nonlinear capacitances are not guaranteed to beidentical, though fundamental laws such as energy and chargeconservation continue to hold.

Where series/parallel combinations of nonlinear capacitorsare present, care must be taken to include the full non-linear voltage dependence when simplifying. In particular,simplification to AC-equivalent impedances, where DC bias isignored, requires careful consideration of the voltage presenton each individual capacitor. As an example, consider thecircuit of Fig. 3. When calculating the equivalent impedanceseen from the port defined by Vsw, it is useful to reduce to theAC-equivalent capacitance Ceq = (Coss

∣∣Vds1

)||(Coss∣∣Vds2

).However, due to the voltage dependence, even if both capac-itors are identical, they exhibit different capacitances due totheir differing DC voltage bias. Given that Vds2 = VA−Vds1,the resulting nonlinear switched-node capacitance Ceq can becalculated as shown in Fig. 4. However, as in the linear case,this simplification is an AC equivalent only; the informationcontained in the DC bias is lost. Thus, this simplification isuseful for calculating impedances, but would not contain thecorrect information for total energy or charge storage in thetwo nonlinear capacitors.

The circuit of Fig. 3 appears often in power converteranalysis; the two nonlinear capacitors can be seen to rep-resent a MOSFET half bridge, or if they are allowed totake different values, may represent a diode and MOSFETbridge. In particular for high frequency power conversion, the

characteristics of the transition of Vsw between 0 and VAare of critical importance to converter design. In either case,the established solutions developed under the assumption ofpurely linear circuits do not apply. In the following section, thegeneral nature of nonlinear capacitances is addressed directly,and linear equivalent capacitors are developed for which thetraditional analysis methods and tools can once again beused to obtain correct predictions of capacitor energy storage,hard switched loss, and resonant transition time, among otherparameters.

III. DEVELOPMENT OF LINEAR EQUIVALENTCAPACITANCES

In order to develop equivalent linear capacitors, analysismust focus on parameters of interest on which to base theequivalence. Because of their fundamental nonlinearity, aconstant-valued, linear capacitance will generally only be ableto correctly model a single parameter for a given voltagetransition. First, independent of the application circuit, boththe energy and charge required to move the capacitancebetween two voltages should be addressed. Because both areconservative, only the defining curve of the nonlinear capacitorvoltage dependence is needed to obtain the storage at a givenvoltage. Thus, linear equivalent capacitors which store thesame amount of charge or energy at a given voltage can bedeveloped for the nonlinear capacitor of Fig. 5, independentof application circuit.

Vc

ic

Cx Vc

Fig. 5. Nonlinear capacitor used in derivation of energy and charge equiva-lents, independent of application circuit.

Using the small-signal definition of Cx∣∣Vc

from (3), it hasbeen shown previously that the total energy in a nonlinearcapacitor is given by integrating the product of Cx and Vcacross the voltage range e.g. from 0 to VC [24]

Ec =

∫ VC

0

vCx∣∣vdv. (6)

Note that this total energy Ec depends on DC bias conditionsand can therefore not be calculated on a AC-equivalent non-linear capacitor. The energy can then be used to find a linearcapacitance value that contains the same amount of energy atVC by considering the solution to the energy stored in someequivalent capacitor Ceq,E , which is linear, constant-valued

Ec =1

2Ceq,EVC

2. (7)

By combining (6) and (7) an expression for the energy-equivalent linear capacitor can be obtained

Ceq,E =2

VC2

∫ VC

0

vCx∣∣vdv, (8)



4

where Ceq,E and Cx store the same amount of energy at aDC voltage VC .

A similar process may be used to find the total charge

Qc =

∫ VC

0

Cx∣∣vdv, (9)

and charge-equivalent linear capacitance,

Ceq,Q =1

VC

∫ VC

0

Cx∣∣vdv, (10)

which will have the same amount of stored charge at VC asthe nonlinear capacitor Cx. As seen from (10), this value issimply the average of the Cx curve with respect to the voltagerange.

Beyond these two, all other parameters of interest arespecific to the application circuit. To remain as general aspossible, the circuit of Fig. 6 is used, and a transition isconsidered throughout this section which results in Vc movingfrom Vc = 0 to Vc = VA. The capacitance Cx

∣∣Vx

is a general-ized nonlinear capacitance and may represent Coss or Csw,where appropriate, or any other capacitance-versus-voltagecurve of interest. In these voltage transitions, the energy stored,supplied, or dissipated in the remaining components of thecircuit is also of interest, as well as the time taken for thevoltage transition, which informs optimal dead time selectionin a converter.

Vc

ig

Vg

Z

Cx Vc

VA

t0

Fig. 6. Generalized equivalent circuit to a voltage transition involvinga nonlinear capacitor. A charging transition is considered, where voltagedynamics during the transition depend on the impedance Z.

Next, consider the energy sourced by a supply in charginga nonlinear capacitance. This energy can be solved indepen-dently of the series element impedance. The total energysupplied, Es, from Vg is the integral of its instantaneous powerover the time taken to charge the capacitance, Cx

Es =

∫t

Vgig(t)dt, (11)

where ig = ic and therefore the definition from (3) can beused to transfer the variable of integration and obtain

Es =

∫ VA

0

VgCx∣∣vdv, (12)

which, given the previous definition of Ceq,Q, can be reducedto

Es = VgCeq,QVA, (13)

with VA the final value of Vc in the transition being considered.Comparing to the linear case, it is apparent that the charge-

equivalent capacitance is also the correct value to use when

solving for supplied energy. This follows intuition, as theenergy supplied by the constant voltage source should bedetermined entirely by the charge supplied to Cx and thevoltage at which it is deposited. Additionally, combining (13)and (7), the energy processed by the impedance Z can befound as

EZ = Es − Ec =

(Ceq,Q

VgVA− 1

2Ceq,E

)VA

2, (14)

and an equivalent capacitance Ceq,Z can be given for theenergy processed by the impedance

Ceq,Z = 2Ceq,QVgVA− Ceq,E . (15)

This capacitance has slightly different meaning depending onwhether Z is inductive or resistive (if Z is capacitive, it canbe trivially combined as an offset in the nonlinear capacitancedefinition). If a resonant transition is considered where Z ispurely inductive, Ceq,Z may be used to model the inductorbehavior during, for example, a zero-voltage switching transi-tion of a half-bridge. If the two devices constituting the halfbridge are paralleled as detailed in Fig. 4, Cx = Ceq and theresulting Ceq,Z is a capacitor which results in the same changein stored energy in the inductor during the transition fromVc = 0 to Vc = VA. If instead a hard-switching transition isconsidered, Z is resistive, and Cx is the output capacitance ofa single device, Coss. In this case, Ceq,Z is the linear capacitorwhich results in the same amount of energy dissipated on theresistance during the voltage transition.

Finally, it desired to develop equivalent capacitors whichcan accurately model the duration of the voltage transition inthe case of either resistive or inductive Z. Such a value isuseful in determining the optimal duration of half bridge deadtimes for hard-switched or resonant transitions, respectively.In the resistive case, under the assumption that Vg > VA sothat the the transition can be completed in finite time, the rise-time of the R − C circuit containing a nonlinear capacitanceis

tr,nlin = R

∫ VA

0

Cx∣∣v

Vg − vdv , (16)

which is compared to the well-known solution for the linearcapacitance case

tr,lin = RClin ln

(Vg

Vg − VA

), (17)

to obtain the equivalent linear capacitance for which rise timesare equal

Ceq,tr =1

ln(

Vg

Vg−VA

) ∫ VA

0

Cx∣∣v

Vg − vdv . (18)

Note that a similar approach is taken to determine a fall-timeequivalent, but the resulting value is not, in general, the same.

If Z is inductive, the time tzvs taken to move voltage Vcfrom 0 to VA is fundamentally given through the solution to asystem of nonlinear differential equations. For Fig. 6, the twodifferential equations describing circuit operation are

ig = Cx∣∣Vc

dVcdt

, (19a)



5

Vg − Vc = Ldigdt. (19b)

These equations can be combined, taking care to rememberthat Cx is now time-varying, and thus cannot be pulled outof the time derivative. Instead, the chain rule for derivativesis used to obtain

LCx∣∣Vc

d2Vcdt2

+ L

(dVcdt

)2d

dVc

(Cx∣∣Vc

)+ Vc = Vg . (20)

The numerical solution for the ZVS interval duration is then,for the nonlinear circuit

tZV S =

∫ VA

0

Cx∣∣vdv√

I2L0 + 2L

∫ v0Cx∣∣vy

(Vg − vy) dvy, (21)

where vy is a dummy notational variable used for integrationwithin the nested integral that occurs due to the second-ordernature of the circuit. This equation may be applied to obtainnumerical solutions in a program such as Matlab. As an ex-ample, if cx is an array of capacitances with correspondinglyindexed voltage array vx, and r is an array with the indexesinto both which correspond to the range 0 <vx< VA, (21)can be solved by a single command

tzvs = trapz(vx(r),cx(r)./sqrt(Il0ˆ2+2/L*...cumtrapz(vx(r),cx(r).*(Vg-vx(r)))));

The value of tzvs can then be combined back into thesolution of Fig. 6 with a time-equivalent linear capacitanceCeq,tzvs; for the circuit at hand with inductive impedance, thissolution is given by the integral

tZV S = Ceq,tzvs

∫ VA

0

dv√I2L0 +

Ceq,tzvs

L (2Vgv − v2). (22)

By plugging in the value for tZV S solved previously, a nu-merical solution for Ceq,tzvs can be obtained through iterativeanalysis.

Comparing (21) and (22), one can note that at L → ∞,Ceq,tzvs → Ceq,Q. This follows intuition; in the case of aconstant current source, the time taken to traverse any voltagerange will be determined only by the total charge. Withfinite values of L considered, Ceq,tzvs may differ somewhatfrom Ceq,Q. Particularly in the case of converters employingsmall-valued, AC, resonant or soft-switching inductors, or inconverters operating at or near their ZVS boundary where thechange in inductor current during the ZVS interval is large.Otherwise, Ceq,Q will often remain a good approximation insituations where it is not feasible to calculate Ceq,tzvs.

With these developed linear capacitors, all parameters ofinterest in a power converter can be solved for. Slight modi-fications of integral limits and defining functions of Cx areneeded to accommodate different circuit configurations ortransition types (e.g. partial soft-switching), but the process ofsolving linear equivalents remains the same. In the followingsection, the processes of simulating nonlinear capacitors inboth Matlab/Simulink and LTSpice are detailed. Simulationresults are used to compare the dynamics of the LC circuitof Fig. 6 containing a nonlinear device capacitance as well aseach of the four linear equivalents developed in this section.

IV. NONLINEAR DEVICE SIMULATION

To confirm the analysis of the previous section, simulationsof circuits containing a nonlinear capacitance are carried outin MathWorks Simulink and LTSpice. Results are includedhere for both tools to illustrate how nonlinear capacitorscan be incorporated into both mathematical and circuit-basedsimulation tools. It is again assumed that the defining voltage-vs-capacitance curves are known, and the numerical data isavailable with appropriate resolution.

A. Simulation in LTSpice

Within the SPICE environment, the effective behavior of anonlinear, voltage-dependent capacitor may be implementedas shown in Fig. 7. A nonlinear capacitor subcircuit is shownin Fig. 7(a) using a behavioral current source whose valueis determined by the time-derivative of the capacitor voltage,multiplied by the capacitance value at the current capacitorvoltage. In order to determine the capacitor voltage at any timeinstant, the table function is used with a .func directiveand the complete array of coma-delimited (vds,Coss) pairs ispasted into the netlist, or LTspice GUI. A behavioral voltagesource then outputs a voltage equal to the capacitance valueassociated with the current operating conditions, which is bothused by the previously described current source, and selectedas an output port to allow observation of the capacitancevalue. This subcircuit can then be given a symbol and usedin the same manner as any normal, linear capacitor in circuitsimulations. Fig. 7(b) shows this element, X1, in a circuitsimulation designed to compare the rise times of the nonlinearcapacitor and its linear equivalent, Ceq,tr.

B. Simulation in Simulink

The implementation of an identical circuit simulation whichcompares the resistively charged rise times of nonlinear and alinear equivalent capacitors is given for Simulink in Fig. 8(a).A one-dimensional lookup table is used in the nonlinear caseto supply the capacitance based on the current terminal voltageof the device.

As circuit complexity increases, and additional circuit statesare included, it is often useful to develop state space descrip-tions of the circuit behavior of the form Kx = Ax+Bu. In thecase of switching power converters, the matrix A and vectorB are potentially time-varying within a switching period dueto the variation in switch states, while K is the diagonalmatrix containing only inductances, mutual inductances, andcapacitances. Often, the matrix K is eliminated to yieldx = A′x + B′u, where A′ = K−1A and B′ = K−1B.However, such an approach results in state space equationsin which A′ and B′ are potentially functions of the nonlinearcapacitance. It is crucial to the speed of the simulation thatthe matrices are not re-calculated at each timestep [10]. Inorder to facilitate the incorporation of a nonlinear capacitancewithout forcing the recalculation of matrices A and B at eachtimestep, K is retained in the state space definition and theintegration of x is carried out explicitly so that the effective Kmultiplication can be implemented with a number of gains for



6

(a)

(b)

Fig. 7. Circuits showing an example implementation of a nonlinear capacitoras a subcircuit (a) and implementation in a schematic (b). Note that thetable has been truncated to show only the first two datapoints of a nonlinearcapacitance with e.g. 850 pF value at 0 V bias in (a). For increased utility,the time-varying capacitance value is output as a voltage proportional to thecapacitance (in pF) through the CapVal port. The resulting subcircuit is givena symbol and implemented in the red dashed box in (b).

the linear reactive elements and look-up table multiplicationsfor the nonlinear.

An example switching converter with one voltage-dependentcapacitor and one linear inductor is shown in Fig. 8(b); aMatlab function is used to perform the Ax+Bu calculation toeasily allow the matrices to be varied between multiple (pre-calculated) values according to the current time-determinedswitch state of the circuit. The matrix K is implemented as asingle 1/L gain and a 1-D lookup table for Coss

∣∣Vds

C. Simulation Results

Among the developed linear equivalents, only Ceq,tr andCeq,tzvs are mutually exclusive. Thus, the rise time equivalentcapacitance is evaluated independently. Simulations are carriedout for a single IPB60R385CP 600 V Infineon CoolMOSdevice [32], starting from Vds = 0 and charged by a seriesVg = 600 V source and 100 kΩ resistor. The linear equivalentCeq,tr is based as normal on the rise time as Vds moves from0 to 80% VDSS , which is VA = 480 V.

In order to simulate the device output capacitance, datasheetplots of the full nonlinear Coss characteristic are used to visu-ally extract the data of Table I, which is then logarithmically

(a)

(b)

Fig. 8. Example Simulink implementations of nonlinear capacitors in anR − C circuit (a) and a time-varying state space description of a switchingpower converter (b).

interpreted to obtain Coss − Vds data at 10 mV resolutionwhich is used in the simulation. To verify proper extractionand interpolation, this data is plotted on top of the datasheetplots for Coss and Eoss in Fig. 9, showing good agreement.

The IPB60R385CP device was chosen here because Infi-neon CoolMOS devices commonly contain more extensivedatasheet reporting of nonlinear capacitance characteristics.This includes the additional Eoss plot shown in Fig. 9(b) whichis used as a second point of verification for data extraction andtwo datasheet-reported values for linear equivalents, Co(er)and Co(tr), which are the energy- and time-related “effectiveoutput capacitances” for VDS from 0 to VA = 480 V, which



7

TABLE IEXTRACTED IPB60R385CP NONLINEAR CAPACITANCE DATAPOINTS

VDS [V] 0 5 10 40 50 75 100 150 200 300 400 500 600Coss [pF] 5500 2500 1900 550 95 50 38 30 29 27 27 25 24

are reported to be 36 and 96 pF, respectively. Based on theextracted data, Ceq,E and Ceq,tr are calculated as in equations(8) and (18) as 36.35 and 96.99 pF.

However, this agreement is not always consistent among de-vices from different manufacturers. Most often, when includedin the datasheet, Co(tr) is defined as “... a fixed capacitancethat gives the same charging time as Coss while VDS is risingfrom 0 to 80% VDSS” [32]. However, this definition doesnot take into account the method by which the capacitance ischarged. If charged by constant current, constant resistance, orresonantly, the equivalent capacitance will differ, and the valuereported in the device datasheet therefore depends on the testsetup used to determine it. For example, among 600 V devices,the Infineon IPx60R450E6 and Vishay SiHU7N60E datasheetslist values for Co(tr) which are the charge-equivalent ca-pacitance, rather than Co,tr, indicating either implicitly orexplicitly that a constant-current charging setup was used.While these values are not incorrect, the varying definitionsof equivalent capacitances among device datasheets indicatescaution should be used whenever these values are used inanalysis.

Simulations of the nonlinear capacitance and the linearequivalent, Ceq,tr, are shown in Fig. 10, in both LTSpice andSimulink. In each case, the voltage across the capacitors risesfrom 0 to 480 V in tr = 15.6µsec. However, the waveformsof the linear and nonlinear capacitors are radically different intheir dynamics while approaching this point.

To simulate the remaining equivalent capacitances in aresonant transition, a 200 V FDMC2610 silicon MOSFET isused as an example device with curves for Coss

∣∣Vds

measuredexplicitly up to 40 V using an Agilent 4284A PrecisionLCR Meter, and extrapolated from the datasheet thereafter.The resulting data for Coss is given in Table II. Again,logarithmic interpolation is used to obtain increased resolutionfor simulation and analysis.

The circuit simulated is that of Fig. 6 with Z implementedas an inductor of magnitude L = 12.5 µH and initial currentIl0 = 0 A. The circuit is allowed to resonate with vds1 startingat an initial voltage of zero volts and resonating until reachingVg = VA = 200 V. The calculated values for the linearequivalents in this circuit are

Ceq,Q = 70.5 pF, Ceq,E = 56.4 pF,

Ceq,tzvs = 64.1 pF Ceq,Z = 84.5 pF.

Though not relevant to the resonant circuit, Ceq,tr = 65.7 pFis calculated for the same voltage range if resistive chargingwere instead employed. None of these values approach thenominal value for Coss quoted in the datasheet, which is 41 pFat Vds = 100 V, and only Ceq,E is near the maximum listed as55 pF. This is, however, purely coincidental; a single Coss −

0 50 100 150 200 250 300 350 400 450 5000

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

C [p

F]

VDS [V]

(a)

0 100 200 300 400 500 6000

1

2

3

4

5

6

VDS [V]

E oss [

µJ]

(b)

Fig. 9. Overlays of visually-extracted data for the nonlinear capacitance (red,dashed) on screenshots of datasheet plots of a IPB60R385CP device. Thesame data is compared to both the Coss and Eoss plots.

Vds datapoint cannot possibly capture the full behavior of thenonlinear characteristic. In general, a single value of Coss

∣∣VDS

from a table in a device datasheet is not intended to modelany behavior other than the small-signal capacitance at DCbias VDS .

Simultaneously, the four appropriate equivalent linear ca-pacitances are simulated under identical conditions. Simulationresults are shown in Fig. 11. The voltage vds, current il,capacitor energy Etot, and capacitor charge Qtot are shownwith respect to time in individual plots. Each circuit is allowedto resonate for precisely the amount of time required to reachvds = VA. In each plot, a horizontal or vertical dashed black



8

TABLE IIMEASURED AND EXTRACTED FDMC2610 NONLINEAR CAPACITANCE DATAPOINTS

VDS [V] 0 0.5 1 2 5 10 15 20 25 30 35 40 50 100 150 200Coss [pF] 580 464 385.5 265.9 168.3 125.5 106.7 95.4 87.7 82 77.6 74 70 55 53 51

Capacitance values are measured in-circuit for the converter detailed in the experimental results of Section V resulting in slightly higher values than reportedin the datasheet.

TABLE IIIEXTRACTED NONLINEAR CAPACITANCE DATAPOINTS FOR CSD16325 AND RSX501LA IN PARALLEL

VDS [V] 0 1 2 3 4 5 6 7 8 9 10 15Coss + CD [nF] 8 5.66 4.76 4.2 3.8 3.57 3.34 3.12 2.91 2.75 2.64 2.20

0 10 20 30 40 500

20

40

60

80

100

120

140

160

180

200

time [nsec]

CossCeq,ECeq,QCeq,tzvsCeq,Z

V ds [V

]

(a)

20 25 30 35 40 45 50

0.3

0.35

0.4

0.45

0.5

time [nsec]

I l [A

]

(b)

30 35 40 45 500.2

0.4

0.6

0.8

1

1.2

1.4

1.6

time [nsec]

E tot [

μJ]

(c)

30 35 40 45 507

8

9

10

11

12

13

14

15

16

17

time [nsec]

Qto

t [nC

]

(d)

Fig. 11. Simulations of the nonlinear capacitance, Coss and the four linear equivalents developed here. The horizontal or vertical dashed black line indicatesthe correct value of the respective simulation parameter which a linear equivalent should match. In each case, only the single, appropriate linear equivalentleads to a correct approximation i.e. (a) Ceq,tzvs, (b) Ceq,Z , (c) Ceq,E , and (d) Ceq,Q.



9

Cap

acito

rVo

ltage

[V]

time [sec](a)

Cap

acito

rVo

ltage

[V]

time [sec](b)

Fig. 10. Simulation results in LTSpice (a) and Simulink (b) showing thecomparison between the voltage waveform of a IPB60R385CP as it is chargedby a series 600 V source and 100 kΩ resistor. Waveform labels indicatewhether the full nonlinear relationship or its linear equivalent is simulated ineach case.

line shows the correct value of the parameter being plotted, asdetermined by simulation of the full nonlinear characteristic.There is a clear necessity to choose the appropriate capacitancewhen solving for a certain aspect of the resonant circuit:Ceq,tzvs for resonant time, Ceq,Z for final inductor current,Ceq,E for energy stored in the capacitor, and Ceq,Q forits charge; also, no one value of capacitance is capable ofsimultaneously modeling all of the characteristics of interestin the circuit.

V. APPLICATION AND EXPERIMENTAL VERIFICATION

It is desired to use the developed linear-equivalent capacitorsto aid in the analysis of the phase-shifted dual active bridge(DAB) converter, whose schematic and typical operatingwaveforms are shown in Fig. 12. A previously developedsilicon-transistor prototype is used; operation is tested up to110 W with a 150-to-12 V step-down conversion ratio andmatched transformer turns ratio nt = 0.08 [33]. Primarydevices Q1−Q4 are implemented with Fairchild FDMC2610MOSFETs, while secondary switches Q5 − Q8 consist ofTexas Instruments CSD16325Q5 NexFETs in parallel withRohm RSX501LA Schottky barrier diodes. All devices are

switched at fs = 1 MHz to emphasize the impact of resonantintervals. To begin, it is of interest to know the amount

+

–VoCo

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

il

Ll 1:nt

Vg

a

b

c

d

(a)

(b)

Fig. 12. (a) Schematic of DAB converter and (b) operating waveforms.MOSFET equivalent capacitances, Coss are shown explicitly.

of losses incurred if the high-voltage primary side devicesare not zero-voltage switched. For this, the inductor Ll isdisconnected, and the primary devices are switched separately,with dead times to prevent shoot-through current. Because thetank is disconnected, il(t) = 0, and the losses in the systemare dominated by the capacitive switching losses of the fourprimary side devices. The expected losses from hard switchingare divided into two categories for each half bridge transition:losses from shorting out device capacitances, and losses fromthe RC-type charging of the opposite device in each half-bridge. With this in mind, both Ceq,E and Ceq,Z are calculatedfor an individual device to obtain the total losses due to hardswitching of device capacitances; considering all four devicesand switching frequency fs this is

Ploss = 4

(1

2Ceq,EVg

2fs

)+ 4

(1

2Ceq,ZVg

2fs

), (23)

which can be reduced via (15) to

Ploss = 4Ceq,QVg2fs. (24)

Interestingly, the total hard-switched loss depends only on thecharge-equivalent capacitance of the individual switches, andnot the energy equivalent as intuition may suggest. The sameanalysis can be applied to obtain the losses due to the hard-switching of the secondary switches,

P ′loss = 4C ′eq,QVo2fs , (25)



10

where the prime (′) indicates parameters referred the the sec-ondary side; C ′eq,Q is the charge-equivalent capacitance of theIRF6713 and RSX501LA in parallel. The voltage dependenceof the nonlinear capacitance of these two devices in parallelis taken directly from plots in their respective datasheets andgiven in Table III

Next, the ZVS boundary and soft-switching time of theprimary devices are evaluated by reducing the output powerof the converter until ZVS of primary side devices is achievedjust as the inductor current reaches 0 A. A single bulkcapacitance is considered between nodes a and b in Fig. 12which consists of the series/parallel combination of all fournonlinear capacitances on the primary full bridge. During theswitching transition, the voltage on this equivalent capacitanceis moved from −150 V to +150 V. From the previous stateplane analysis, it is known that the ZVS condition on thenormalized inductor current Jpk at the start of the resonance,and normalized total primary resonant time α, are given by

Jpk > 2, (26)

α =π

2− cos−1

(2

Jpk

). (27)

Here one can observe that standard state-plane analysis ben-efits from the development of linear capacitors i.e. becausethe capacitance involved is used to perform normalization, itsnonlinearity is not present in the normalized equations. Tra-ditional state plane analysis can be used without modificationto solve characteristics of circuit operation; one only needs toselect the correct linear equivalent capacitor to denormalizethe results. Because (26) is a condition on inductor energy,Ceq,Z is used, while Ceq,tzvs is used to denormalize time in(27) to obtain the actual values for peak current at the start ofthe resonance, Ipk and resonant interval duration tα

Ipk > 2Vg

√Ceq,ZLl

, (28)

tα =√LlCeq,tzvs

[π

2− cos−1

(2VgIpk

√Ll

Ceq,tzvs

)], (29)

where a transition between zero and VA = Vg = 150 Vis considered for each of the half-bridge capacitances, as inFig. 4. The linear-equivalent predictions for hard-switchingloss, ZVS condition, and resonant time of the primary-sideFDMC2610 devices are compared to experimental results inTable IV, showing good agreement. Also included as referenceare the analytical estimates one would obtain if the samecalculations were made using the approximation that Coss islinear, with magnitude equal to that quoted on the datasheet forthe device (41 pF at 100 V), and with magnitude extrapolatedfrom the datasheet plot for Coss at Vg (25 pF at 150 V). Theseapproximations are shown to be highly inaccurate, indicatinga clear need for the use of appropriate linear equivalents.

Finally, the hard switching loss of the low-voltage, highcurrent secondary is tested experimentally, again with theinductor and transformer disconnected to isolate capacitivelosses. The DC output voltage is set from an external supplyand is varied across the range 0 < Vo < 12 V. Capacitive

0 2 4 6 8 10 120

0.5

1

1.5

2

2.5

P ′ loss [W

]

Reference 1Reference 2

PredictedExperimental

Vo [V]

Fig. 13. Low-voltage secondary switch losses under hard-switching con-ditions. Experimental (circles) results are compared to predictions using theproposed analysis (from equation (25)) and to two references. Reference curve1 assumes a constant capacitance equal to the value of Coss listed in thedatasheet of CSD16325 (at 12.5 V) and the capacitance of the RSX501LAevaluated at the same voltage; reference 2 assumes a linear capacitance takenfrom the datasheet plots evaluated at Vo.

switching loss is predicted using (25), with Ceq,Q evaluatedat each output voltage. Results are given in Fig. 13, showingexcellent accuracy of the proposed analysis at a variety ofvoltages. References curves are again included for comparison,to illustrate how assuming a fixed Coss based on the valueprovided for a specific voltage yields erroneous switching lossestimates.

VI. CONCLUSION

The examination of in-circuit effects of nonlinearities inthe output capacitance, Coss, of switching devices in powerelectronic circuits is often neglected or treated in a simplifiedbut potentially inaccurate manner. Use of a linear substitutionto Coss based on a datasheet value at a specific voltagecan result in significant errors in circuit calculations. Thenonlinearity cannot be modeled correctly in terms of time,energy, and charge simultaneously by a single linear capacitor.Instead, this paper shows how an appropriate linear equivalentmust be determined to correctly model a specific charac-teristic of circuit operation. In particular, as the boundariesof frequency, efficiency, and power density are pushed, thissignificant nonlinearity needs to be carefully addressed.

To achieve both simplicity and accuracy of circuit analysis,linear equivalent capacitances to the nonlinear Coss can beused to remove the need for cumbersome nonlinear analysisthrough an algorithmic approach. After linearization, tradi-tional circuit analysis techniques can be applied, and theanalysis remains accurate for the parameter used as the basisfor determining the linear equivalent capacitance. Simulationsand experiments show how the process results in highlyaccurate predictions for power electronic circuits under bothhard-switched and soft-switched conditions.

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TABLE IVEXPERIMENTAL RESULTS FOR DUAL ACTIVE BRIDGE PRIMARY

Parameter CapacitorsUsed

ValuePredicted Experimental Reference 1† Reference 2‡

Hard Switched Primary Loss Ploss Ceq,Q 6.9 W 7.05 W 3.69 W 2.25 WMinimum ZVS Current Ipk Ceq,Z 819 mA 850 mA 579 mA 452 mASoft-Switched Time tα Ceq,tzvs 40.68 ns 39 ns 16.9 ns 9.7 ns

† Values obtained if FDMC2610 datasheet listed value for Coss (at 100 V) is used in calculation‡ Values obtained if FDMC2610 datasheet plot is used to obtain Coss at Vg = 150 V

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12

Daniel Costinett (S’10-M’13) received the B.S.,M.S., and Ph.D. degrees in electrical engineeringfrom the University of Colorado, Boulder, conclud-ing in 2013. In 2012, he assisted with research andcourse development as an instructor at Utah StateUniversity. He is currently an Assistant Professorin the Department of Electrical Engineering andComputer Science at the University of Tennessee,Knoxville. His research interests include resonantand soft switching power converter design, highefficiency power supplies, mixed-signal integrated

circuit design, implantable devices, and electric vehicles.Dr. Costinett is the Co-Director of Education and Diversity for the National

Science Foundation/Department of Energy Research Center for Ultra-wide-area Resilient Electric Energy Transmission Networks (CURENT). He is alsoa Research Engineer with the Power Electronics and Electric MachineryResearch Center, Oak Ridge National Laboratory. He currently serves asAssociate Editor for IEEE Transactions on Industrial Applications

Regan Zane (SM’07) received the Ph.D. degree inelectrical engineering from the University of Col-orado, Boulder, in 1999. He is currently a USTARProfessor in the Department of Electrical and Com-puter Engineering at Utah State University in Logan,UT. Prior to joining USU, Dr. Zane was a facultymember at the University of Colorado-Boulder, Col-orado Power Electronics Center, CoPEC, 2001 to2012, and research engineer at GE Global ResearchCenter, Niskayuna, NY, 1999 - 2001. He has recentand ongoing projects in bi-directional converters for

dc and ac micro-grids, high step-down power converters for dc distributionsystems such as high efficiency data centers, improved battery managementsystems (BMS) for electric vehicles, LED drivers for lighting systems andlow power energy harvesting for wireless sensors.

Dr. Zane received the NSF Career Award in 2004 for his work in energyefficient lighting systems, the 2005 IEEE Microwave Best Paper Prize forhis work on recycling microwave energy, the 2007 and 2009 IEEE PowerElectronics Society Transactions Prize Letter Awards for his work on modelingof digital control of power converters and the 2008 IEEE Power ElectronicsSociety Richard M. Bass Outstanding Young Power Electronics EngineerAward. He received the 2006 Inventor of the Year, 2006 Provost FacultyAchievement, 2008 John and Mercedes Peebles Innovation in Teaching, andthe 2011 Holland Teaching Awards from the University of Colorado. Hecurrently serves as Associate Editor for the IEEE Transactions on PowerElectronics, Letters, and as the Publicity Chair for the IEEE Power ElectronicsSociety.

Dragan Maksimovic (M’89-SM’04) received theB.S. and M.S. degrees in electrical engineering fromthe University of Belgrade, Serbia (Yugoslavia), in1984 and 1986, respectively, and the Ph.D. de-gree from the California Institute of Technology,Pasadena, in 1989.

From 1989 to 1992, he was with the Univer-sity of Belgrade. Since 1992, he has been withthe Department of Electrical, Computer and EnergyEngineering, University of Colorado, Boulder, wherehe is currently a Professor and Director of the

Colorado Power Electronics Center (CoPEC). His current research interestsinclude mixed-signal integrated circuit design for control of power electronics,digital control techniques, as well as energy efficiency and renewable energyapplications of power electronics.

Prof. Maksimovic has co-authored over 250 publications and the textbookFundamentals of Power Electronics. He received the 1997 NSF CAREERAward, the IEEE PELS Transactions Prize Paper Award in 1997, the IEEEPELS Prize Letter Awards in 2009 and 2010, the University of ColoradoInventor of the Year Award in 2006, the IEEE PELS Modeling and ControlTechnical Achievement Award for 2012, the Holland Excellence in TeachingAwards in 2004 and 2011, the Charles Hutchinson Memorial Teaching Awardfor 2012, and the 2013 Boulder Faculty Assembly Excellence in TeachingAward. He currently serves as an Associated Editor for IEEE Transactions onPower Electronics and as an Editor for the IEEE Journal of Emerging andSelected Topics in Power Electronics.

Circuit-Oriented Treatment of Nonlinear Capacitances in Switched-Mode Power Supplies

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