Circuit Analysis for Main Board

7/31/2019 Circuit Analysis for Main Board

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Circuit Analysis for Hi3560Q



第一版

2011-05-21

1、 ` Main Board Power Supply

C

W

2

5

1

0

0

N

J P W 1

C O N 9 ( 2 . 5 4 m m )

1234567

89

L W 4F B 1 2 0 R 3 A

L W 7F B 1 2 0 R 3 A

5 V

2 4 V _ I N

C W 1

1 0 0 N

C W 2 8

1 0 0 N

Power Supply Interface

1 2 V

L W 1F B 1 2 0 R 3 A3 V 3

+C W E 1 4

1 0 0 U F / 1 6 V

+C W E 1 8

4 7 U F / 5 0 V

L W 2F B 1 2 0 R 3 A

+C W E 1 5

N C / 1 0 U F / 1 6 V

C

W

2

1

1

0

0

N

C

W

2

2

1

0

0

N



Definition for JPW1 Power Supply Interface：1、GND 2、3.3V 3、3V3 4、GND 5、5V8 6、5V8 7、GND 8、15V

9 、30V

5V For Dac and video buffer

5 V 9

+ C W E

1 0 0 U

M C U _ P W R C T L

5 V 0

+

C W E 6

2 2 0 U F / 1 6 V

C W 6

1 0 0 N

C W 9

1 0 0 N

C W 2 3

1 0 0 N

R W 1 7

0 R

R W 1 8N C

U 2 5C E 6 2 1 8 E 5 0 M

V I N1

G

N D

2

C E3

N C4

V O U

T5

5V for USB



U 2 4

C E 6 2 1 5 A 5 0 G L

V I N1

G

N

D

2

G

N

D

4

V O U T3

5 V 0 _ U S B

+C W E 8

2 2 0 U / 1 6 V

C W 1 1

1 0 0 N

R W 2 13 0 0 R

5 V 9

C W 1 3

1 0 0 N

1v25 for demo



C A 5

1 0 0 N

C

A

4

1

0

0

N

+C A E 3

4

7

U

F

/ 1

6

V

G NG N D

U A 17 8 L 0 9

V I N1

V O U

T3

G N D

2

9 V1 2 V 0

1 2 V T o 9 V

L A 3N C / 5 R 1

2v5/1v25 for SDRAM



C W 2 9

1 0 0 N

L W 5

F B 1 2 0 R 3 A

C W 1 8

N C / 1 0 U F / 6 . 3 V

C W 3 0

N C / 1 0 U F / 6 . 3 V

U 1 0

R T 9 0 0 5 A P S P

B P1

V I N 12

V I N 23

V C N T L4

V R E F E N5V O U T

26G N D7V O U T

18

S I N K9

1 V 2 5

C W 1 0

1 0 0 N

+C P E 2

2 2 0 U F / 1 6 V

+C W E 4

2 2 0 U F / 1 6

R W 3

1 0 K _ 1 %

C W 1 7

1 0 U F / 6 . 3 V

C W 1 6

1 0 0 N

R W 41 0 K _ 1 %

C W 1 2

1 0 0 N

+C W E 5

1 0 0 U F / 1 6 V

C W 1 5

1 0 0 N

3 V 3

2 V 5

C F 3

1 0 0 N



13V/18V for LNB

+C E T 6

4 7 U F / 5 0 V

C T 1N C

U T 1L M 3 1 7

V I N3

V O U T2 T A B4

A D J

1

R T 3 2

3 R

R T 1 9

1 0 K

R T 2 2

3 0 0 R

R T 1 8

8 K 2

R T 1 0

1 2 K

2 4 V

R T 2 1

9 K 1

R T 7

1 0 KQ T 22 S C 1 8 1 5

1

2

3

Q T 1

2 S C 1 8 1 5

1

2

3

C T 4 1

1 0 0 N

V _ S E L

R T 3 7

1 0 K

R T 3 8

1 K 2

C TR T 3 9

1 0 0 R

C T 4 5

1 0 N

1

D i s e q c _ O U TC T 4 6

1 0 0 N

L N B _ E N

C T 4 3

1 0 0 N

C T 4 4

3 3 0 P F

R T 4 0

4 K 7

F B 3 P T C 6 0 V 0 . 3 A

1 2

R T 4 14 K 7

V D D 0 _ 3 V 3



3V3 for tuner

5 V 0

C 2 4

1 0 0 N F

C 2 5

1 0 0 N F

+C W E 2 1

1 0 U F / 1 0 V

R W 1 12 0 0 R

R W 1 3

1 2 0 R

U W 5A Z 1 1 1 7 - A D J

1

A D J2

V O U T 1 V I N3

4V O U T 2

C W 4

1 0 U F / .

3 V 3 _ T U N E R



C 2 31 0 0 N F

Q 72 N 2 9 0 7

C 2 1

1 0 0 N F

L B 1 6 N C / F B 1 2 0 R 3 A

3 V 3

R W 1 4

2 K 2

R W 54 K 7

R W 21 0 K

Q W 6

2 S C 1 8 1 5B1

E2

C3

M C U _ P W R C T L1 , 7

+C W E 1 2

1 0 U F / 2 5 V

M C U _ P W R C T L

1 2 V 1 2 V 0

P O W E R F O R A U D I O

R W 1 51 0 K



8 m A ( M A X )

R W 2 04 K 7

2 4 V _ C O N T R O L

L B 2 0 N C / F B 1 2 0 R 3 A

Q W 7 A O 3 4 0 1 A

G

1

S2

D3

R W 1 92 4 K

R W 1 2

2 K 2

Q W 2

2 S C 1 8 1 5B1

E

2

C

3

C 3 7

1 0 0 N F

R 2 4 31 0 0 K

2 4 V _ C O N T R O L1

2 4 V2 4 V _ I N



C 6

1 0 0 N F

L B 1 8

N C / F B 1 2 0 R 3 A

Q W 4

U T 2 3 0 1

G

1

S2

D3

R W 9

2 K 2

R W 1 61 K

Q W 1

2 S C 1 8 1 5B1

E2

C3

R 1 4

7 5 R

C 3 5

2 2 0 N F

R 2 4 1

1 5 0 K

R 2 4 2

1 K

M C U _ P W R C T L1 , 7

3 V 3

3 V 3 _ M O S

M C U _ P W R C T L

Main Point: Test whether the voltage for power supply interface is established after opening STB.

Exclude the power board failure and then test the board to see if the voltage is normally established. Notice that just as standby control pin is high

level , the voltage can be established.



二、 Tuner and Demodulator

40mA

145mA

R T 4 0 R

R T 5 0 R

V D D 0 _ 3 V 3

R T 9

1 K

R T 1 1

2 K C T 3 7

1 0 N

S C L T

C T 4 2

1 0 N

3 V 3 _ T U N E R

S D A T

C T 3 5

N C

C T 3 6

N C

R T 3 14 7 R

R T 3 6 N C

L T 4F B 1 2 0 R 3 A

L T 5F B 1 2 0 R 3 A

R T 2 4 3 3 R

R T 2 3 3 3 R

C T 3 9

2 0 P F

C T 4 0

2 0 P F

R T 1 2

2 K 2

R T 81 K

500mA

+

C

E

T

5

4

7

0

U

F

/ 1

0

V

C

T

3

3

1

0

N

A A G C

RF-IN

RF- O UT

AB

T 1T

U

N

- S

H

A

R

P

-7

3

0

6

B 1 B1

B 1 A2

B 4 ( 3 V 3 )3

B 2 ( 3 V 3 )4

Q O U T5

I O U T6

A G C7

S D A8

S C L9

C L K - O U T1 0

G

N

D

1

1

G

N

D

1

2

G

N

D

1

3

G

N

D

1

4

Q T 3

2 N 5 5 5 12

1

3

I P

V D D 0 _ 3 V 3

R T 3 33 9 0 R

R T 30 R

Q P

L N B B

C T 3 8N C

C

T

3

4

1

0

N

+

C

E

T

1

4

7

0

U

F

/ 1

0

V

C T 3 2

1 0 0 P F

C T 4 7

1 0 0 P F

L N B A

D 2

1 N 4 0 0 7

12



C

T

4

9 1

0

0

N

R T 2 7

1 M

R T 2 53 3 R

Read

Value of RT35, RT2

andRT34, RT6

C T 1 0

2 0 P F

Write

C T 1 1

2 0 P F

V D D 0 _ 3 V 3

T S I _ C L K

A A G C

T U N E R _ R S T

T S I _ D A T [ 0 . .1

D E M O _ L O C K1

T S I _ S Y N C

R T 1 74 K 7

T S I _ D A T [ 0 . . 7 ]

R T 1 64 K 7

V D D 0 _ 3 V 3

R N T 14 7 R X 4

1234

8765

R N T 2 4 7 R X 41234

8765

I 2 C _ A D D R 1

T S I _ E R 1

V

D

D

A

_

3

V

3

T S I _ V A L

C T 4

1 0 0 N

V D D 0 _ 3 V 3

C T 5

2 P F

C T 6

2 P F

R N T 34 7 R X 4

1234

8765

C T 7

1 0 0 N

C T 9

1 0 0 N

C T 8

1 0 0 N

T S I _ E R

Chip address of M88DS3002

T S I _ V A L 1

I 2 C _ A D D R 0

I 2 C _ A D D R 1

D E M O _ L O C K

T S I _ S Y N C 1

Operation address

3 V 3 _ M O S

T S I _ C L K 1

V _ S E L

V D D 0 _ 3 V 3

+

C

E

T

2

1

0

0

U

F

/ 1

6

V S C L _ T U N E R

I 2 C _ A D D R 0

C T 1 3

N C

S D A T S D A _ T U N E R

I 2 C _ A D D R 1

L T 1

F B 1 2 0 R 3 A

S C L _ T U N E R1 , 8

V

D

D

0

_

3

V

3

+

C

E T

3

2

2

0

U

F

/ 1

6

V

V D D A _ 3 V 33 V 3 _ M O S

L T 2

F B 1 2 0 R 3 A C

T

1

9 1

0

0

N

C

T 2

0 1

0

0

N

C

T 2

1 1

0

0

N

S D A _ T U N E R1 , 8

C

T

1

4 1

0

0

N

D i s e q c _ O U T C

T

1

5

1

0

0

N

U T 2

M 8 8 D S 3 0 0 2

G N D A1

X T A L _ I N2X T A L _ O U T

3

V D D A4

G N D A5

I P6

I N7

V D D A8

G N D A9

Q N1 0

Q P1 1

N C1 2

V D D D1 3

V C C1 4

V C C1 5

N C1 6

A

A

G

C

1

7

S

C

L

T

1

8

S

D

A

T

1

9

V

C

C

2

0

S

D

A

2

1

S

C

L

2

2

V

D

D

D

2

3

A

D

D

R

_

S

E

L

1

2

4

A

D

D

R

_

S

E

L

0

2

5

V

C

C

2

6

V

S

E

L

2

7

D

I S

E

Q

C

_

I N

2

8

D

I S

E

Q

C

2

9

V

C

C

3

0

C

K

X

T

A

L

_

2

7

3

1

R

E

S

E

T

3

2

V C C3 3M _ D 03 4M _ D 13 5M _ D 23 6M _ D 33 7

V C C3 8

M _ D 43 9M _ D 54 0V D D D4 1M _ D 64 2M _ D 74 3M _ E R R4 4M _ V A L4 5

V C C4 6M _ S Y N C4 7

M _ C L K4 8 G

N

D

4

9

O

L

F

5

0

C

K

X

T

A

L

_

1

3 5

1

L

N

B

_

E

N

5

2

V

C

C

5

3

L

O

C

K

5

4

N

C

5

5

N

C

5

6

N

C

5

7

N

C

5

8

V

D

D

D

5

9

N

C

6

0

N

C

6

1

V

C

C

6

2

G

P

O

6

3

N

C

6

4

G

N

D

6

5

RT35=NCRT2=0R

C

T

1

6 1

0

0

N

_

C

T

1

7 1

0

0

N

_

RT34=NCRT6=0R

RT35=0RRT2=NC

RT34=NCRT6=0R

RT35=0RRT2=NC

RT34=0RRT6=NC

RT35=NCRT2=0R

RT34=0RRT6=NC

3 V 3

T S I _ D A T 7

V

D

D

1

_

1

V

2

5

T S I _ D A T 6

Y T 12 7 M H Z

C T 2

3 0 P F

C T 3

3 0 P F

C T 1 21 0 0 N

R T 2 0

1 0 K

D 1 H

T S I _ D A T 5

D 4 H

D 2 H

D 0 H

D 7 H

D 5 H

D 3 H

R T 1

0 R

D 6 H

R T 3 5N C / 0 R

V

D

D

1

_

1

V

2

5

I P

R T 3 4N C / 0 R

T S I _ D A T 4

R T 2

0 R

R T 6

0 R

T U N E R _ R S T1

Q P

L N B _ E N

T S I _ D A T 2T S I _ D A T 3

T S I _ D A T 0T S I _ D A T 1

R T 1 42 K 2

R T 1 32 K 2

V

D

D

0

_

3

V

3

R T 2 63 3 R

C T 1 8

4 7 P F

C T 4 8

4 7 P F

S C L T



The above is schematic diagram for tuner, T1 for SHARP-7306, and with the CPU function through the IIC bus-

mastering UT2-M88DS3002, then through the UT2-M88DS3002 IIC control satellite signals change into the

input IF signal output. After demodulating by UT2-M88DS3002, digital TS stream signal would be output finally.

No matter CPU’s control or Tuner’s feedback are all come true by IIC（SCL，SDA）. However, the data which

CPU decode picture & voice is controlled by TS（ TSIN_DATA0－7）. So, if TS stream is abnormal, which would

not affect the testing for signal quality and strength of channel searching. But if IIC cable is abnormal, signal

quality and strength can’t be tested and even not decode for corrected TS stream.

Main Point:

Judge if Tuner and demodulated IC work normal:

1) Whether there is 4M CLK signal output from10th pin of T1?

2) Whether there is normal signal output from 5th and 6th pin of T1?

3) Whether there is waveform with 27M from YT1 crystal oscillation?

4) Whether there is normal AGC signal output from 17th pin of UT2-M88DS3002?

5) Whether there is low PWL 3V3 from 32th pin of UT2-M88DS3002?



6) Whether there is normal output from TS stream（ TSIN_DATA0－7,CLK, SYNC,VAL）of UT2-M88DS3002?

三、Memory

E B I _ A B 6

E B I _ D B 1 0

E B I _ A B 5

3 V 3

E B I _ D B 9

E B I _ A B 4

E B I _ D B 8

E B I _ A B 3

E B I _ D B 7

E B I _ A B 2

E B I _ D B 6

E B I _ A B 1

E B I _ D B 5

E B I _ A B 0

E B I _ D B 4E B I _ D B 3

/ W E _ E B I

E B I _ D B 2

/ O E _ E B I

E B I _ D B 1

/ C E _ F L A S H

E B I _ A B 2 1

E B I _ D B 0

E B I _ A B 2 0

C F 6

1 0 0 P F

E B I _ A B 1 9E B I _ A B 1 8

/ R S T _ S Y S1 , 8

W P

E B I _ A B 1 7E B I _ A B 1 6E B I _ A B 1 5

E B I _ D B 1 5

E B I _ A B 1 4E B I _ A B 1 3

E B I _ A B 1 2

/ R S T _ S Y S

E B I _ A B 1 1

B Y T E

U F 2S 2 9 G L 0 6 4 N 9 0 T F I 0 4 0

A 1 51

A 1 42

A 1 33

A 1 24

A 1 15

A 1 06

A 97

A 88

A 1 99 A 2 0

1 0

W E #1 1

R E S E T #1 2

A 2 11 3

W P # / A C C1 4

R Y / B Y #

1 5

A 1 81 6

A 1 71 7

A 71 8

A 61 9

A 52 0

A 42 1

A 32 2

A 22 3

A 1

2 4

A 02 5

C E #2 6 G N D 1

2 7O E #

2 8

D Q 02 9

D Q 83 0

D Q 13 1

D Q 93 2

D Q 23 3

D Q 1 03 4

D Q 33 5

D Q 1 13 6

V C C3 7

D Q 43 8

D Q 1 23 9

D Q 54 0

D Q 1 34 1

D Q 64 2

D Q 1 44 3

D Q 74 4

D Q 1 4 / A - 14 5

G N D 24 6

B Y T E #4 7

A 1 64 8

E B I _ D B 1 4

E B I _ A B 1 0

E B I _ D B 1 3

E B I _ A B 9E B I _ A B 8

E B I _ D B 1 2

E B I _ A B 7

E B I _ D B 1 1



D

D

R

_ W

E 5

DDR_DQ[0:15]

D D

R

_

B

A

1 5

DDR_BA1

D D R _ A D D R [ 0 : 1 2 ]5

1 V 2 5

D

D

R

_ D

M

1 5

1 V 2 5

D

D

R

_ C

K

N

0 5

2 V 5

D

D

R

_ C

K

P

0 5

D D R _ D Q S 15 2 V 5D D R _ D Q S 05

D

D

R

_ D

M

0 5

1 V 2 52 V 5

DDR_DM1

DDR_CKN0

D

D

R

_ R

A

S 5

DDR_DM0

DDR_CKP0

D

D

R

_

C

S 5

D D R _ D Q :5

D D

R

_

B

A

0 5

D

D

R

_

C

K

E 5

DDR_CASDDR_WE

DDR_CKE

U D 1

E D D 5 1 1 6 A G T A - 5 B - E

V D D _ 01

D Q 02

V D D Q _ 13

D Q 14D Q 25

V S S Q _ 16

D Q 37D Q 48

V D D Q _ 29

D Q 51 0D Q 61 1

V S S Q _ 21 2

D Q 71 3

N C _ 01 4

V D D Q _ 31 5

L D Q S1 6

N C _ 11 7

V D D _ 11 8

D N U _ 01 9

L D M2 0

^ W E2 1

^ C A S2 2

^ R A S2 3

^ C S2 4

N C _ 22 5

B A 02 6

B A 12 7

A 1 0 / A P2 8

A 02 9

A 13 0

A 23 1

A 33 2

V D D _ 23 3

V S S _ 03 4

A 43 5

A 53 6

A 63 7

A 73 8

A 83 9

A 94 0

A 1 14 1

A 1 24 2

N C _ 34 3

C K E4 4 C K4 5 ^ C K4 6 U D M

4 7

V S S _ 14 8

V R E F4 9

D N U _ 15 0

U D Q S5 1

V S S Q _ 35 2

N C _ 45 3

D Q 85 4

V D D Q _ 45 5

D Q 95 6D Q 1 05 7

V S S Q _ 45 8

D Q 1 15 9D Q 1 26 0

V D D Q _ 56 1

D Q 1 36 2D Q 1 46 3

V S S Q _ 56 4

D Q 1 56 5

V S S _ 26 6

R D 1 7

1 K _ 1 %

R D 1 81 K _ 1 %

C

D

4

1

0

0

N

R D 1 61 0 0 R

R D 6 02 2 R

R D 4 1 0 0 R

R D 2 1 0 0 RR D 3 1 0 0 R

R D 6 1 0 0 R

R D 5 1 0 0 RR D 1 1 0 0 R

R

D

2 3

1

0

0

R

C

D

9

1

0

0

N

C

D

1

0

1

0

0

N

R D 6 2 2 2 R

C

D

1

3

1

0

0

N

C

D

1

1

1

0

0

N

R D 6 1 2 2 R

C

D

1 2

1

0

0

N

C

D

8

1

0

0

N

C

D

1 4

1

0

0

N

C

D

7

1

0

0

N

C

D

6

1

0

0

N

C

D

5

1

0

0

N

C

D

3

1

0

0

N

R

D

3

7

1

0

0

R

R

D

3 8

1

0

0

R

R

D

3 6

1

0

0

R

R

D

3

5

1

0

0

R

R

D

3 3

1

0

0

R

R

D

3 4

1

0

0

R

R

D

3

2

1

0

0

R

R

D

3 1

1

0

0

R

R

D

3

0

1

0

0

R

R

D

2 9

1

0

0

R

R

D

2

7

1

0

0

R

R

D

2 8

1

0

0

R

R

D

2 6

1

0

0

R

R

D

2

5

1

0

0

R

R

D

2 4

1

0

0

R

R D 5 92 2 RR D 5 82 2 RR D 5 72 2 RR D 5 62 2 RR D 5 52 2 RR D 5 42 2 RR D 5 32 2 RR D 5 22 2 RR D 5 12 2 RR D 5 02 2 RR D 4 92 2 RR D 4 82 2 RR D 4 72 2 RR D 4 62 2 RR D 4 52 2 R

C

D

2

1

0

0

N

C

D

1

5

1

0

0

N

+ C

D

1

1

0

U

F

/ 6

. 3

V

R

D

1

9

1

0

0

R

C

D

1

7

1

0

0

N

R

D

2

0

1

0

0

R

R

D

2

1

1

0

0

R

R

D

1

5

1

0

0

R

R

D

1

4

1

0

0

R

R

D

1 3

1

0

0

R

R

D

1

1

1

0

0

R

R

D

1

2

1

0

0

R

R

D

9

1

0

0

R

R

D

1

0

1

0

0

R

R

D

8

1

0

0

R

R

D

7

1

0

0

R

C

D

1

6

1

0

0

N

R

D

2 2

1

0

0

R

R D 3 91 0 0 RR D 4 01 0 0 R

DDR_RASR D 4 11 0 0 RR D 4 21 0 0 R

R D 4 31 0 0 RR D 4 41 0 0 R

DDR_CS

DDR_DQS0DDR_DQS1

DDR_DQ2

DDR_DQ5DDR_DQ4DDR_DQ3

DDR_DQ7DDR_DQ6



DDR_DQ15DDR_DQ14

DDR_DQ0DDR_DQ1

DDR_ADDR[0:12]

D

D

R

_

C

A

S 5

D D R

0

DDR_BA0

C D 1 8

1 0 u F / 6 . 3 V

R D 6 3N C / 3 0 0 R

DDR_ADDR4

DDR_ADDR1DDR_ADDR0

DDR_ADDR8DDR_ADDR7

DDR_ADDR12

DDR_ADDR9

DDR_ADDR5

DDR_ADDR11DDR_ADDR10

DDR_ADDR6

DDR_ADDR3DDR_ADDR2



Above refer to partial circuit for FLASH [UF2] and DDR [UD1].

The main function of Flash is stock software code which storage system needed and conserve all code after

power-down. Therefore, it requests flash could complete restoration before CPU reset and then waiting for CPU

reading. In fact, STB upgrading process is also updating the FLASH program code, which need to make sure do

not power-off during upgrading to avoid system halted when code updating.

The main function of DDR is stock procedure and program temporarily in system operation. When power-off, all

data will be disappeared. Their work are two differential clock signal CLK, currently used in the 133MHz

frequency, a single peak is about 700mV around the clock, the oscilloscope measurement of peak value is

about 3.3V. If the rate is too low, it would cause the system run unstable, causing crashes, mosaic, and slow

response to the problem.

LMI_VREF is the reference voltage of DDR, the design voltage is 1.25V. If the voltage ripple is too large, it will

cause the system run unstable.



四、Reset Circuit and Surge

TCM809U S 1

C Y T 8 0 9 - 2 . 6 3 V

G

N

D

1

R

E

S

E

T

2

V

C

C

3

C S 6

1 0 0 N

R S 2 51 0 0 K

R S 1 4

5 1 R

/RST_SYS/ R S T _ S Y S1 , 5

3 V 3

S D A _ T U N E RS C L _ T U N E R

Addr:0x1010000

C

B

5

1

0

0

N

3 V 3

R S 5N C / 4 K 7

R S 1 3

1 K

U S 2

2 4 C 6 4

A 01

A 12

A 23

G N D4

S D A5S C L6W P7V C C8



C V B S / R G B

4/3 OR 16/9

S D A _ R F

M U T E 3M U T E

S D A _ R F1 1

S C L _ R FS C L _ R F1 1

P W E N _ S I M

/ R S T _ E T H

P W E N _ S I M1 0

/ R S T _ E T H

T U N E R _ R S T

C 5

1 0 0 P F

T U N E R _ R S T9

G P I O

3 V 3

3 V 3 _ D A C

3 V 3

T X D 1 _ M I I

D A T _ S I M1 0

/ R S T _ S I M1 0

R X D 0 _ M I IRXD0_MII

RXD3_MIIRXD2_MIIRXD1_MII

T S I _ D A T [ 0 . . 7 ]9

D E C _ S I M1 0C L K _ S I M1 0

T X D 1 _ M I I

T S I _ S Y N C9C V B S 1 1V D A C _ B1 1V D A C _ G1 1

T X D 2 _ M I I

T X D 3 _ M I I

V D A C _ R1 1

T S I _ V A L9T S I _ C L K9

U T X D 08U R X D 08

T C K _ C P U1 0

T D O _ C P U1 0

T M S _ C P U1 0

T D I _ C P U1 0

L R C K _ I I S3D A T A _ I I S3

M C L K _ D A C3B C L K _ I I S3

S D A _ T U N E R8 , 9

/ T R S T N _ C P U1 0

S P D I F 3S C L _ T U N E R8 , 9

V B U S _ U S B1 0M D I O _ M I IM D C _ M I I

D M _ U S B1 0

T X D 0 _ M I ID P _ U S B1 0

T X C K _ M I IT X E N _ M I I

R X D V _ M I I

V B U S _ E N1 0

R X C K _ M I IR X E R _ M I I

C L K _ L E D8D A T A _ L E D8

M C U _ P W R C T L6 , 7

C R S _ M I I F P - S T B 8T S I _ E R 9

C O L _ M I I

I R _ I N8

R X D 2 _ M I IR X D 1 _ M I I

R

1 1

N

C

/ 1 K

M I S C ( 2 ) I n t e r f a c e 3 o f 3

U 2 B

H I 3 5 6 0 Q _ P W R

T S I D A T 02

T S I D A T 13

T S I D A T 25

T S I D A T 36

T S I D A T 47

T S I D A T 58

T S I D A T 69

T S I D A T 71 0

T S I S Y N C1 1

T S I C K1 3

T S I V L D1 4

T S I E R R / G P I O 1 91 6

U R X D 0 / G P I O 2 01 7

U T X D 0 / G P I O 2 11 8

U S I M _ D A T A2 0

^ U S I M _ P W R E N2 1

U S I M _ R E S E T2 2

U S I M _ C L K2 4

U S I M _ D E T2 6

G P I O 02 7

G P I O 12 8

G P I O 22 9

O T G I D3 1

O T G V B U S3 2

O T G D P3 6

O T G D M3 8

O T G R E X T4 0O T G D R V V B U S

4 3

^ W D G R S T4 5

S D A4 6

S C L4 7

T D O4 9

T D I5 0

T C K5 1

T M S5 3

^ T R S T N5 4

F U N S E L5 6

^ R S T N5 7

X I N5 9

X O U T6 0

D A C S V M6 7

D A C B7 0

D A C G7 3

D A C R7 6

D A R E X T7 9

D A C O M P8 0

D A V R E F I N8 1

D A V R E F O U T8 2

S I O B X C K / G P I O 2 58 8

S I O B D I / G P I O 2 28 9

S I O B D O / P W M 19 0

S I O B X F S / G P I O 2 49 1S I O B R F S / G P I O 2 39 2

S I O X F S9 4

S I O D I / G P I O 4 29 5

S I O D O9 6

S I O X C K9 7

S I O M C L K / G P I O 2 79 9

S I O R F S / G P I O 2 61 0 0

S P D I F O U T / G P I O 2 81 0 1

M D C K1 0 2

M D I O1 0 4

T X D 01 0 5

T X D 11 0 6

T X D 21 0 7

T X D 31 0 8T X E N / G P I O 3 0

1 0 9

T X C K / G P I O 3 11 1 1

R X D 0 / G P I O 3 21 1 3

R X D 1 / G P I O 3 31 1 5

R X D 2 / G P I O 3 41 1 6

R X D 3 / G P I O 3 51 1 7

R X D V / G P I O 3 61 1 8

R X E R R / G P I O 3 71 1 9

R X C K / G P I O 3 81 2 1

C R S / G P I O 3 91 2 2

C O L / G P I O 4 01 2 3

G P I O 1 41 2 4

T S I P W M / G P I O 4 31 2 6

G P I O 1 51 2 7

I R I N / G P I O 4 41 2 9

G P I O 1 81 6 1

R X D 3 _ M I I

R 1 2 1 0 0 R

R 9 0 R

R 8 0 R

R

4

N

C

/ 4 K

7

R

3

3 .

4 8 K

_ 1 %

24V_CONTROL

+ C

E

1

1 0 0 U

F /

1 6 V

C

2

1 0 N

R 1 2 7 0 R

C

1

1 0 N

R 7 4 K 7 _ 1

X 1

2 7 M H z

C 4 2 7 P F

C 3 2 7 P F

R

2

1 M

R

5

4 K

7

R

6

4 k 7

/RST_SYS

TSI_ERFP-STB

DATA_LEDCLK_LED

MCU_PWRCTL

VBUS_EN

DP_USBDM_USB

ID_USBVBUS_USB

BCLK_IISDATA_IIS

CRS_MII

SCL_TUNER

TMS_CPU/TRSTN_CPU

SDA_TUNER

UTXD0

TDI_CPU

VDAC_B

VDAC_RURXD0

VDAC_G

/RST_SIM

SPDIF

IR_IN

TXCK_MII

COL_MII

RXCK_MII

CVBS

RXER_MII

MDIO_MII

RXDV_MII

TXEN_MII

LRCK_IISTCK_CPU

TDO_CPU

CLK_SIM

DAT_SIM

MCLK_DAC

DEC_SIMTSI_SYNCTSI_CLKTSI_VAL

MDC_MII

G P I O _ L O C K

TSI_DAT0

TSI_DAT[0..7]

TSI_DAT2TSI_DAT1

TSI_DAT5TSI_DAT4TSI_DAT3

TXD0_MII

TSI_DAT7TSI_DAT6

TXD2_MII

0:Normal Mode1:Test Mode

USB 2.0 Host Only

Mode Selection:

/ R S T _ S Y S5 , 8

TXD3_MII



The above picture shows the EEPROM, reset circuit, HyperTerminal, and part of the schematic system clock.

Reset is precondition for the entire start system. Normally, when power supply is in 200-300mS, 2nd foot of

Us1 / RST_SYS signal would go from low to high, which began CPU reset. US2's EEPROM chip is a IIC bus

devices, controlled by the CPU, when saving some systems need to power down some small amount of

information, such as channel information, system settings, and a small amount of data.

X1 is the system clock signal . Through this pin in C3 and the voltage 2.5V to produce oscillations, which make

27M sine wave signals in the C4 pin.

五、Video and Audio

V D A C _ GV D A C _ B

C V 2 8

1 0 0 N

B

U 2 1 F M S 6 1 4 3

I N 11

I N 22

I N 33

V C C4

G N D5

O U T 36

O U T 27O U T 18

+

C 2 3 5

1 0 0 u F / 1 6 V

GR _ O U

5 V 0

G _ O U

L V 5

F B 1 2 0 R 3 A

B _ O U

V D A C _ R R

+C 2 3 2 2 2 0 u F / 1 6 V

+C 2 3 4 2 2 0 u F / 1 6 V

R 2 2 5 7 5 R _ 1 %

R 2 2 6 7 5 R _ 1 %

R 2 5 1 7 5 R _ 1 %

+

C 2 3 1 2 2 0 u F / 1 6 V

5 V _ A V



U 2 0 F M S 6 1 4 3

I N 11

I N 22

I N 33

V C C4

G N D5O U T 36O U T 27O U T 18 C V B S _ O U T

5 V _ A V

R 2 2 8

N C / 7 5 R _ 1 %

U 2 6

N C / S G M 9 1 1 3

I N1

G N D2

V C C3

G N D4

O U T5

C V B S

C V B S _ T V

R 2 2 7

7 5 R _ 1 % +

C 2 3 3

2 2 0 u F / 1 6 V

C V 2 4

1 0 0 N

C V B S _ O U T 1

5 V _ A V



E 5E S D

E 9E S D

C V 3 0

N C / 1 N F

R _ O U T

C N 1

R C A 6 _

L 18

R 15

G 17

R 19

R 26

G 24

V 12

V 23

G 31

E 1 2E S D

C V 3 2

N C / 1 0 0 P F E 1 5E S D

C V 3 3

N C / 1 0 0 P F

C V 3 4

N C / 1 0 0 P F

E 1 6E S D

C V B S _ O U T 1

C V 2 3

N C / 1 N F

L _ C H3

R _ C H3

B _ O U TE 1 0E S D

C V 3 1

N C / 1 0 0 P F

G _ O U T



Above is schematic diagram for audio & video

Audio:

CPU directly output IIS digital audio signals, and UA2-CS4334 change IIS signals into analog signals then which

be amplified by 4558. Circuit resistance on the RA11 and RA1 are the feedback impedance, which together

with input impedance ratio determines the size of magnification, and also determines the size of set-top box

output volume.

Video:

R7-4K7 & R1-270R resistors are configured video DAC reference current on CPU configuration. With 4 video

DAC, HI3560Q could be respectively configured in different combinations. DAC output converted analog video

signals. CVBS and YPBPR signals will be amplified and output by FM6143 .

六、Spare Parts reference data



From left to right: operational amplifier LM833/4558 , voltage stablizing unit LM/AZ1117-ADJ, EEPROM

AT24C64

Circuit Analysis for Main Board

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Transcript of Circuit Analysis for Main Board