CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit

Generation Linus Witschen,

Tobias Wiersema,Hassan Ghasemzadeh Mohammadi,

Muhammad Awais,Marco Platzner

Computer Engineering GroupPaderborn University

Outline

• Motivation• Related Work

– Classification– Requirements & Goals

• The CIRCA Framework– Concept– Current State: Implementation & Exemplary Results

• Conclusion & Outlook

2

Motivation

• Approximate Computing (AC) on circuit level– AC exploits gap between required and provided computational accuracy– Trade off computational accuracy against area, delay, or energy

consumption

• Large approximation space for complex Circuits– Large amount of possible approximation candidates– Effects of approximations become non-intuitive

• Demand for an automated approximation process

3

Related Work: Classification

4

Category SASIMI[1]

SALSA[2]

AIG RW[3]

ABACUS[4]

SCALS[5]

ASLAN[6]

Circuit Type Comb. Comb. Comb. Comb. + seq.(?) Comb. Seq.

Input Model Gate netlist Gate netlist Gate netlist/AIG Behavioral HDL Gate/LUT netlist Structural HDL + annotations

Error Model Error bound Quality function Error bound #Iterations Error bound Quality Evaluation Circuit

Search Method Heuristic(hill climbing) - Heuristic

(greedy)Heuristic(greedy)

Heuristic (Metropolis-Hastings)

Heuristic(hill climbing)

AC Technique Substitute-and-Simplify Approx. don’t care AIG re-writing AST transforms Logic transforms Precision scaling

Quality Assurance

Testing By construction Formal verification Testing Testing Formal

verification

Output Approx. circuit Approx. circuit Approx. circuit Pareto front Approx. circuit Approx. circuit

Output Model Gate netlist Gate netlist Gate netlist (AIG) Behavioral HDL Gate/LUT netlist Structural HDL

Target Technology

Std. cell Std. cell Technology Independent Std. cell Std. cell/LUT-

based Std. cell

Publicly Available

- - Yes Yes - -

Input

Generation/synthesis

Output

Availability

Related Work: Classification

5

Category SASIMI[1]

SALSA[2]

AIG RW[3]

ABACUS[4]

SCALS[5]

ASLAN[6]

Circuit Type Comb. Comb. Comb. Comb. + seq.(?) Comb. Seq.

Input Model Gate netlist Gate netlist Gate netlist/AIG Behavioral HDL Gate/LUT netlist Structural HDL + annotations

Error Model Error bound Quality function Error bound #Iterations Error bound Quality Evaluation Circuit

Search Method Heuristic(hill climbing) - Heuristic

(greedy)Heuristic(greedy)

Heuristic (Metropolis-Hastings)

Heuristic(hill climbing)

AC Technique Substitute-and-Simplify Approx. don’t care AIG re-writing AST transforms Logic transforms Precision scaling

Quality Assurance

Testing By construction Formal verification Testing Testing Formal

verification

Output Approx. circuit Approx. circuit Approx. circuit Pareto front Approx. circuit Approx. circuit

Output Model Gate netlist Gate netlist Gate netlist (AIG) Behavioral HDL Gate/LUT netlist Structural HDL

Target Technology

Std. cell Std. cell Technology Independent Std. cell Std. cell/LUT-

based Std. cell

Publicly Available

- - Yes Yes - -

Related Work: Requirements & Goals

• Requirements to a framework– Compatible �

– Open-source O– General �

– Extensible �

– Modular �

• Goal: Develop framework which satisfies these requirements

6

CIRCA: Concept

7

• Pre-process input data

• Perform– Search– Quality assurance– Approximations– Estimate circuit

parameters

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.vPareto Frontier

AnnotationsTest Vector Set

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

CircuitConfigs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

Quality Assurance Approximation

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

Expand

Evaluate

SelectCircuit

Configs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

ErrorPower

DelayArea

Quality Assurance

TestingVerification

Approximation

etc.AIG rewrite

Prec. scaling

CIRCA: Concept

8

Orig.A

Error: 0B

Error: 0

Orig.A

Error: 0B

Error: 0

Cfg. 1A

Error: 1B

Error: 0

Cfg. 2A

Error: 0B

Error: 1

Orig.A

Error: 0B

Error: 0

Cfg. 1A

Error: 1B

Error: 0

Cfg. 2A

Error: 0B

Error: 1

Cfg. 3A

Error: 2B

Error: 0

Cfg. 4A

Error: 1B

Error: 1

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

Expand

Evaluate

SelectCircuit

Configs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

ErrorPower

DelayArea

Quality Assurance

TestingVerification

Approximation

etc.AIG rewrite

Prec. scaling

2 Candidates

x xx

xx

Error

Area

10 510 5

CIRCA: Concept

9

• Input & Output stage ensure compatibility

• User configures the approximation process

• Independent blocks– Modular– Extensible– General

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.vPareto Frontier

AnnotationsTest Vector Set

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

CircuitConfigs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

Quality Assurance Approximation

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

Expand

Evaluate

SelectCircuit

Configs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

ErrorPower

DelayArea

Quality Assurance

TestingVerification

Approximation

etc.AIG rewrite

Prec. scaling

CIRCA: Current State

10

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.vPareto Frontier

AnnotationsTest Vector Set

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

CircuitConfigs.

New CircuitConfigs.

CUT

Pareto Frontier

AnnotationsTest Vector Set

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

Quality Assurance Approximation

QUAES stage

Input Stage

Orig.Circuit

*.vConfig. File

Output Stage

Approx.Circuit

*.v

Search Space Exploration

CircuitConfigs.

New CircuitConfigs.

CUT

Annotations

Approx.Component

Library

pass Y/N

CircuitConfigs.

CircuitParameters

Estimation

Quality Assurance Approximation

Hill climbing

AIG rewritePrec. scaling

Area

Verification

• Hill climbing search– Heuristic considers

hardware area of candidates individually

• Two approximation techniques– Precision scaling– AIG re-writing

• Formal verification assures quality– Inductive solver used

from ABC [7]– Support for

combinational and sequential circuits

CIRCA: Exemplary Results

11

Circuit Name Description #4-LUTs #Candidatesbutterfly [8] Operation used in FFT 7221 8fir_gen [8] FIR filter 4-tap 5438 7fir_pipe_16 [9] FIR filter 16-tap 8768 23rgb2ycbcr [10] Color-space transformation 4527 5ternary_s_n [10] Adder tree 1483 4weight_calc Industrial scale 1872 4

• ABC used to estimate area• 10 runs per benchmark circuit

– Varied worst-case error from 0.25% to 2.0%– Use precision scaling & AIG RW– Report for hardware area & runtime of CIRCA

CIRCA: Exemplary Results

12

0.8

0.9

1.0

1.178:56:03 79:25:36 78:55:29 79:18:17 79:09:02

01:11:09 01:15:34 01:21:15 01:20:38 01:26:44

butterfly AIGbutterfly PS

0.8

0.9

1.0

1.1

01:46:29 01:46:24 01:32:40 01:30:16 01:28:33

00:43:48 00:46:47 00:48:24 00:52:09 00:50:33

fir gen AIGfir gen PS

0.8

0.9

1.0

1.1 03:07:07 20:04:19 51:12:48 59:42:27 83:43:36

20:12:27 59:21:03 67:01:34 109:12:02 115:43:21

fir pipe 16 AIGfir pipe 16 PS

0.9

1.0

1.1

1.2

Nor

mal

ized

area

02:14:54 02:09:54 02:09:25 02:14:07 02:11:23

00:42:50 00:44:45 00:44:53 00:47:05 00:46:39

rgb2ycbcr AIGrgb2ycbcr PS

0.70.80.91.01.1

01:29:51 00:53:02 00:43:56 00:40:46 00:29:39

00:04:58 00:05:38 00:06:33 00:06:42 00:07:03

tern s n AIGtern s n PS

0.0 0.5 1.0 1.5 2.0

Worst-case error [%]

0.9

1.0

1.1

1.2

07:12:24 19:18:19 26:20:11 30:13:30 33:30:50

13:12:26 20:24:02 27:42:01 23:00:16 28:16:56

weight calc AIGweight calc PS

Conclusion & Outlook

• Analyzed existing frameworks– Identified & elaborated on requirements

• Presented concept for CIRCA– Modular and extensible framework– Showed current state & initial experimental results

• CIRCA enables comparing studies in Approximate Computing

• Continue implementation– Investigate other search methods and approximation techniques, e.g., A*

and circuit carving [11]– Implement other error metrics, e.g., average case error– Connect to back-end synthesis tool, e.g., Synopsys Design Compiler

• Make CIRCA open-source• Create an AC benchmark circuit set• Develop front-end to automatically identify candidates

13

Thank you for your attention!

Questions?

Bibliography[1] S. Venkataramani, K. Roy, and A. Raghunathan, “Substitute-and-simplify: A unified design paradigm for approximate and qualityconfigurable circuits,” in Proceedings of the Conference on Design, Automation & Test in Europe, DATE’13, IEEE, 2013.

[2] S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan, “SALSA: Systematic logic synthesis of approximatecircuits,” in Proceedings of the 49th Annual Design Automation Conference, DAC’12, ACM, 2012.

[3] A. Chandrasekharan, M. Soeken, D. Groesse, and R. Drechsler, “Approximation-aware rewriting of aigs for error tolerant applications,” in Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD’16, ACM, 2016.

[4] K. Nepal, Y. Li, R. I. Bahar, and S. Reda, “ABACUS: A technique for automated behavioral synthesis of approximate computingcircuits,” in Proceedings of the Conference on Design, Automation & Test in Europe, DATE’14, IEEE, 2014.

[5] G. Liu and Z. Zhang, “Statistically certified approximate logic synthesis.,” in Proceedings of the 36th International Conference on Computer-Aided Design, ICCAD’17,, IEEE, 2017.

[6] A.Ranjan, A. Raha, S. Venkataramani, K. Roy, and A. Raghunathan, “ASLAN: Synthesis of approximate sequential circuits,” in Proceedings of the Conference on Design, Automation & Test in Europe, DATE’14, IEEE, 2014.

[7] R. Brayton and A. Mishchenko, “ABC: An academic industrial-strength verification tool,” in Computer Aided Verification (T. Touili, B. Cook, and P. Jackson, eds.), pp. 24–40, Springer Berlin Heidelberg, 2010.

[8] U. Meyer-Baese, Digital signal processing with field programmable gate arrays. Springer, 2014.

[9] J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose, and V. Betz, “VTR 7.0: Next generation architecture and CAD system for FPGAs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, pp. 6:1–6:30, July 2014.

[10] D. Lundgren, “OpenCores jpegencode.” https://github.com/chiggs/oc_jpegencode. Accessed: 2018-05-25.

[11] [1] I. Scarabottolo, G. Ansaloni, and L. Pozzi, “Circuit carving - A methodology for the design of approximate hardware.,” DATE, pp. 545–550, 2018.

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