Chp 1- Vlsi Introduction

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    VLSI DESIGN

    Introduction

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    BACK END FRONT END

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    What is VLSI?? VLSI means Very Large-Scale Integration.

    It is an effort to integrate discrete component

    circuits in a single silicon base (chip).

    The integration results in a high reliability,

    low power consumption, high speed, lessweight, low volume, and low cost of products.

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    HISTORY of VLSI Small-Scale Integration (SSI)

    10 gates per chip, 1960s

    Medium-Scale Integration (MSI)

    1001000 gates per chip,1970s

    Large-Scale Integration (LSI)

    100010,000 gates per chip, 1980s

    Very Large-Scale Integration (VLSI)

    10,000100,000 gates per chip,1990s

    Ultra-Large Scale Integration (ULSI)

    1M10M gates per chip, Present

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    Moores Law Gordon Moore -- Intels co-founder

    Statement: Transistors on a IC

    doubles every 2 years.

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    VLSI Design Companies Semiconductor Fab

    companies Semiconductor

    Fabless companies

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    MOS related VLSI technology

    nMOS

    pMOS

    CMOS Logic (nMOS & pMOS)

    BiCMOS I/O and Driver circuits

    GaAs High mobility

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    CMOS Circuit Example

    VDD VDD

    VinVout

    M1

    M2

    M3

    M4

    Vout2

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    CMOS Circuit - Layout View

    VDD VDD

    VinVout

    M1

    M2

    M3

    M4

    Vout2

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    Fabrication Technology

    nMOS Fabrication

    CMOS Fabrication

    p-well process

    n-well process

    twin-tub process

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    Fabrication Technology

    Silicon of extremely high purity

    chemically purified then grown into large crystals

    Wafers

    crystals are sliced into wafers wafer diameter is currently 150mm, 200mm, 300mm

    wafer thickness

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    A relatively thick silicon dioxide layer (5000A), also called

    field oxide, is created on the surface SI Substrate

    Si Substrtate

    N-MOS Fabrication

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    N-MOS Fabrication (contd..)

    Photolithography

    Spin on photoresist

    Photoresist is a light-

    sensitive organic polymer

    Softens where exposed to

    light

    Expose photoresist to UV rays

    through optical mask layerand strip off exposed

    photoresist.

    (b) After oxidation and depositionof negative photoresist

    Photoresist

    SiO2

    Si-substrate

    Si-substrate

    (c) Stepper exposure

    UV-light

    Patternedoptical mask

    Exposed resist

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    N-MOS Fabrication(Contd..)

    Photolithography

    Etching: selective removal of

    a layer. Remove Silicon dioxide

    with hydrofluoric acid.

    Only attacks oxide

    where resist has been

    exposed

    Strip off remaining

    photoresist using etching.

    Si-substrate

    SiO2

    Si-substrate

    Si-substrate

    SiO2

    SiO2

    (d) After development and etching of resist,chemical or plasma etch of SiO

    2

    (e) After etching

    (f) Final result after removal of resist

    Hardened resist

    Hardened resist

    Chemical or plasmaetch

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    oxidation

    opticalmask

    processstep

    photoresist coatingphotoresistremoval (ashing)

    spin, rinse, dry

    acid etch

    photoresist

    stepper exposure

    development

    Typical operations in a single

    photolithographic cycle (from [Fullman]).

    Photo-Lithographic Process

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    The field oxide is selectively etched to expose the silicon

    surface on which the MOS transistor will be created

    The surface is covered with a thin, high-quality oxide

    layer (25A), which will eventually form the gate oxide of

    the MOS transistor

    On top of the thin oxide, a layer of polysilicon

    (polycrystalline silicon, 3000A) is deposited

    After deposition, the polysilicon layer is patterned

    and etched to form the interconnects and the

    MOS transistor gates

    N-MOS Fabrication (contd..)

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    The thin gate oxide not covered by polysilicon is also

    etched away, which exposes the bare silicon surface

    on which the source and drain junctions are to be

    formed

    The entire silicon surface is then doped with a high

    concentration of impurities, either through diffusion

    or ion implantation ultimately creating two n-type

    regions (source and drain junctions) in the p-type

    substrate

    Once the source and drain regions are completed,

    the entire surface is again covered with an

    insulating layer of silicon dioxide

    The insulating oxide layer is then patterned inorder to provide contact windows for the drain andsource junctions

    The thin gate oxide not covered by polysilicon is also

    etched away, which exposes the bare silicon surface

    on which the source and drain junctions are to be

    formed

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    The surface is covered with evaporatealuminum (5000A) which will form the

    interconnects

    Finally, the metal layer is patterned andetched, completing the interconnectionof the MOS transistors on the surface

    N-MOS Fabrication (contd..)

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    3D View of NMOS Transistor

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    CMOS Fabrication - Types

    p-well process

    n-well process

    twin-tub process

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    CMOS Technology

    First proposed in the 1960s. Was not seriously considered untilthe severe limitations in power density and dissipation occurredin NMOS circuits

    Now the dominant technology in IC manufacturing Employs both pMOS and nMOS transistors to form logic

    elements

    The advantage of CMOS is that its logic elements drawsignificant current only during the transition from one state to

    another and very little current between transitions - hencepower is conserved.

    In the case of an inverter, in either logic state one of thetransistors is off. Since the transistors are in series, (~ no)current flows.

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    CMOS Fabrication P-Well Process

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    CMOS Inverter Device using p well

    In p & n-well CMOS process, the doping density of the well region

    is typically about one order of magnitude higher than the substrate, which

    results in unbalanced drain parasitics. The twin-tub process avoids this problem.

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    Twin tub process

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    Twin tub process

    This technology provides the basis for separate optimization of

    the nMOS and pMOS transistors.

    The starting material is a n+ or p+ substrate, with a lightly

    doped epitaxial layer on top.

    This epitaxial layer provides the actual substrate on which the

    n-well and the p-well are formed.

    Since two independent doping steps are performed for the

    creation of the well regions, the dopant concentrations can be

    carefully optimized to produce the desired device

    characteristics.

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    BiCMOS Technology

    A known deficiency of MOS technology is its limited load drivingcapabilities (due to limited current sourcing and sinking abilitiesof pMOS and nMOS transistors.

    Bipolar transistors have higher gain

    better noise characteristics

    better high frequency characteristics

    BiCMOS gates can be an efficient way of speeding up VLSI

    circuits. CMOS fabrication process can be extended for BiCMOS

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    CMOS and Bi-CMOS Difference

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    N-well CMOS and Bi-CMOS

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    BiCMOS npn Transistor

    P+ baseregion.

    N+ collectorarea.

    BuriedSubcollector

    (BCCD)

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    Electrical Properties of NMOS

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    NMOS Transistor Cut-off region

    Vgs

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    NMOS Transistor Linear region

    n+

    n+

    p-substrate

    D

    S

    G

    B

    VGS

    xL

    V(x) +

    VDS

    ID

    MOS transistor and its bias conditionsVgs > Vt

    Vds > 0

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    NMOS Transistor Saturation region

    n+n+

    S

    G

    VGS

    D

    VDS > VGS - VT

    VGS

    - VT

    +-

    Pinch off

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    Voltage & Current Properties

    0 0.5 1 1.5 2 2.50

    1

    2

    3

    4

    5

    6x 10

    -4

    VDS

    (V)

    ID(A

    )

    VGS= 2.5 V

    VGS= 2.0 V

    VGS= 1.5 V

    VGS= 1.0 V

    Resistive Saturation

    VDS

    = VGS

    - VT

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    Electrical parameters of NMOS

    Source to Drain Current (Ids)

    Threshold Voltage (Vt).

    Transconductance (gm)

    Figure of Merit (0

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    Pass Transistors

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    NMOS INVERTER

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    NMOS Enhancement Mode Transistor as Load

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    Vss

    Vo

    Vin

    D

    S

    D

    S

    NMOS Enhancement Mode Transistor as LoadVdd

    Vgg

    Vt (pull down)

    V0Vdd

    Vt (pull up)

    Non zero output

    Vin

    Dissipation is high since current flows when Vin = 1

    Vgg can be derived from a switching source

    Vout can never reach Vdd (effect of channel)

    This type of inverter is not preferred.

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    CMOS Technology

    First proposed in the 1960s. Was not seriously considered untilthe severe limitations in power density and dissipation occurredin NMOS circuits

    Now the dominant technology in IC manufacturing Employs both pMOS and nMOS transistors to form logic

    elements

    The advantage of CMOS is that its logic elements drawsignificant current only during the transition from one state to

    another and very little current between transitions - hencepower is conserved.

    In the case of an inverter, in either logic state one of thetransistors is off. Since the transistors are in series, (~ no)current flows.

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    CMOS INVERTER

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    Circuit and Layout

    Polysilicon

    In Out

    VDD

    GND

    PMOS2

    Metal 1

    NMOS

    OutIn

    VDD

    PMOS

    NMOS

    Contacts

    N Well

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    CMOS Inverter Properties

    Full rail-to-rail swing high noise margins

    Logic levels not dependent upon the relative device sizestransistors can be minimum size ratioless.

    Always a path to Vdd or GND in steady state low outputimpedance (output resistance in k range) large fan-out.

    Extremely high input resistance (gate of MOS transistor is nearperfect insulator) nearly zero steady-state input current.

    No direct path steady-state between power and ground no static

    power dissipation.

    Propagation delay function of load capacitance and resistance oftransistors.

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    Basic Operation

    VIN= 0 then VOUT= VDD

    VGSn= 0 < VTn . NMOS OFF

    VSGp= VDD > -VTp . PMOS ON

    VIN= VDD then VOUT= 0

    VGSn= VDD > VTn . NMOS ON

    VSGp= 0 < -VTp . PMOS OFF

    No power consumption while idling in any logic

    state.

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    CMOS Inverter: Simple Response

    VoutVout

    Rn

    Rp

    VDDVDD

    Vin= VDDVin= 0V

    (a) Low-to-high (b) High-to-low

    CLCL

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    NMOS Transistor Characteristics

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    X 10-4

    VGS = 1.0V

    VGS = 1.5V

    VGS = 2.0V

    VGS = 2.5V

    VDS (V)

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    PMOS Transistor Characteristics

    -1

    -0.8

    -0.6

    -0.4

    -0.2

    0

    0-1-2VDS (V)

    X 10-4

    VGS

    = -1.0V

    VGS = -1.5V

    VGS = -2.0V

    VGS = -2.5V

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    CMOS Inverter Load CharacteristicsIDn

    Vout

    Vin = 2.5

    Vin = 2

    Vin = 1.5

    Vin

    = 0

    Vin = 0.5

    Vin = 1

    NMOS

    Vin

    = 0

    Vin

    = 0.5

    Vin = 1Vin

    = 1.5

    Vin = 2

    Vin = 2.5

    Vin = 1Vin = 1.5

    PMOS

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    Voltage Transfer CharacteristicsVout

    Vin0.5 1 1.5 2 2.5

    0.

    5

    1

    1.

    5

    2

    2.

    5

    NMOS res

    PMOS off

    NMOS sat

    PMOS sat

    NMOS off

    PMOS res

    NMOS sat

    PMOS res

    NMOS res

    PMOS sat

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    CMOS Propagation Delay

    VDD

    Vout

    Vin = VDD

    CLIav

    tpHL = CL Vswing/2

    Iav

    CL

    kn VDD

    ~

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    CMOS Propagation Delay

    VDD

    Vout

    Vin = VDD

    Ron

    CL

    tpHL = f(Ron.CL)

    = 0.69 Ron

    CL

    t

    Vout

    VDD

    RonCL

    1

    0.5

    ln(0.5)

    0.36

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    NMOS Transistor Capacitances

    Gate to Source (CGS).

    Gate to Substrate (CGB).

    Gate to Drain (CGD).

    Drain to Substrate (CDB).

    Source to Substrate (CSB).

    DS

    G

    B

    CGDCGS

    CSB

    CDBCGB

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    Design for performance - Speed

    Keep capacitances small

    Increase transistor sizes

    Increase VDD (Slight increase)

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    BiCMOS Inverter

    Speed is the only restricting factor inCMOS Inverter, especially whenlarge capacitors must be driven.

    Propagation delay of CMOS inverteris more in that case, which dependon the capacitances. So Speeddecreases.

    So, for this reason BiCMOS inverteris used in current driven circuits(Capacitance).

    In the BiCMOS structure, the input

    stage and the phase-splitter areimplemented in MOS, which resultsin a better performance and higherinput impedance.

    Low Power Consumption because ofMOS Transistors.

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    BiCMOS Inverter Operation

    When the input is high, the

    NMOS transistor M1 is on,

    causing Q1 to conduct, while

    M2 and Q2 are off. The

    result is a low output voltage

    When the input is low, the

    PMOS transistor M2is on,

    causing Q2to conduct, while

    M1and Q1are off. The

    result is a high output

    voltage.

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    tpLH for CMOS and BiCMOS

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    Latch-up in CMOS

    Latch-up is a failure mechanism of CMOS integratedcircuits.

    It is characterized by excessive current drain coupled withfunctional and parametric failure, and finally devicedestruction.

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    Latch-up in CMOS (Contd)

    Latch-up exists in all junction isolated or bulk CMOS Process

    Parastic PNPN paths forms NPN and PNP Bipolar Transistorswhich cause latch-up.

    Normally, only a small leakage current flows between the

    substrate and P-well causing only a minute bias and CMOSis well behaved.

    In the presence of intense ionizing radiation, thermal orover-voltage stress, however, current can be injected intothe PNP emitter-base junction, forward-biasing it and the

    NPN device turns on, increasing the base drive to the PNP. Gain of the PNP and NPN Transistors increases.

    Then the CMOS draws more current from external network,

    thus causing Latch-up.

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    Remedies for Latch-up

    Reduction of substrate

    resistance Rs.

    Reducing N-well Resistance (Rn)

    in N-well Process and P-wellResistance (Rp) in P-well

    process to decrease Gain of the

    Transistors.

    Introduction of guard rings for

    large current carrying devices

    (Transistors) to reduce the

    resistance.