Choosing the Right Fixed Frequency Buck Regulator Control...

52
Choosing the Right Fixed Frequency Buck Regulator Control Strategy Brian Cheng Eric Lee Brian Lynch RobertTaylor

Transcript of Choosing the Right Fixed Frequency Buck Regulator Control...

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Choosing the Right Fixed Frequency Buck Regulator Control Strategy

Brian Cheng

Eric Lee Brian Lynch RobertTaylor

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How Do You Choose?

1-2

Part A •  Buck regulator basics

-  Basic functions -  Filter design -  Fixed frequency vs. variable

•  Fixed frequency control -  Voltage mode control -  Current mode control -  Emulated current mode control

Part B •  Variable frequency control

Texas Instruments – 2014/15 Power Supply Design Seminar

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Buck Regulator

•  Step down only •  “Chop up” the input voltage •  Send to averaging filter

1-3 Texas Instruments – 2014/15 Power Supply Design Seminar

Pretty simple – right?

VOUT = Duty Cycle × VIN

VIN

VIN

GNDD 1-D

LOUT

ESR

HDRV

LDRV

SW

COUT RLOAD

VOUT

VOUTIL

ISW

ISR

Control

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Texas Instruments – 2014/15 Power Supply Design Seminar 1-4

Synchronous Buck Waveforms

Continuous Conduction Mode •  Inductor current

flow is continuous during the switching cycle

Duty CycleCCM =tON

tON + tOFF

Duty CycleCCM = tONTS

HDVR

LDRV

ISW

ISR

SW

VOUT

IL 20.018.016.014.012.010.0

5.04.03.02.01.00.0

5.04.03.02.01.00.0

20.015.010.05.00.0

10.00.0

-10.0-20.0

5.04.03.02.01.00.0-1.0

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1-5 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Continuous Conduction Mode Switch turn ON

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

4.0

2.0

0.0

4.0

2.0

0.0

20.015.010.05.00.0

10.05.00.0

-5.0-10.0-15.0-20.0

(V)

(V)

(Am

pere

s)(A

mpe

res)

(Am

pere

s)(V

olts

)

Control

5.04.03.02.01.00.0

-1.011.711.611.511.411.311.2

500.15µTime (Seconds)

500.2µ

Buck Converter Waveforms

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5.04.03.02.01.00.0

20.015.010.05.00.010.0

0.0

-10.0

-20.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

Control

5.04.03.02.01.00.0-1.0

20.018.016.014.012.010.0

5.04.03.02.01.00.0

1-6 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Continuous Conduction Mode Power transfer

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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4.0

2.0

0.0

4.0

2.0

0.0

20.015.010.05.00.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

Control

5.04.03.02.01.00.0-1.0

10.05.00.0-5.0-10.0-15.0-20.0

19.018.818.618.418.218.017.8

1-7 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Continuous Conduction Mode Switch turn OFF transition to SR turn ON

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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4.0

2.0

0.0

4.0

2.0

0.0

20.015.010.05.00.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

Control

0.40.20.0-0.2-0.4-0.6-0.8

10.05.00.0-5.0-10.0-15.0-20.0

20.018.016.014.012.010.0

1-8 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Continuous Conduction Mode Inductor reset

HDVR

LDRV

ISW

ISR

SW

IL

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1-9 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Continuous Conduction Mode Transition for next cycle

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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Duty CycleDCM

=tON

tON

+ tOFF

+ tdead

Duty CycleDCM

=2 × L × I

OUT

TS × VIN

× V

OUT

VIN

− VOUT

⎝⎜⎞

⎠⎟

5.04.03.02.01.00.0

-1.0

1.01.0

-1.0-2.0-3.0-4.0-5.0

5.04.03.02.01.00.0

5.04.03.02.01.00.0

6.04.02.00.0

-2.0

(V)

(V)

(Am

pere

s)(A

mpe

res)

(Am

pere

s)(V

olts

)

500 µ 501 µ 502 µ 503 µ 504 µ 505 µ 506 µ Time (Seconds)

5.04.03.02.01.00.0

-1.0

1-10 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode •  Inductor current flow is

discontinuous during the switching cycle

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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5.04.03.02.01.00.0

5.04.03.02.01.00.05.04.03.02.01.00.0-1.0

5.04.03.02.01.00.0-1.0

1.00.0-1.0-2.0-3.0-4.0-5.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

Control 6.04.02.00.0-2.0

1-11 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode •  First part is the same as

CCM Mode •  High side switch turns ON

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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5.04.03.02.01.00.0

5.04.03.02.01.00.05.04.03.02.01.00.0-1.0

5.04.03.02.01.00.0-1.0

1.00.0-1.0-2.0-3.0-4.0-5.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

6.04.02.00.0-2.0

Control

1-12 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode Switch ON

HDVR

LDRV

ISW

ISR

SW

VOUT

IL

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5.04.03.02.01.00.0

5.04.03.02.01.00.05.04.03.02.01.00.0-1.0

5.04.03.02.01.00.0-1.0

1.00.0-1.0-2.0-3.0-4.0-5.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

6.04.02.00.0-2.0

Control

1-13 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode •  Switch turn OFF •  SR turn ON ISW

ISR

SW

VOUT

IL

HDVR

LDRV

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5.04.03.02.01.00.0

5.04.03.02.01.00.0

40.0 m20.0 m

0.0-20.0 m-40.0 m

0.20.15

0.150.0 m

0.0-50.0 m

1.00.0

-1.0-2.0-3.0-4.0-5.0

(V)

(V)

(Am

pere

s)(A

mpe

res)

(Am

pere

s)(V

olts

)

4.03.02.01.00.0

-1.0-2.0

Control

1-14 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode •  SR turns OFF at zero

current in inductor ISW

ISR

SW

VOUT

IL

HDVR

LDRV

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8.06.04.02.00.0-2.0

5.04.03.02.01.00.0

5.04.03.02.01.00.0-1.0

1.51.00.50.0-0.5

6.04.02.00.0-2.0

1.00.0-1.0-2.0-3.0-4.0-5.0

(V)

(V)

(Amperes)

(Amperes)

(Amperes)

(Volts)

Control

1-15 Texas Instruments – 2014/15 Power Supply Design Seminar

Synchronous Buck Waveforms

Discontinuous Conduction Mode •  Freewheeling interval

ISW

ISR

SW

VOUT

IL

HDVR

LDRV

Duty CycleDCM

=tON

tON

+ tOFF

+ tdead

Duty CycleDCM

=2 × L × I

OUT

TS × VIN

× V

OUT

VIN

− VOUT

⎝⎜⎞

⎠⎟

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1-16 Texas Instruments – 2014/15 Power Supply Design Seminar

L-C Filter Design

•  Inductor design for ripple current

ΔIL =VIN −VOUT( ) × D × TS

L

•  Ripple current is generally 10% to 30% of full load current

•  Capacitor selection for general purpose -  Select TYPE based on ESR and ESL -  Voltage ripple = impedance x inductor ripple -  Select VALUE based on corner frequency of ~1/10 of

desired crossover frequency

VIN x D

RDS(ON_SR)

RDS(ON_SW) RLL

D

1-D

VOUT

ZOUT

RLOAD

ZLZIN

C1 C2

ESR2ESR1

ESL2ESL1

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1-17 Texas Instruments – 2014/15 Power Supply Design Seminar

Output Capacitors

Type of Cap Advantages Disadvantages

Ceramic Small size, low cost, low ESR, high ripple current rating

DC bias effects, low capacitance, cracking

Aluminum Electrolytic

High capacitance, low cost, good for high voltage

High ESR, low ripple current rating, temp issues, large size

Aluminum Polymer

High capacitance, low ESR, high ripple current rating

Expensive, fewer manufacturers, large size, voltage rating

Tantalum Polymer

High capacitance, low ESR, high ripple current rating, small size

Expensive, fewer manufacturers, voltage rating

Output capacitors will determine output ripple, transient response and greatly impact the compensation

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Output Inductors

1-18 Texas Instruments – 2014/15 Power Supply Design Seminar

Output inductors will also determine output ripple, transient response and greatly impact the compensation

Type of Cap Advantages Disadvantages

Drum Core Low cost, many vendors, high Isat, higher inductances

Can be unshielded, high core loss, high DCR, hard Isat

Molded Core Very high Isat, easy to shape into many sizes, shielded, soft Isat

High core losses, low inductance range

Shaped Core Low core loss, low DCR, high current, shielded, high inductance range

High cost, hard Isat, not suitable for low profile

Power Bead Low core loss, low DCR, excellent for multiphase

Low inductance, hard Isat

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Filter AC Response

1-19 Texas Instruments – 2014/15 Power Supply Design Seminar

Corner frequency ~ 5 kHz

ESR zero ~ 21 kHz

ESL zero ~ 240 kHz

Filter Response

Frequency (Hz)

10

0

-10

-20

-30

-40

-50

180

135

90

45

0

-45

-90

-135

-180

10 100 1x103 1x104 1x105 1x106

dB

De

gre

es

Gain Phase

VIN x D

RDS(ON_SR)

RDS(ON_SW) RLL

D

1-D

VOUT

ZOUT

RLOAD

ZLZIN

C1 C2

ESR2ESR1

ESL2ESL1

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Filter Design for Transient Response

1-20 Texas Instruments – 2014/15 Power Supply Design Seminar

•  Select L for current slew rate

•  Select capacitance VALUE based on support of output voltage while current is increasing

ΔVC = ΔI2

2 × VIN −VOUT( ) × LC

ΔIL =VIN −VOUT( ) × D × TS

L

Capacitor Discharge

¨,/

¨9&

,QGXFWRU�&XUUHQW

&DSDFLWRU�9ROWDJH

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•  Propagation delays limit the minimum controllable pulse width

•  Below minimum controllable on-time, pulse skipping could occur

• 

•  Example – TPS40170, min on-time is 100 ns max -  VIN = 60 Vmax -  VOUT = 5 V or 3.3 V -  Frequency = 600 KHz (+10% shift)

•  For a 3.3 V output, the frequency would need to be lowered to ensure no pulse skipping

1-21 Texas Instruments – 2014/15 Power Supply Design Seminar

Minimum Controllable On-Time

TonMIN ≤VOUT

VIN _ max × fmax

TonMIN ≤ 5 V60 V × 600 kHz × 1.1

= 140 ns

TonMIN ≤ 3.3 V60 V × 600 kHz × 1.1

= 91 ns

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1-22 Texas Instruments – 2014/15 Power Supply Design Seminar

Fixed Frequency vs. Variable Frequency

•  Fixed frequency operation (Part A) –  Synchronize multiple devices

•  Eliminate beat frequencies between multiple converters •  Ripple cancellation to reduce losses in capacitors and PCB

traces –  EMI peaks consistent at any operating mode –  Minimum controllable pulse width

•  Variable frequency operation (Part B)

–  Easier to compensate –  Lower peak EMI, higher average –  Faster load transient response –  Could be lower cost due to lower component count

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1-23 Texas Instruments – 2014/15 Power Supply Design Seminar

Fixed Frequency Control

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1-24 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control Introduction

+

+

PWM Comparator

VOUTPower Stage

Reference

Voltage

Voltage Error

Amplifier

Output

Voltage

Divider

Ramp

Compensation

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1-25 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Basic Operation

•  Power switches generate a square wave

•  Output inductor and output capacitor form a low pass filter

•  (CCM)

•  Type 3 compensator generally required

VOUT = D × VIN

PWM Comparator

+VOUT

Voltage ErrorAmplifier

OutputVoltageDivider

+–+

+–

Power Stage

ReferenceVoltage

Compensation

CHF

RCOMP

RCOMP2

CCOMPCCOMP2

VFB

VREF

RFBT

RFBB

Amplifier

S Q

R Q

+–

CLKRamp

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PWM Comparator

+VOUT

Voltage ErrorAmplifier

OutputVoltageDivider

+–

Power Stage

ReferenceVoltage

Compensation

Ramp

VIN

GNDD 1-D

LOUT

ESR

COUT RLOAD

VOUT

40

20

0

-20

-40

-6010 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Gai

n (d

B)

LC Double Pole

ESR Zero-40 db/decade

-20 db/decade

1-26 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Power Stage

HPS

(s) =1+ (C

OUT × R

ESR)s

1+L

OUT

ROUT

+ RESR

× COUT

⎝⎜⎞

⎠⎟s +

ROUT

+ RESR

ROUT

⎝⎜⎞

⎠⎟L

OUT × C

OUT × s2

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1-27 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Pulse Width Modulator

•  If the output voltage is too low, the duty cycle is increased

•  If the output voltage is too high, the duty cycle is reduced

•  Gain of the modulator: HMod =VINVRamp

PWM Comparator

PWM Comparator

+

VOUT

VRamp

VError

VPWM

Voltage Error

Amplifier

Output

Voltage

Divider

+

+

Power Stage

Power Switch

Driver

Reference

Voltage

Compensation

Ramp

Error Signal from

Compensation

Network

Ramp

D 1-D

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1-28 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Feed Forward •  As  VIN  is  increased,  the  gain  increases.  Not  good  for  wide  input  voltage  ranges.  

Voltage  feed  forward  fixes  this  issue.  

•  Gain  of  the  modulator:    

•  Feed  Forward  increases  the  ramp  amplitude  propor@onal  to  the  input  voltage  

HMod =VIN

VRamp=

VINK × VIN

VIN

VCLK

VCOMP

PWM

RAMP

MInimum OFF Time

t-Time

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1-29 Texas Instruments – 2014/15 Power Supply Design Seminar

Why Do We Compensate?

Output Voltage (AC coupled) 50 mV/Division Output Current 500 mA/Division

100 µs/Division

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PWM Comparator

+VOUT

VOUT

Voltage ErrorAmplifier

OutputVoltageDivider

+

+

Power Stage

Compensation

Ramp

ReferenceVoltage

ReferenceVoltage

Voltage ErrorAmplifier

OutputVoltageDivider

40

20

0

-20

-40

-6010 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Gai

n (d

B)

PolePole

Zero

-20 db

-20 db0 db

0 db+20 db

1-30 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Compensation Type 3 Compensator

•  Type 1 compensator – single dominant pole

•  Type 2 compensator – two poles, one zero

•  Type 3 compensator – three poles, two zeros

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40

20

0

-20

-40

-60

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Ga

in (

dB

)

Pole

Pole

Zero

-20 db

-20 db

0 db

0 db

+20 db

40

20

0

-20

-40

-60

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Gain

(d

B)

LC Double Pole

ESR Zero

-40 db/decade

-20 db/decade

60

40

20

0

-20

-40

-60

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Gain

(d

B)

Crossover Frequency

=

+

1-31 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control Loop Compensation

•  Use double zero to cancel double pole

•  Cross 0 dB with -20 dB/decade response

•  Cross 1/10th to 1/4th below the switching frequency

Type 3 Compensator Power Stage + Modulation

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1-32 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control – Transient Response

•  Output filter and loop compensation will impact the transient response

•  Increasing the loop BW will lead to faster recovery time and lower voltage deviation

•  Closed loop impedance of filter multiplied by load step can predict the voltage deviation

Output Current 10 A/Division Output Voltage (AC Coupled) 500 mV/Division Recovery Time

Voltage Deviation

200 µs/Division

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1-33 Texas Instruments – 2014/15 Power Supply Design Seminar

Voltage Mode Control

Advantages Disadvantages

Fixed frequency operation High bandwidth error amplifier required

Easy to synchronize to external clocks

Double pole compensation is more difficult

Voltage regulation is independent of current

Inductor value affects the compensation

Single feedback loop VIN affects loop gain (unless using feed forward)

Less susceptible to noise Difficult to control light load efficiency modes

Good load regulation Multiphase operation would require an extra current sharing loop

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VIN

VOUT

ENABLE UVLO

VINSYNC

BOOTM/S

HDRVRT

SWSS

VBPTRK

LDRVFB

PGNDCOMP

ILIMAGNDPGOODVDD

1 20

10 11

19

18

17

16

15

14

13

12

2

3

4

5

6

7

8

9

TPS40170

1-34 Texas Instruments – 2014/15 Power Supply Design Seminar

Design Example #1 Voltage Mode – Design Specifications

Design Specifications

Input voltage range 10 V to 60 V

Target output voltage 5 V

Output current range 0 A to 6 A

Switching frequency 300 kHz

Controller TPS40170

Operating Values (Theoretical) Minimum duty cycle 0.083

Minimum on-time 0.277 µs

Maximum duty cycle 0.500

Maximum on-time 1.667 µs

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1-35 Texas Instruments – 2014/15 Power Supply Design Seminar

Design Example #1 Voltage Mode – Design Procedure

•  Choose switching frequency first •  Calculate the output filter components (L and C) •  Calculate the power stage components (FETs)

•  WEBENCH® •  Helps calculate all of specific values for design •  Allows optimization based on design goals •  Gives estimates for loop response and efficiency •  Provides a complete schematic and bill of materials

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1-36 Texas Instruments – 2014/15 Power Supply Design Seminar

Design Example #1 Voltage Mode – Performance Graphs

Data is taken with TPS40170 EVM (HPA578)

Output Ripple 20 mV/Div

Switch Node 10 V/Div

Output Current 5 A/Div

1 µs/Div

Output Current 5 A/Div 200 µs/Div

Output Votlage 20 mV/Div

Transient Response

Switching Operation

VI = 60 V

VI = 12 V VI = 10 V

VI = 48 VVI = 36 V

VI = 24 V

0 1 2 3 4 5 6 7

100

95

90

85

80

75

70

Efficiency

Loop ResponseVI = 60 V,VO = 5 V,IO = 6 A,Bandwidth: 58 kHzPhase Margin: 51°

Phase

Gain

100

80

60

40

20

0

-20

-40

-60

225

180

135

90

45

0

-45

-90

-135

Gai

n (d

B)

Phas

e (d

eg)

f - Frequency (kHz)

0.1 1 10 100 1000

- Ef

ficie

ncy

- %

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C171000 pF

R912.1 K

R102.74 K

R43.83 K

R731.6 K

C1547 nF

C14220 µF

C13 8200 pF

R622.1 K

R510.0 K

C181 µF

C194.7 µF

C201000 µF

VOUT

VOUT

20191817161514131211

123456789

10

TP5

TP9 TP10 TP11 TP12

TP6 TP7 TP81

1

1

21

R1120.0 K

R13511

C211500 pF

R1249.9

C161 µF

VDDPGOOD

R30

U1TPS4017ORGY

ENABLESYNC

M/S

TRK

VIN

VIN 10 - 60 V

R2200 K

R11.0

C70.1 µF

C12.2 µF

C22.2 µF

C32.2 µF

C42.2 µF

C51 µF

C6120 µF

TP1

TP2

TP3

TP4

J1

J2

12

12 5 V @ 6 A

Q1CSD18537NQ5A

Q2CSD18563Q5A

L18.2 µH

C922 µF

C1022 µF

C2210 µF

C1210 µF

Caution:Surfaces may be HotHigh Voltages Present

Connect AGND and PGND to GND with 10 mil traces under IC

ENABLESYNCM/SRTSSTRKFBCOMPAGNDVDD

UVLOVIN

BOOTHDRV

SWVBP

LDRVPGND

ILIMPGOOD

GND

1-37 Texas Instruments – 2014/15 Power Supply Design Seminar

Design Example #1 Voltage Mode – Schematic (HPA578)

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1-38 Texas Instruments – 2014/15 Power Supply Design Seminar

Current Mode Control Basic Operation

•  Peak current mode is more popular than valley •  Outer voltage loop + inner current loop •  High-side / DCR current sensing •  Error amp output controls peak inductor current •  Allows current source to replace inductor

Type 2 Compensation

PWM Comparator

+VOUT–

+–

Power Stage

Compensation

CurrentFeedback

Ramp

ReferenceVoltage

Voltage ErrorAmplifier

OutputVoltageDivider

+–

CHF

RCOMP CCOMPVFB

VREF

RFBT

RFBB

+– –

S Q

R Q

+–

CLK

VERR

VCS

VSW

TON

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+– –

S Q

R Q

+–

CLK

+ –+– –

S Q

R Q

+–

CLK

+ –

DCR Sensing Sub-Harmonic Oscillation

Resistor Sensing

¨,2

¨,2

¨,1¨,0

¨,0

VERR

VERR

¨,1

D

D

1-39 Texas Instruments – 2014/15 Power Supply Design Seminar

Current Mode Control Other Considerations

•  ∆I0 > ∆I1 > ∆I2 when D < 0.5

•  ∆I0 < ∆I1 < ∆I2 when D > 0.5 (sub-harmonic Oscillation) •  Requires slope compensation to

be stable

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L

RESR

RLOAD

COUT

RESR

RLOAD

COUT

40

20

0

-20

-40

-60

-8

-100

-120

Gai

n (d

B)

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

0

-45

-90

-135

-180

Phas

e (°

)

Frequency (Hz)

0

-45

-90

-135

-180

Phas

e (°

)10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Voltage Mode

Current Mode 40

20

0

-20

-40

-60

-8

-100

-120

Gai

n (d

B)

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Double Pole

ESR Zero

Double Pole

ESR Zero

-20 dB/decade

-40 dB/decade

-180° Phase Shift

-90° Phase Shift

10 100 1x103 1x104 1x105 1x106

1-40 Texas Instruments – 2014/15 Power Supply Design Seminar

Current Mode Control Power Stage + Modulation

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60

40

20

0

-20

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Ga

in (

dB

)

Compensation

Zero

Compensation

Pole

Mid

Frequency

Gain

40

20

0

-20

-40

-60

10 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Ga

in (

dB

)

ESR Zero

Load Pole

Sampling Pole

DC Gain

40

20

0

-20

-40

-6010 100 1x103 1x104 1x105 1x106

Frequency (Hz)

Ga

in (

dB

)

Crossover Frequency

=

+

1-41 Texas Instruments – 2014/15 Power Supply Design Seminar

Current Mode Control Loop Compensation

•  Cancel load pole and ESR zero by placing error amplifier zero and pole

•  Cross 0 dB with -20 dB/decade response

Type 2 Compensator Power Stage + Modulation

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1-42 Texas Instruments – 2014/15 Power Supply Design Seminar

Current Mode Control

Advantages Disadvantages Single pole system allows simple Type 2 compensation

Need for slope compensation to eliminate sub-harmonic oscillation

Inherent feed forward improves line transient performance

Noise sensitivity at leading edge spike

Easy implementation of cycle-by-cycle current limit

Need for relatively long minimum on-time (peak current mode)

Easy current share across multiple converters

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Type 2 Compensation

Valley Current Feedback

PWM Comparator

+VOUT–

+–

Power Stage

Compensation

Ramp

ReferenceVoltage

Voltage ErrorAmplifier

OutputVoltageDivider

+–

CHF

RCOMP CCOMPVFB

VREF

RFBT

RFBB

+– –

S Q

R Q

+–

CLK+

EmulatedRamp

S&H

+

VERR

VECS

VCS

VSW

TON

S&H S&H

S&H

1-43 Texas Instruments – 2014/15 Power Supply Design Seminar

Emulated Current Mode Control Basic Operation

•  Low-side current sensing during free-wheeling •  Sample & hold valley current before high-side

switch turns on •  Reconstruct buck switch current

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1-44

Emulated Current Mode Control Leading Edge Spike

•  The on-time of conventional peak current mode controller is limited by the leading edge spike

•  R-C filtering distorts the waveform •  Leading edge blanking limits the minimum

on-time •  Emulated current mode ensures a clean

current waveform during high-side switch on-time

Texas Instruments – 2014/15 Power Supply Design Seminar

R-C Filter

Leading Edge Blanking

Waveform Distortion

Unavailable Area

Emulated Current Mode

Sample & Hold Sample & Hold

Reconstructed Ramp

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RAMP

RAMP

CRAMP

tON

Sample and HoldDC Level 10 x RS V/A

5 µA/V x (VIN – VOUT)

RS IL

25 µA

Inductor CurrentReconstruction

SlopeCompensation

TO PWMCurrent Sense

Amplifier

S&H

HO_ENABLECSG

CS

-

+AS = 10

1-45

Emulated Current Mode Control Ramp Reconstruction

•  Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the current sense resistor (RS)

•     RS × AS = 5µ × LCRAMP

Texas Instruments – 2014/15 Power Supply Design Seminar

RAMP = 5 µA / V × (VIN

− VOUT

) + 25 µA( ) × tON

CRAMP

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1-46

Emulated Current Mode Control

Advantages Disadvantages Single-pole system allows simple Type 2 compensation

Need for slope compensation to eliminate sub-harmonic oscillation

Inherent feed forward improves line transient performance

Need for relatively long minimum off-time than peak current mode

Easy implementation of cycle-by-cycle current limit Easy current share across multiple converters Noise immunity at leading edge spike

Minimum on-time can be less than peak current mode

All advantages of peak current mode control remain

Texas Instruments – 2014/15 Power Supply Design Seminar

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1-47

Design Example #2 Design Specifications

Design Specifications

Input voltage range 7 V to 60 V

Target output voltage 5 V

Output current range 0 A to 7 A

Switching frequency 250 kHz

Controller LM5116

Operating Values (Theoretical) Minimum duty cycle 0.083

Minimum on-time 0.333 µs

Maximum duty cycle 0.714

Maximum on-time 2.857 µs

Texas Instruments – 2014/15 Power Supply Design Seminar

optional 5-15 V

RCOMP CCOMP

CHF

COUT1

L

COUT2

CIN

CHBCRAMP

CFT

CSS

RT

RUV1

RUV2

CVCCRRAMP

RS

RDEMRFB2

RFB1

VIN

VCCRAMP

UVLO

RT/SYNCSS

VCCXENAGNDPGND

COMP FBVOUT

DEMB

CSG

CS

LO

SW

HO

HB

VIN

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1-48

Design Example #2 – Calculation

Texas Instruments – 2014/15 Power Supply Design Seminar

•  Choose switching frequency first •  Calculate the output filter components (L and C) •  Calculate the power stage components (FETs)

•  WEBENCH® •  Helps calculate all of specific values for design •  Allows optimization based on design goals •  Gives estimates for loop response and efficiency •  Provides a complete schematic and bill of materials

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1-49

Design Example #2 – Performance Graphs

Texas Instruments – 2014/15 Power Supply Design Seminar

Efficiency Switching Operation

Loop Response Transient Response

Data is taken with LM5116EVM

VIN = 7 V

VIN = 24 V

VIN = 60 V

VOUT

IOUT (1 A à 6 A à 1 A)

Phase

Gain

VOUT

VSW

2 µs/Div

500 µs/Div

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1-50

Design Example #2 - Schematic

Texas Instruments – 2014/15 Power Supply Design Seminar

C16

100 µF

C8

2.2 µF

C9

2.2 µF

C10

2.2 µF

C11

2.2 µF

C12

1 µF

C13

0.1 µF

C14

1 µF

C17

100 µF

C18

100 µF

C20

100 µF

C21

N/A

C22

N/A

C19

100 µFPAD

VINUVLORT/SYNCENRAMPAGNDSSFBCOMPVOUT

SWHOHB

VCCXVCC

LOPGND

CSGCS

DEMB

21 LM5116

R12

N/A

+5 VDC 7 A

P3VOUT+

P4GND

GNDGND

GND

GND

PGNDAGND

AGND

PGND

TP4

P2

D2

N/A

R1102 K

R121 K

R916.2 K R10

10 K

R41.21 K

R33.74 K

R131 M

C15100 pF

C4

270 pF

C5

100 pFC2

1 µFC7

N/A C3

0.01 µF

C6

0.01 µF

TP1SYNC EN

TP3 123456789

10

20191817161514131211

D1

C1

1 µF

CM

PD20

03 Q1

Q2

L1

5.6 µH

R5N/A

R60 R7

0R110.01

R14N/A

C23

N/A

R810 K

12

JMP1

VIN+ 7 VDC – 60 VDCP1

4 3 2 1

4 3 2 1

9 8 7 6 5

9 8 7 6 5

TP2 PGND

TP5 VCCX

+

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1-51

Fixed Frequency Control

Texas Instruments – 2014/15 Power Supply Design Seminar

Questions? Stay tuned for Variable Frequency!

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