Chip Design Sign-Off For Shrinking TechnologyAnurag Sahai

Managing Director, Vertical Gravity, Naida, UP. Indiaanurags_1999@yahoo.com

Abstract-In today's IC's competitive market place, as technologyis shrinking and we are stepping into 45nm and below, IC'scomplexity is increasing, die areas are also getting larger in orderto incorporate the increased functionality that comes with moreadvanced technology. Due to shrinking design, physicalverification of design such as design rule checking (DRC) andlayout vs, schematic (LVS), may not give accurate result asexpected due to electrical side effects inherent in nanometerprocess technology. Therefore, shrinking designs demandadditional verification before being signed-off for manufacturing.For example, if signal integrity (SI) and other electrical effectsare not controUed, a design will likely suffer from lowerperformance, lower yield, and even functional failure. Any chipfailure after manufacturing will result in expensive mask changesand delays in getting the chip to market. Consequently, mostdesigns today require a nanometer sign-off process, where theinfluence of different electrical effects on the functionality andperformance ofthe design are analyzed before manufacturing.

1. COMPLEXITY DUE TO SHRINKING DESIGN

Implementing 45nm and below design raises significant SI(Signal Integrity) related issues that have to be verified inorder to avoid chip functional failure. These include reducedfeature sizes, decreases in wire pitch, lower power supplyvoltages, and shrinking threshold voltages. With each newprocess technology, more and more levels of wire are packedmore closely together. As a consequence, the fraction of totalwire capacitance represented by lateral coupling increasesdramatically. This in turn is responsible for a dramaticincrease in on-chip crosstalk noise. Another electrical problemin shrinking designs is increased clock frequencies with fasteron chip slew rates. Faster slew rates create more switchingnoise and increase instantaneous power consumption. This inturn puts stress on the power grid, resulting in voltage (IR)drop and electro-migration. Nanometer sign-off is becoming achallenge, uncovering any problems that may have beenmissed during design implementation or that have been causedby last-minute manual design changes.

Nanometer sign-off is a final verification to assure that adesign does not have electrical issues that will result in chipfailure after manufacture. However, finding many problemsonly just before manufacturing could lead to multiple designiterations and delay in manufacturing and market.

As design is shrinking, we can observe increased powerdensity, increased clock frequencies and slew rate, lowersupply voltage, domination of wire to wire couplingcapacitance over ground capacitance, smaller transistorthresholds to decrease transistor delay and because of all thesefactors we can see from figure 1 that crosstalk glitches areincreasing and it gives result of silicon respins, longer designcycle, lower performance and lower yield.

Increased Density and Scaling

• Wire·to·wire coupling capacitance dominates ground capacitance.

• Clock frequencies and slew rates increase.

• Lower supply voltages

• Smaller transistor thresholds

J'LCrosstalk

ICrosstalk Trends

Silicon Respins

Longer DesignCycles.

Lower Penormance6wr-----~~--------~~40~----~------------~220Vl~ O~--~~---,------_T--~...U

Lower Yield0.18 0.15 0.13

Process TechnologyFig. I Crosstalk Trends

II. SHRINKING DESIGN SIGN-OFFREQUIREMENTS

The role of nanometer sign-off is to uncover any problemsthat may have been missed during design implementation orthat have been caused by last-minute manual design changes.Nanometer sign-off is a final verification to assure that a

NIET Journal of Engineering & Technology, Vol. 1, Issue 1, 2012 23

Prevention

Repair

S;9~of' -[

Fig. 2 Flow to fix signal integrity.design does not have electrical issues that will result in chipfailure after manufacture.

45 nanometer and below sign-off is best applied as part of athorough design closure methodology that issues such assignal and power integrity from early chip planning through totap~out, as shown in figure 2. The number of problems founddunng fin~l nanometer sign-off should be small enough to bedealt efficiently, even by means of manual repair.

~he tools used during design implementation to supportdesign closure should be fast and flexible in order to maintaindesi~ pr~ducti~ity. These tools should guide the design'selectn.cal integnty continuously, without major compromisesto d~slgn pe~formance, power, or area. The final sign-off phasereq~lres an integrated tool suite that is production-proven andvalidated against real silicon.

Nanometer sign-off tools used during this phase should bemore thorough and accurate than the design closure tools used?uring implementation. This full-chip examination shouldinclude analysis of the subtle and complex interactions thatoccur between many different electrical effects across manyproc~ss comers. For example, nanometer sign-off shouldpredict how IR drop affects crosstalk-and how this affectstiming, which in turn affects power, which is responsible forIR drop. The key components of nanometer sign-off includeaccura~e 3-D parasitic extraction, full-chip IR drop analysis,full-chip crosstalk analysis, and SI-aware static timing

• Identify imponant SI issues based on chip'smarket requirements

• Decide how to manage SI for critical global signals(power. clock'S. buses. etc.)

• Take SI into account when seleting IP blocks(cells, c:ores. memories. etc.)

analysis (STA) that accounts for the influence of bothcrosstalk and IR drop.

III. 3-D PARASITIC EXTRACTION

Extraction accuracy is largely a function of the relationshipbetween the tool vendor and the foundry and also a function ofthe design representation. Tool vendors need early access toproprietary process information to determine how best tomodel the process and to capture the necessary processcharacteristics. Tools need to use the physical details of designelements, rather than simplistic abstractions. As an example,while it is expedient to provide a simplified model of a port,doing so inherently limits design optimization. Similarly, cellmodels should be instance-specific, not treated as if each cellwere isolated.

From a methodology point of view, getting the most out ofthe silicon requires utilizing the most accurate necessary~hysi.cal information for design iterations. For early designrterations, turnaround time is important and later in the designcycle, accuracy is most critical issue. Using a less accurateextractor to speed iterations can mean increased margin andincreased timing closure risk. An extractor should be fastenough to enable designers to complete block iterations within1-2 hours. It should also complete a full-chip extractionovernight, using multiprocessor computers if necessary to doso. The output from 3-D extraction tools is either a parasiticdatabase or a text me in detailed specified parasitic format

NIET Journal of Engineering & Technology, Vol. 1, Issue 1, 2012 24

(DSPF) or standard parasitic extraction format (SPEF). SPEFis required for coupling extraction, which is critical foraccurate SI analysis. As design sizes increase, so do thenumber of parasitic elements required for accurate analysis.

IV. IR DROP ANALYSIS

IR drop due to parasitic effects, such as resistance orcapacitance, cause a decrease in the current flowing from theVDD (source) input/output pins to the transistors or gates of adesign. An excessive IR-drop can increase the delay oftargeted paths (global effect) and significantly reduce thevoltage reaching a device causing reason for logic failure.

The risk of IR drop increases with the shrinking processtechnologies of nanometer design. With each new generationof process technology, the current demand per unit area of adesign is increased due primarily to shrinking gate-oxidethickness. This, combined with the fact that nanometer designscontain more transistors or gates, adds additional stress topower grid integrity.

The effect of IR drop on chip performance is significant,primarily affecting timing. IR drop compromises the drivecapability of the gates and increases the overall delay.Typically, a 5% drop in supply voltage can affect delay by15% or more. Such an increase in delay is critical when clockskews are in the range of 100 picoseconds. IR drop can makepath delay unpredictable and can even cause the critical pathof a design to change. For this reason, nanometer timingcalculations must take IR drop into account.

IR drop has significant impact on SI. Supply voltagesshrink as nanometer device dimensions are scaled to avoidtransistor punch-through conditions, hot-electron effects, anddevice breakdown. This has resulted in smaller and smallernoise margins. IR drop reduces these margins even further,rendering nanometer designs more vulnerable to SI noiseeffects.

A complete picture of power grid integrity can only beobtained when effects such as IR drop, ground bounce, andelectro migration are computed and analyzed accurately.These effects involve complex interactions across a chip andmust be analyzed at the full-chip level. However, a leading-edge 45 nm design can contain over 10 million gates,processed with eight layers of metal, which could produce aVDD grid approaching one billion RC elements.

Therefore, power grid verification tools must have thecapacity and performance required to analyze detailedrepresentations of such large, complex chips with reasonableturnaround time.

Many power grid verification tools rely onoversimplifications, such as black-boxing embedded IP blocksor using simple power-consumption distribution models, thustrading accuracy for speed. However, because the currentflowing through a chip's power grid doesn't stop at the portsof cells and IP blocks, power grid verification tools must beaccurate to the transistor level while maintaining the speed and

Fig. 3 Gate-level analysis doesn't accurately model IP.De-coulling cap acts a; alocal dleillt' ~UUlCt;S?r--------.-t-4-L~

Mini/Tlzes curert

Fig. 4 Shrinking design impact IR drop analysis.

efficiency required for large-scale nanometer designs, asshown in Figure 3. The ability to pre-characterize the powergrids of library elements facilitates the reuse strategies that arecentral to nanometer design styles.

In the gate-level plot (left), the IR drop in the center of thechip is fairly severe. But the transistor-accurate analysis (right)of the IP's contents and the current flowing through the IPreveals that the IR drop is actually much smaller

We need to understand General robustness of power raildesign (static), Power rail electro migration (static), IR dropimpact on timing (dynamic),Optimal size & location of de-coupling capacitance (dynamic),Trade-off de-couplingcapacitance vs leakage power (dynamic)

This figure 4 shows how de-coupling capacitors are addedto the power rails to minimize IR drop transients. Whathappens is that the de-coupling capacitor acts as a local chargesource to help charge up the load capacitor through the p-channel transistor. This local charge source helps to minimizethe amount of current that is drawn through the resistivepower rails, which helps minimize IR drop transients.

To understand the general robustness of the power rails, astatic approach can be used. This approach will clearlyidentify major weaknesses in the power rails, such as routingthat is too narrow and missing vias or power straps. The valueof the static approach is that it is available very early in thedesign cycle, even prior to signal routmg being completed.

The static approach is also the best solution for power railelectro migration, since electro migration is caused by highaverage currents flowing over a period of time.

The static approach is good down to 130nm, but beyond130nm, a dynamic approach should be used so that the impact

NIET ,Journal of Engineering & Technology, Vol. 1, Issue 1, 2012 25

of IR drop transients on timing can be analyzed. The dynamicsolution also enables to understand where to add or removede-coupling capacitors and evaluate the impact on transient IRdrop and total leakage.

V. CROSSTALK ANALYSIS

Crosstalk analysis considers the effect of wire coupling,increase clock frequencies and slew rates, lower supplyvoltages, smaller transistor thresholds on the performance andfunctionality of a design. The primary source of wire couplingis wire-to-wire capacitances, though, for very high-speednanometer designs, inductive coupling can also be a problem.

q~

~-V-i-ct-im--~-----J

Fig. 5 Crosstalk functional failure

Crosstalk can also cause functional failures. In this example,coupling from attacker A causes a significant glitch on thereset signal such that it resets the flip-flop and destroys thestored logic state. This problem will not show up in logicsimulation, formal verification or timing analysis. Thedesigner is mystified. Isolating the source of a noise inducedfunctional problem can take many months of debuggingresulting in lost time to market.

Due to glitch, there is change (e.g., from logic 0 to logic 1)to appear on otherwise static signals. A glitch has a truefunctional impact when it propagates and is latched before thenext clock cycle, as shown above. Consequently, to verify if adesign has a functional problem due to crosstalk, it is notsufficient just to determine if a signal is subject to a sizeablenoise pulse. The circuit must be tested to determine if thatnoise pulse will propagate and reach a storage element such asa latch or flip-flop. Therefore, effective sign-off crosstalkanalysis must include both accurate noise glitch calculationand noise propagation.

Accurate noise glitch calculation must account for temporaland logical relationships of the aggressor signals, as well asthe holding resistance of the victim driver. When a driver isholding a static logic state, its resistance is larger than when itis switching. Therefore, noise calculations using switchingresistance derived from standard timing libraries over-estimatenoise. A separate cell library characterization step is requiredto calculate holding resistance.

For accurate noise propagation, simulation of the receiverinput noise is required to determine the amount of noise topropagate. Since digital CMOS logic gates are inherentlynoise-immune and act as low-pass filters, most glitches will befiltered before they are latched. Without accurate noise

propagation, the number of functional failures will be greatlyexaggerated, while at the same time, the true crosstalk-inducedfunctional errors easily could be overlooked. Figure 5 shows acomparison of noise failures reported by using a glitch peakthreshold of 30% of supply versus using noise propagation.For these examples, noise propagation reports over 400 timesfewer failures on average. For the largest example, thisreduces the task of tracking down more than 10,000 reportedcrosstalk violations-a task that literally could cost man-weeks-to a far more manageable 40 violations.

9.160 6.50010.832 • > 30% vaa

40Not,. propagation

21

1 1115 nets 174 nets "1.4 nets 457 nots 532 nets180nm 150nm 150nm 130nm 130nm

Fig. 6 Number of crosstalk violations using noise propagation vs. glitch peak.

Other types of crosstalk-induced functional violations arebootstrap noise and double clocking. Bootstrap noise failures .occur when crosstalk on the input of an unbuffered latch pullsa static signal below ground (undershoot) or above supply(overshoot). In such cases, that the logic value stored in thelatch can be destroyed, even when the clock is inactive.Overshoot and undershoot can also cause reliability problemsby over-stressing transistors and causing time-dependentdielectric breakdown (TDDB).

Double clocking occurs when a glitch causes a clock tocross its switching threshold more than once during a singletransition. In this case, even a small crosstalk glitch can causea functional violation due to false triggering of flipflops orlatches. Double clocking can be particularly troublesome forcounters, state machines, and on-chip clock dividers, all ofwhich rely on the fidelity of the clock signal.

Crosstalk Repair Techniques for Glitch and Delay

Victim driver sizing, buffer insertion,aggressor downsizing

Rip-up aggressors and victim spacing

Soft spacing, victim rerouting

Shielding

VI. DESIGN SIGN-OFF FLOW FOR 45NM ANDBELOW

An electrical chip problem can be rooted due to crosstalkand IR drop. Therefore, it is necessary to integrate the noiseand IR drop analysis into a single flow as shown in Figure 9.Following 3-D parasitic extraction, IR drop analysis isperformed to determine the worst-case IR drop for each cellinstance. This information is then used as input to SI awareSTA and for crosstalk-glitch analysis

NIET Journal of Engineering & Technology, Vol. 1, Issue 1,2012 26

Rq:.·upDownsizeiloor~ssnrdriver

Upsizevictimdriver

•....••• '....AAd~ds~'!gOQ_u.•." ";~I- ~~.L1"': t/~/>i,~/<;» I '"/"or ;; RelOute'fr'/

Insert buffer soft spacing

Fig. 7 Crosstalk Repair Techniques

Designimplementation

.•..•.- ."

Fig. 8 Design sign off flow

Since SI-aware STA is dependent on IR drop, it isperformed after IR drop analysis. Unlike traditional static-timing sign-off, SI-aware timing sign-off accurately calculatesdelays in the presence of noise (both crosstalk and IR drop),resolves the interdependency between crosstalk and timingdata (arrival times and slews), and avoids overly pessimisticapproximations. SI-aware timing analysis must also filterunrealistic combinations of SI events, either automatically orvia user control. A timing sign-off flow that blindly usesworst-case data and accumulates all SI delay effects likely willrender an unattainable timing target. Finally, the SI-awaresign-off timing analysis must be supported with the librarydata necessary to permit accurate calculation of SI effects.This data must be readily available from library vendors,and/or easily created via automated library characterizationtools.

As crosstalk glitch analysis is dependent on both convergedtiming windows and slews from SI-aware STA and IR dropanalysis, this check is performed last.

VII. CONCLUSIONS

Physical IC verification for shrinking design 45 nm andbelow requires advanced tools and methodologies in order tocover all its effects. Its success also requires a new set ofimplementation, analysis, and database technologies.

Silicon integrity and IR drop have become most importantfactor in measuring of timing effects due to shrinking 45 nmand below design, and in such case, EM is also an issue forsignals as well as the power grid. An extensible, unifieddatabase provides the foundation for nanometer design,especially since most designs are be digital/mixed-signal. Itneeds to support a rich set of objects, attributes, andrelationships. Perhaps more importantly, it must supportextensibility with native performance. The database and allnanometer tools should support hierarchy elegantly and handle100M or more gate designs efficiently.

No Doubt, shrinking design implementation placesextraordinary demands on design teams to calculate power railelectro migration (static), IR drop impact on timing (dynamic),optimal size & location of de-coupling capacitance (dynamic)and to do crosstalk analysis to measure it effects on timing andchip functionality.

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