Chip Design Traning Plan V1.0

7/31/2019 Chip Design Traning Plan V1.0

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Confidential For Arrive Technologies Customers use only

Chip Design Training PlanChip Design Training Plan

June 2012


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Slide 2Confidential For Arrive Technologies Customers use only

Section I: Basic Chip Design Technology Training

Section II: Product Development Training

Section III: Product Verification Training

ContentsContents


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SectionSection I: Basic Chip Design TechnologyI: Basic Chip Design Technology

TrainingTraining

Back to Contents


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BasicBasic Chip Design Technology TrainingChip Design Technology Training

Subject 1: Verilog LanguageSubject 2: Verilog Coding Standard

Subject 3: RTL Design Guidelines

Subject 4: Testbench Design Guidelines

Subject 5: Telecom Basic

Subject 6: Small design Exercises


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VerilogVerilog Language Training (1)Language Training (1)

Chapter 1 Introduction Major features of the Verilog HDL

Rationale for synthesis policy

Chapter 2 Lexical Conventions

How the language interprets

How to specify lexical tokens White space

Comments

Attribute delimiters

Numbers

Character strings Identifiers

Keywords

Operators


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Chapter 3 Data Types Registers

Nets

Constant values

Chapter 4 Expressions

Operators Operands

Chapter 5 Assignments

Continuous assignments

Procedural assignments

Chapter 6 Gate and Switch Level Modeling Gate and switch level primitives

Declarations

Specifications


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Chapter 7 User-Defined Primitives (UDPs) How a primitive can be defined in the Verilog HDL

How these primitives are included in Verilog models

Chapter 8 Behavioral Modeling

Procedural assignments

Behavioral language statementsChapter 9 Tasks and Functions

Tasks

Functions

Procedures to call tasks and functions in a behavioral model

How tasks can be used like subroutines How functions can be used to define new operators.


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Chapter 10 Disabling of Named Blocks and Tasks Disable the execution of a task

Disable the execution of a block

Chapter 11 Procedural Continuous Assignments

Type of procedural assignment called a procedural continuous

assignmentChapter 12 Hierarchical Structures

How model hierarchies are created in the Verilog HDL

How parameter values declared in a module can be overridden

Macro modules


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Chapter 13 Attributes Attribute framework

Attribute classes

Attribute types

Attribute inheritance

Attribute declaration Attribute and access mechanisms

Chapter 14 Specify Blocks

Verilog HDL constructs in a specify block


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VerilogVerilog Coding StandardCoding Standard (1)(1)

Layout Conventions

Source File Layout

Testbench File Layout

Testcase File Layout

Function Layout Code Layout

Vertical spacing

Horizontal spacing

Indentation

Comments


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VerilogVerilog Coding StandardCoding Standard (2)(2)

Naming Conventions Source, Testbench, and Testcase File Names

Reset Signal Name

Clock Tree Signal Name

Constant Names

Input and Output Names Wire and Register Names

Active Low Variable Names

Complex Conditionals

Complex Conditionals

RTL MandatoryProject Hierarchy


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RTL DesignRTL Design Guideline (1)Guideline (1)

Coding OrganizationCoding Formatting

Design Partitioning

Circuit Concepts

Timing Model

Timing ClosureSynchronous Design techniques

Synchronization Concepts

Single signal synchronization

Synchronization Pitfall

Metastability Bus synchronization

4 Phase Handshaking

2 Phase Handshaking

Handshaking without ACK


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RTL DesignRTL Design Guideline (2)Guideline (2)

Creating Safe State Machine

Pipeline

FIFO Design Guide Line

RAM interface

CPU interfaceCommon Engine

Buffer Management

Introduce Link Buffer Method

Scan Test


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TestbenchTestbench DesignDesign Guideline (1)Guideline (1)Test Structure

Design Data StructureDatabase Structure

Coding Conventions

Testbench Structure

Generator

Generate a frame data stream Generate errors

Control error insertion

Data type in data stream

Analyzer

Scan even FIFO Report Errors

Text display format

Testcase

Test Progress

Test Case Struture


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TestbenchTestbench DesignDesign Guideline (2)Guideline (2)

Memory Test guide line

Test progress on Mem test

Test progress on test

Data generate method

Fault covering

Observe the test result

Run test case

Text display

Wave form display

Short Frame, Scale Down, Test Mode


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Telecom Basic (1)Telecom Basic (1)

Networking, Switching and Transmission Circuit based

Packet based

TDM

PDH:

o

DS1/3, E1/3, M13/E13o Packet mapped

DS3 C-bit, E3 G.832

VCAT/LCAS

o SDH/SONET

PDH mapped (AU/STS, TU/VT) Packet mapped, VCAT/LCAS (HO/LO)


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Telecom Basic (2)Telecom Basic (2)Packet

HDLC/PPP GFP

ATM

PSN:

o Ethernet-based switching

o

MPLS-based forwardingo IP-based (UDP/L2TP) routing

Protection

Linear

SNCP/UPSR

MSSP/BLSR


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Telecom Basic (3 )Telecom Basic (3 )Clock & Synchronization

Jitter & Wander PDH, SDH/SONET

Packet:

o Network

Sync Ethernet

IEEE 1588

o Service

DCR

ACR

Bonding

IMA MLPPP

OAM

QoS


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Section 2:Section 2: Product DevelopmentProduct Development

TrainingTraining

Back to Contents


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Product Development TrainingProduct Development Training

Subject 1: Product RequirementsSubject 2: RTL Design

Subject 3: Testbench Design

Subject 4: Simulation

Subject 5: Device Driver Design


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Section 3:Section 3: Product VerificationProduct Verification TrainingTraining

Back to Contents


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Product Verification TrainingProduct Verification Training

Subject 1: Board Schematic DesignSubject 2: Board Layout Design

Subject 3: Operating System Modification/Porting

Subject 4: Board Bring-up and Debug

Subject 5: On-board Testing


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Chip Design Traning Plan V1.0

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