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Chhatrapati Shivaji Maharaj Institute of Technology, Shedung.
Year: SE [Comp] Subject: DLDA
Question bank with solution –by Revatee Bagade
Unit - 1
1] Convert the decimal number 29410 into its binary number equivalent.
Number 294
Dividing each decimal number by “2” asshown will give a result plus aremainder.
If the decimal number being divided iseven then the result will be whole andthe remainder will be equal to “0”. If thedecimal number is odd then the resultwill not divide completely and theremainder will be a “1”.
The binary result is obtained by placing all theremainders in order with the least significant bit (LSB)being at the top and the most significant bit (MSB)being at the bottom.
divide by 2
result 147 remainder 0 (LSB)
divide by 2
result 73 remainder 1
divide by 2
result 36 remainder 1
divide by 2
result 18 remainder 0
divide by 2
result 9 remainder 0
divide by 2
result 4 remainder 1
divide by 2
result 2 remainder 0
divide by 2
result 1 remainder 0
divide by 2
result 0 remainder 1 (MSB)
This divide-by-2 decimal to binary conversion technique gives the decimal number29410 an equivalentof 1001001102
2] Convert (1101010111001111)2 into hexadecimal system
The following group of binary digits 1101 0101 1100 11112 are much easier to read and understandthan (1101010111001111)2 when they are all bunched up together. Then convert them to hex system(D5CF)16
3] Convert the following Hexadecimal number #3FA716 into its Binary equivalent, and alsointo its Decimal
#3FA716
= 0011 1111 1010 01112
= (8192 + 4096 + 2048 + 1024 + 512 + 256 + 128 + 32 + 4 + 2 + 1)
= 16,29510
Then, the Decimal number of 16,295 can be represented as:-
#3FA716 in Hexadecimal or (0011 1111 1010 0111)2 in Binary.
4] 11010101110011112 convert this binary number to its octal equivalent, (base-2 to base-8).
Binary Digit Value 001101010111001111
Group the bits into three´s starting
from the right hand side001 101 010 111 001 111
Octal Number form 1 5 2 7 1 78
Thus, (001101010111001111)2 in its Binary form is equivalent to (152717)8 in Octal form or (54,735) indecimal no. system.
5] Write a note on Excess-3 & gray code
Excess-3 or 3-excess is binary code (often abbreviated as XS-3 or X3) or Stibitz code (after George
Stibitz) is a self complementary binary-coded decimal code and numeral system. It is a biased
representation. Excess-3 was used on some older computers as well as in cash registers and hand-held
portable electronic calculators of the 1970s, among other uses. Biased codes are a way to represent
values with a balanced number of positive and negative numbers using a pre-specified number N as a
biasing value. Biased codes (and Gray codes) are non-weighted codes. In XS-3, numbers are
represented as decimal digits, and each digit is represented by four bits as the digit value plus 3 (the
"excess" amount):
The smallest binary number represents the smallest value (0 − excess).
The greatest binary number represents the largest value (2N+1 − excess − 1).
Excess-3 arithmetic uses different algorithms than normal non-biased BCD or binary positional
system numbers. After adding two excess-3 digits, the raw sum is excess-6. For instance, after
adding 1 (0100 in excess-3) and 2 (0101 in excess-3), the sum looks like 6 (1001 in excess-3) instead
of 3 (0110 in excess-3). In order to correct this problem, after adding two digits, it is necessary to
remove the extra bias by subtracting binary 0011 (decimal 3 in unbiased binary) if the resulting digit is
less than decimal 10, or subtracting binary 1101 (decimal 13 in unbiased binary) if an overflow (carry)
has occurred. (In 4-bit binary, subtracting binary 1101 is equivalent to adding 0011 and vice versa.)
The primary advantage of XS-3 coding over non-biased coding is that a decimal number can
be nines' complemented (for subtraction) as easily as a binary number can be ones' complemented;
just invert all bits. Also, when the sum of two XS-3 digits is greater than 9, the carry bit of a 4-bit
adder will be set high. This works because, after adding two digits, an "excess" value of 6 results in
the sum. Because a 4-bit integer can only hold values 0 to 15, an excess of 6 means that any sum
over 9 will overflow (carry).
Gray CodeThis is a variable weighted code and is cyclic. This means that it is arranged so that every transition
from one value to the next value involves only one bit change. The gray code is sometimes referredto as reflected binary, because the first eight values compare with those of the last 8 values, but inreverse order.
The gray code is often used in mechanical applications such as shaftencoders.Modulo 2 ArithmeticThis is binary addition with the carry ignored.Converting Gray Code to BinaryA. write down the number in gray codeB. the most significant bit of the binary number is the most significant bit ofthe gray codeC. add (using modulo 2) the next significant bit of the binary number to thenext significant bit of the gray coded number to obtain the next binary bitD. repeat step C till all bits of the gray coded number have been addedmodulo 2the resultant number is the binary equivalent of the gray number
Unit -2
1] State De Morgan’s Theorems
In propositional logic and boolean algebra, De Morgan's laws are a pair of transformation rulesthat are both valid rules of inference. They are named after Augustus De Morgan, a 19th-century Britishmathematician. The rules allow the expression of conjunctions and disjunctions purely in terms of eachother via negation.
In set theory and Boolean algebra, these are written formally as
Bar(A. B) = (barA)+( bar B)
Bar(A+B) = (barA).( bar B)
where
DecimalBinaryGray0 0000 00001 0001 00012 0010 00113 0011 00104 0100 01105 0101 01116 0110 01017 0111 01008 1000 11009 1001 1101
10 1010 111111 1011 111012 1100 101013 1101 101114 1110 100115 1111 1000
A and B are sets,
barA is the complement of A,
Applications of the rules include simplification of logical expressions in computer programs and digitalcircuit designs. De Morgan's laws are an example of a more general concept of mathematical duality.
In electrical and computer engineering, De Morgan's laws are commonly written as:
Bar(A. B) = (barA)+( bar B)
Bar(A+B) = (barA).( bar B)
where:
(.) is a logical AND,
(+) is a logical OR,
the bar is the logical NOT of what is underneath the overbar.
2] Design 8 bit adder.
Though the implementation of larger logic diagrams is possible with the above full adder logic asimpler symbol is mostly used to represent the operation. Given below is a simpler schematicrepresentation of a one-bit full adder.
Single-bit Full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower order ofmagnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bitoperation, each bit must be represented by a full adder and must be added simultaneously. Thus, to addtwo 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks.The addition of two 4-bit numbers is shown below.
Multi-Bit Addition using Full Adder
3] Design 1 bit comparator
Data comparison is needed in digital systems while performing arithmetic or logical operations.
This comparison determines whether one number is greater than, equal, or less than the other number. A
digital comparator is widely used in combinational system and is specially designed to compare the
relative magnitudes of binary numbers.
These are also available in IC form with different bit comparing configurations such as 4-bit, 8-bit,
etc. More than one comparator can also be connected in cascade arrangement to perform comparison of
numbers of longer lengths. Whenever we want to compare the two binary numbers, first we have to
compare the most significant bits.
If these MSBs are equal, then only we need to compare the next significant bits. But if the MSBs
are not equal, then it would be clear that either A is greater than or less than B and the process of
comparison ceases.
For example, the two 2-bit number are A = A1A0 and B=B1B0. If A1 is not equal to B1, then it is
clear that A is greater than B for A1 =1 & B1= 0 or else A is less than B for A0= 0 & B0 =1. At this stage
the process of comparison ceases.
If the MSBs are equal, i.e., A1=B1 only then we need to compare the next significant bits A0 and
B0 and decide whether the number is greater than, less than or equal. So, the comparator produces three
outputs as L, E and G corresponds to less than, equal and greater than comparisons.
Digital comparators can be of two types
Identity Comparator
Comparators that have only one output terminal and produces the output either low or high are
identity comparators.
Magnitude Comparator
Comparators with three output terminals and checks for three conditions i.e greater than or less
than or equal to is magnitude comparator.
Single Bit Magnitude Comparator
A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit
comparator. It consists of two inputs for allowing two single bit numbers and three outputs to generate
less than, equal and greater than comparison outputs.
The figure below shows the block diagram of a single bit magnitude comparator. This comparator
compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G (A>B).
The truth table for the single bit comparator is given below. When A0 B0 = 00 & 11, both inputs
are equal, therefore A=B output will be high. When A0 B0 = 01, B is more than A and hence AB is active.
From the truth table logical expressions for each output can be expressed as
By using these Boolean expressions, we can implement a logic circuit for this comparator using
two AND gates, one NOT gate and one Ex-NOR gate as shown in below figure. AND gates are used to
find whether a binary digit is less than greater than another bit whereas Ex-NOR gate is used to find
whether two binary numbers are equal or not.
In the figure, one AND gate has inputs of A0 (B0) ̅ and another has inputs (A0) ̅ B0. Therefore,
one AND gate output is 1 if A0 > B0 (i.e., A0 =1 and B0 =0) and is zero if A0 < B0 (i.e., A0 =0 and B0 =1).
Similarly, other AND gate output is one if A0 < B0 (i.e., A0 =0 and B0 =1)
and is zero if A0 > B0 (i.e., A0 =1and B0 =0).
The Ex-NOR gate has inputs A0 B0, hence the output of the Ex-NOR gate will be 1 if A0 = B0
and the output will be 0 if A0 is not equal to B0.
4] Design a half adder & a full adder.
Half AdderWith the help of half adder, we can design circuits that are capable of performing simple addition with thehelp of logic gates.Let us first take a look at the addition of single bits.0+0 = 00+1 = 11+0 = 11+1 = 10These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem canbe solved with the help of an EXOR Gate, if you do care about the output, the sum result must be re-written as a 2-bit output.Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below. ‘SUM’ is thenormal output and ‘CARRY’ is the carry-out.
INPUTS OUTPUTSA B SUM CARRY0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR Gatefor the output ‘SUM’ and an AND Gate for the carry.
Half Adder Circuit
For complex addition, there may be cases when you have to add two 8-bit bytes together. This can bedone only with the help of full-adder logic.
NAND gates or NOR gates can be used for realizing the half adder in universal logic and the relevantcircuit diagrams are shown in the figure below.
Full AdderThis type of adder is a little more difficult to implement than a half-adder. The main difference between ahalf-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs areA and B and the third input is an input carry designated as CIN. When a full adder logic is designed wewill be able to string eight of them together to create a byte-wide adder and cascade the carry bit fromone adder to the next. The output carry is designated as COUT and the normal output is designated as S.Take a look at the truth-table.
INPUTS OUTPUTSA B CIN COUT S0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We can see that the output S is anEXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also note thatthe COUT will only be true if any of the two inputs out of the three are HIGH.Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adderwill be used to add A and B to produce a partial Sum. The second half adder logic can be used to addCIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logicproduces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carryoutputs. Take a look at the implementation of the full adder circuit shown below.
Full Adder Circuit
Though the implementation of larger logic diagrams is possible with the above full adder logic a simplersymbol is mostly used to represent the operation. Given below is a simpler schematic representation of aone-bit full adder.
Single-bit Full Adder
Unit - 3
1] Write a short note on multi-vibrators
An Astable Multivibrator is an oscillator circuit that continuously produces rectangular wave without theaid of external triggering. So Astable Multivibrator is also known as Free Running Multivibrator.
Astable Multivibrator using 555 Timer is very simple, easy to design, very stable and low cost. It can beused for timing from microseconds to hours. Due to these reasons 555 has a large number of applicationsand it is a popular IC among electronics hobbyists.
Monostable Mode
In the monostable mode, as the name suggests, it stays in its stable state until and unless an external
trigger is applied. In this mode, the 555 functions as a “one-shot” pulse generator. The best application
of a monostable is to introduce a time delay in to a system.
Applications comprise many things viz., timers, missing pulse detection also included bounce free
switches, touch switches as well as frequency divider, capacitance measurement and pulse-width
modulation (PWM) and many more.
Bistable Mode
In the bistable mode, the IC 555 acts as a flip-flop as it has two stable states. It can be used to store 1-
bit of data. It is not a great choice for implementing a flip-flop.
Astable Multivibrator using 555–Circuit The circuit diagram of a 555 Timer wired in Astable Mode. 8th pin
and 1st pin of the IC are used to give power, Vcc and GND respectively. The 4th pin is RESET pin which
is active low and is connected to Vcc to avoid accidental resets. 5th pin is the Control Voltage pin which is
not used. So to avoid high frequency noises it is connected to a capacitor C’ whose other end is
connected to ground. Usually C’ = 0.01μF. The Trigger (pin 2) and Threshold (pin 6) inputs are connected
to the capacitor which determines the output of the timer. Discharge pin (pin 7) is connected to the
resistor Rb such that the capacitor can discharge through Rb. Diode D connected in parallel to Rb is only
used when an output of duty cycle less than or equal to 50% is required.
Astable Multivibrator using 555 Timer Circuit Diagram
Circuit with Internal Block Diagram
Astable Multivibrator using 555 Timer Block Diagram
Since the Control Voltage (pin 5) is not used the comparator reference voltages will be 2/3 Vcc and 1/3
Vcc respectively. So the output of the 555 will set (goes high) when the capacitor voltage goes below 1/3
Vcc and output will reset (goes low) when the capacitor voltage goes above 2/3 Vcc.
Working
When the circuit is switched ON, the capacitor (C) voltage will be less than 1/3 Vcc. So the output
of the lower comparator will be HIGH and of the higher comparator will be LOW. This SETs the
output of the SR Flip-flop.
Thus the discharging transistor will be OFF and the capacitor C starts charging from Vcc through
resistor Ra & Rb.
When the capacitor voltage will become greater than 1/3 Vcc ( less than 2/3 Vcc ), the output of
both comparators will be LOW and the output of SR Flip-flop will be same as the previous
condition. Thus the capacitor continuous to charge.
Astable Multivibrator using 555 Timer – Working
When the capacitor voltage will becomes slightly greater than 2/3 Vcc the output of the higher
comparator will be HIGH and of lower comparator will be LOW. This resets the SR Flip-flop.
Thus the discharging transistor turns ON and the capacitor starts discharging through resistor Rb.
Soon the capacitor voltage will be less than 2/3 Vcc and output of both comparators will be LOW.
So the output of the SR Flip-flop will be the previous state.
So the discharging of capacitor continuous.
When the capacitor voltage will become less than 1/3 Vcc, the output SETs since the output of
lower comparator is HIGH and of higher comparator is LOW and the capacitor starts charging
again.
This process continuous and a rectangular wave will be obtained at the output.
Capacitor Charges through Ra and Rb.
Thigh = 0.693(Ra + Rb)C
Capacitor Discharges through Rb
Tlow = 0.693RbC
Output Frequency = 1/(Tlow + Thigh) = 1.44/((Ra + 2Rb) * C)
Duty Cycle = Thigh/(Thigh + Tlow)
Where Thigh and Tlow are the time period of HIGH and LOW of the output of 555.
From this we can find that Duty Cycle less than or equal to 50% cannot be obtained.
Some of the important areas of applications of the 555 timer are:
Pulse Generation
Time Delay Generation
Precision Timing
Sequential Timing
Pulse Width Modulation (PWM)
The typical applications of a 555 timer can be differentiated by the mode of operation. Depending on the
mode in which it is operated i.e. either in astable or in monostable mode, some of the applications of IC
555 are:
Frequency Divider
Linear Ramp Generator
Missing Pulse Detector
Pulse Position Modulation
Square Wave Generation
Pulse Width Modulation
Oscillator
Tone Burst Generator
Speed Warning Device
Regulated DC – to – DC Converter
Voltage – to – Frequency Converter
Low Cost Line Receiver
Cable Tester
2] Explain Johnson Ring counter
Johnson Counter
A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connectedto the input to the first. The register cycles through a sequence of bit-patterns. The MOD of the Johnsoncounter is 2n if n flip-flops are used. The main advantage of the Johnson counter counter is that it onlyneeds half the number of flip-flops compared to the standard ring counter for the same MOD.
It can be implemented using D-type flip-flops (or JK-type flip-flops).
100000
Notes:
Enable the flips flops by clicking on the RESET (Green) switch. The RESET switch is a on/offswitch (similar to a room light switch)
Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The CLKswitch is a momentary switch (similar to a door bell switch - normally off).
The D flip flop clock has a rising edge CLK input. For example Q1 behaves as follows:o The D input value just before the CLK rising edge is noted (Q0).o When CLK rising edge occurs, Q1 is assigned the previously noted D value (Q0).
The MOD or number of unique states of this 3 flip flop johnson counter is 6.
Truth Table
State Q0 Q1 Q2
0 0 0 0
1 1 0 0
2 1 1 0
3 1 1 1
4 0 1 1
5 0 0 1
3] Design synchronous up counter
A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state
simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to
connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse
at the exact same time:
Now, the question is, what do we do with the J and K inputs? We know that we still have to maintain the
same divide-by-two frequency pattern in order to count in a binary sequence, and that this pattern is best
achieved utilizing the “toggle” mode of the flip-flop, so the fact that the J and K inputs must both be (at
times) “high” is clear. However, if we simply connect all the J and K inputs to the positive rail of the power
supply as we did in the asynchronous circuit, this would clearly not work because all the flip-flops would
toggle at the same time: with each and every clock pulse!
Asynchronous counter circuit design is based on the fact that each bit toggle happens at the same timethat the preceding bit toggles from a “high” to a “low” (from 1 to 0). Since we cannot clock the toggling of abit based on the toggling of a previous bit in a synchronous counter circuit (to do so would create a rippleeffect) we must find some other pattern in the counting sequence that can be used to trigger a bit toggle:
Examining the four-bit binary count sequence, another predictive pattern can be seen. Notice that justbefore a bit toggles, all preceding bits are “high:”
This pattern is also something we can exploit in designing a counter circuit. If we enable each J-K flip-flop
to toggle based on whether or not all preceding flip-flop outputs (Q) are “high,” we can obtain the same
counting sequence as the asynchronous circuit without the ripple effect, since each flip-flop in this circuit
will be clocked at exactly the same time.
The result is a four-bit synchronous “up” counter. Each of the higher-order flip-flops are made ready to
toggle (both J and K inputs “high”) if the Q outputs of all previous flip-flops are “high.” Otherwise, the J
and K inputs for that flip-flop will both be “low,” placing it into the “latch” mode where it will maintain its
present output state at the next clock pulse. Since the first (LSB) flip-flop needs to toggle at every clock
pulse, its J and K inputs are connected to Vcc or Vdd, where they will be “high” all the time. The next flip-
flop need only “recognize” that the first flip-flop’s Q output is high to be made ready to toggle, so no AND
gate is needed. However, the remaining flip-flops should be made ready to toggle only when all lower-
order output bits are “high,” thus the need for AND gates.
To make a synchronous “down” counter, we need to build the circuit to recognize the appropriate bit
patterns predicting each toggle state while counting down. Not surprisingly, when we examine the four-bit
binary count sequence, we see that all preceding bits are “low” prior to a toggle (following the sequence
from bottom to top):
Since each J-K flip-flop comes equipped with a Q’ output as well as a Q output, we can use the Q’
outputs to enable the toggle mode on each succeeding flip-flop, being that each Q’ will be “high” every
time that the respective Q is “low:”
4] Explain SR,T,JK flip-flop
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs. It is the basic storage element
in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems
used in computers, communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of
data; one of its two states represents a "one" and the other represents a "zero". Such data storage can be
used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state
machine, the output and next state depend not only on its current input, but also on its current state (and
hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed
input signals to some reference timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered).
Although the term flip-flop has historically referred generically to both simple and clocked circuits, in
modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the
simple ones are commonly called latches.
Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a
latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive
going or negative going) of clock edge.
SR NOR latch
A SR latch, constructed from a pair of cross-coupled NOR gates. Red and black mean logical '1' and '0',
respectively.
An animated SR latch. Black and white mean logical '1' and '0', respectively.
(A) S = 1, R = 0: set
(B) S = 0, R = 0: hold
(C) S = 0, R = 1: reset
(D) S = 1, R = 1: not allowed
The restricted combination (D) leads to an unstable state.
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S
and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The
stored bit is present on the output marked Q.
While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant state,
with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is
forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then
the Q output is forced low, and stays low when R returns to low.
SR latch operation[13]
Characteristic table Excitation table
S R Qnext Action Q Qnext S R
0 0 Q hold state 0 0 0 X
0 1 0 reset 0 1 1 0
1 0 1 set 1 0 0 1
1 1 X not allowed 1 1 X 0
Note: X means don't care, that is, either 0 or 1 is a valid value.
The R = S = 1 combination is called a restricted combination or a forbidden state because, as both
NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also
inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition
from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time
relations between the gates (a race condition).
To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) =
(1,1) to one of the non-restricted combinations. That can be:
Q = 1 (1,0) – referred to as an S (dominated)-latch
Q = 0 (0,1) – referred to as an R (dominated)-latch
This is done in nearly every programmable logic controller.
Keep state (0,0) – referred to as an E-latch
Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.
Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S
SR NAND latch
The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state
table:
JK latch truth table
J K Qnext Comment
0 0 Q No change
0 1 0 Reset
1 0 1 Set
1 1 Q Toggle
Hence, the JK latch is an SR latch that is made to toggle its output (oscillate between 0 and 1) when
passed the input combination of 11. Unlike the JK flip-flop, the 11 input combinations for the JK latch is
not very useful because there is no clock that directs toggling.
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T
input is low, the flip-flop holds the previous value. This behavior is described by characteristic equation:
(expanding the XOR operator)
and can be described in a truth table:
T flip-flop operation[26]
Characteristic table Excitation table
Comment Comment
0 0 0 hold state (no clk) 0 0 0 No change
0 1 1 hold state (no clk) 1 1 0 No change
1 0 1 toggle 0 1 1 Complement
1 1 0 toggle 1 0 1 Complement
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency
is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has
application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K
pins are connected together and act as T) or a D flip-flop (T input XOR Qprevious drives the D input).
JK flip-flop
A circuit symbol for a positive-edge-triggered JK flip-flop
A JK flip-flop made of NAND gates
JK flip-flop timing diagram
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the J = K =
1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to
set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination
J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its
current value. Setting J = K = 0 maintains the current state. To synthesize a D flip-flop, simply set K
equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is
therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or
a T flip-flop.
The corresponding truth table is:
JK flip-flop operation[26]
Characteristic table Excitation table
J K Comment Qnext Q Qnext Comment J K
0 0 hold state Q 0 0 No Change 0 X
0 1 reset 0 0 1 Set 1 X
1 0 set 1 1 0 Reset X 1
1 1 toggle Q 1 1 No Change X 0
UNIT - 5
Write a short note on VHDL
VHDL (VHSIC Hardware Description Language) is a hardware description language usedin electronic design automation to describe digital and mixed-signal systems such as field-programmablegate arrays and integrated circuits. VHDL can also be used as a general purposeparallel programminglanguage.
Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASICLibraries) and microwave circuit design extensions.
In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to work on the nextupdate of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibilitywith older versions, this proposed standard provides numerous extensions that make writing andmanaging VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2,1076.3) into the main 1076 standard, an extended set of operators, more flexible syntaxof case and generate statements, incorporation of VHPI (interface to C/C++ languages) and a subset ofPSL (Property Specification Language). These changes should improve quality of synthesizable VHDLcode, make test benches more flexible, and allow wider use of VHDL for system-level descriptions.
VHDL is commonly used to write text models that describe a logic circuit. Such a model is processedby a synthesis program, only if it is part of the logic design. A simulation program is used to test the logicdesign using simulation models to represent the logic circuits that interface to the design. This collectionof simulation models is commonly called a test bench.
VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs(processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is stronglytyped and is not case sensitive. In order to directly represent operations which are common in hardware,there are many features of VHDL which are not found in Ada, such as an extended set of Booleanoperators including nand and nor. VHDL also allows arrays to be indexed in either ascending ordescending direction; both conventions are used in hardware, whereas in Ada and most programminglanguages only ascending indexing is available.
VHDL has file input and output capabilities, and can be used as a general-purpose language for textprocessing, but files are more commonly used by a simulation test bench for stimulus or verification data.There are some VHDL compilers which build executable binaries. In this case, it might be possible to useVHDL to write a test bench to verify the functionality of the design using files on the host computer todefine stimuli, to interact with the user, and to compare results with those expected. However, mostdesigners leave this job to the simulator.
It is relatively easy for an inexperienced developer to produce code that simulates successfully butthat cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is theaccidental production of transparent latches rather than D-type flip-flops as storage elements.
One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, AlteraQuartus, Synopsys Simplify or Mentor Graphics HDL Designer) to produce the RTL schematic of thedesired circuit. After that, the generated schematic can be verified using simulation software which showsthe waveforms of inputs and outputs of the circuit after generating the appropriate test bench. Togenerate an appropriate test bench for a particular circuit or VHDL code, the inputs have to be definedcorrectly. For example, for clock input, a loop process or an iterative statement is required.
A final point is that when a VHDL model is translated into the "gates and wires" that are mappedonto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware beingconfigured, rather than the VHDL code being "executed" as if on some form of a processor chip.
The key advantage of VHDL, when used for systems design, is that it allows the behavior of therequired system to be described (modeled) and verified (simulated) before synthesis tools translate thedesign into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system. VHDL is a data flowlanguage, unlike procedural computing languages such as BASIC, C, and assembly code, which all runsequentially, one instruction at a time.
A VHDL project is multipurpose. Being created once, a calculation block can be used in many otherprojects. However, many formational and functional block parameters can be tuned (capacity parameters,memory size, element base, block composition and interconnection structure).
A VHDL project is portable. Being created for one element base, a computing device project can beported on another element base, for example VLSI with various technologies.