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CHARACTERIZATION AND ANALYSIS OF SMALL GEOMETRY P-CHANNEL MOS DEVICES AT CRYOGENIC TEMPERATURES

Jing Wahg ,

B.SC.; University of Science and Technology of China, 1984

M. Sc,, Case Western Reserve University, 1986

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in the Department

of \--

Engineering Science

O JING WANG 1989

SIMON FRASER UNIVERSITY

March 1989

All rights reserved. This thesis may not be

reproduced in whole or in part, by photocopy

ar other means, without permission of the author.

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The author retains ownership of the copyright L'auteur conserve la pcopriet6 du droit d'auteur in hislher thesis. Neither the thesis nor qui protege sa these. Ni la th&e ni des e>ctraits substantial extracts from it may be printed or substantiels de celle-ci ne doivent &re otherwise reproduced without hisher per- imprimes ou autremerrf remui ts sans son mission. autorisation. .

APPROVAL

Name : Jing Wang ,

Degree: Master of Applied Science (Engineering Science) i

Title of Thesis: Characterization and Analysis of Small Geometry

P-Channel MOS Devices at cryogenic ~ e m p e r a t u ~ e s

Examining Committee:

Chairman: Prof. V. Cuperman - * .

Senior SupervFsor: Prof. Jamal Deen . .

Committee member: Prof. Albert Leung

External Examiner: Prof. Steve Hardy

--

<

Date- Approved:

-> \

P A R T I A L COPYRIGHT L I C E N S E -

I hereby g r a n t t o ~ i rnon ' ~ r a s e r u n i v e r s i t y the r i g h t :to lend

my t h e s i s , p r o j e c t o r extended essay ( t h e t i t l e o f which i s shown b e l w )

t o users o f t h e Simon Fraser U n r v e r s i t y L i b r a r y , and t o make p a r t i a l o r

s i d g l e cop ies o n l y f o r such users o r i ~ n response t o a request f rom the

l i b r a r y o f any o t h e r u n i v e r s i t y , o r ' o t h e r educa t iona l i n s t i t u t i o n , on

. i t s own b e h a l f o r f o r one o f i t s users. I f u r t h e r agree t h a t permissi'on

f o r m u l t i p l e copy ing o f t h i s work f o r s c h o l a r l y purposes may be granted

by me o r the Dean o f Graduate S tud ies . I t i s understood t h a t copy ing

o r p u b l i c a t i o n o f t h i ; work f o r f i n a n c i a l ga in s h a l l n o t be a l lowed .

w i t h o u t my w r i t t e n permiss ion . 4

- , T i t l e o f Thes is /Pro jec t /Extended 'Essay

Au thor :

(name)

Abstract

Crj-ogenic operation' of small 'geometry

(140s) devices provides a powerful way of

systems operating at high speeds. This thesis

charticterisiics of small geometry P-channel -

Metal-Oxide-Semiconductor .

achieving densely packed

examines in detail the DC

MOS (PYOS) devices under

varying biasing voltages and at temperatures between 300K and 77K. *

It was found that short channel effects (on a L-0.6pm device) on

threshold voltages (V,) . subthreshold slopes (S) , substrate bias

mobility degradation consqant (0 ) and substrate current normalized to B

drain breakdown current were weaker at 77K, compared to 300K for varying

channel length dev'ices. However, intrinsic-mobility-surface-degradation

constant ( B o ) , saturation-drain voltages and parasitic-series resistance

( R p ) all increased with decreasing temperature, indicating that new

device technology is required for cyro-PMOS devices. Detailed results

and discussions for varying channel width devices (V=0,9 to 3.4pm) are 2 " .

also presented and validity of the small geometry device models under

various operating conditions are confirmed.

Our results showed a much improved performance and a small

degradation due either to small geometry effect or hot carrier effect,

Y

of the PMOS devices, at 77K; S improved by more than 2.5 times, R P

decreazd from 550 at 300K to 350 at 77K, V (absolute value) increased T

linearly with the temperature at a rate of=1.8mV/K. 6 increased 5 times 0

at 77K comparing that at 300K, indicating surface-roughness scattering

is relatively important at 77K.

Dedication

To my parents

I sincerely thank all the people who helped in making this t5esis

possible, with special thanks to Professor M.J. Deen for his

encouragement, suggestion, patience and constructive criticisms of this r'

work and advice in device physics study. He has provided valuable advice

and this research and has afforded me the j'

I am also thankful t6 Professor Z. X. Yan for his many invaluable -- discussions on MOS theory and for understanding MINIMOS simulation. I

appreciate very much the help of Mr. Z. P. Zuo for implementing part of

the software in PC and giving many instructive hints in the development ,

of the software. I would also like to thank Mr. C. Alakija for his help

in finishing the Semiconductor Parameter Analyzer controlling program.

Most of all, I thank my parents for their love and encouragement. I

would also like to thank my girlfriend, H. Zheng, for her understanding,

and emotional support.

Finally, this research was supported in part by the School of

Engineering Science and Center System Science (CSS) of SFU, by Northern

Telecom Electronics Ltd, Ottawa and b,y Natural Science-and Engineering

Research Council (NSERC) of Canada.

TABLE OF CONTENTS .. .-

* Page . ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i i i

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEDICATION iv

ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

LI'ST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; vii

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i --

1 . INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 HISTORICAL'OUTLINE 1 . 2 DEVICES AT LOW TEMPERATURES . . . . . . . . . . . . . . . . . . . . 1.3 PMOS VS NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 MOTIVATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 . THEORY OF MOS TRANSISTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2 . 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 . 2 .PRINCIPLES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 2.3 THEORY OF PMOS TRANSISTORS .................... 2 . 4 LOW TEMPERATURE EFFECTS . . . . . . . . . . . . . . . . . . . . . . . 2 . 5 -SHORT CHANNEL EFFECTS . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 6 NARROW CHANNEL EFFECTS . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . TEST DEVICES

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 TEST DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 PACKAGING . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . EXPERIMENTAL DETAILS

4 . 1 ROOM TEMPERATURE MEASUREMENT SYSTEM . . . . . . . . . . . 4 . 2 *LOW TEXPERATURE MEASUREMENT SYSTEM . . . . . . . . . . . . 4 . 3 SYSTEM CALIBRATION AND ACCURACY . . . . . . . . . . : . . . .

5 . SOFTWARE USED FOR EXTRACTING PARAMETERS . . . . . . . . . . . . . 5. 1 VISUAL EDITOR PROGRAM (VEP) . . . . . . . . . . . . . . . . . . . 5.2 PARAMETER EXTRACTION PROGRAM (FET) .\ . . . . . . . . . . 5 . 3 PARAMETER EXTRACTION PROGRAM (FETW) . . . . . . . . . . .

I 6 . RESULTS AND DISCUSSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 . 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 LINEAR CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . 6 . 3 SATURATION CHARACTERISTICS 6 - 4 STRESSED CUCTERISTICS ......................

7 . CONCLUSIONS AND RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . .

7 . 1 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.2 RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

8 . REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1

9 . APPENDICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Fig. 1-1

Fig. 1-2

Fig. 2-1

Fig ,2 - 2 Fig. 2-3

Fig. 2-4

Fig. 2-5

Fig. 2-6

Fig -2% 7

Fig. 2-8

Fig. 3-1

Fig. 3-2

Fig. 3-3

Fig.4-1

Fig.4-2

Fig.5-1

Fig. 5-2

Fig.6-1

Fig. 6-2

Fig.6-3

Fig.6-4

Fig. 6-5

Fig.6-6

Fig. 6-7

Fig.6-8

Fig.6-9

LIST OF FIGURES --

RELATIVE RESISTIVITY VS. TEMPERATURE

THERMAL CONDUCTIVITY VS. TEMPERATURE

STRUCTURE OF A PMOS DEVICE L

ENERGY DIAGRAM OF A PMOS DEVICE

SURFACE CHARGE DENSITY VS. SURFACE POTENTIAL

ENERGY DIAGRAM OF PMOS DEVICES AT RT AND LNT -.I

CHANNEL DIAGRAM OF SHORT CHANNEL PMOS DEVICES

CHANNEL DIAGRAM FOR PINCHOFF EFFECT

VELOCITY OF CHARGE CARRIER VS. E-FIELD

DIAGRAM FOR CALCULATING W

DOPING PROFILE OF THE PMOS DEVICES USED -

POTENTIAL PLOT OF THE PMOS DEVICES USED

DEVICE LAYOUT

BLOCK DIAGRAM OF THE TESTING SYSTEM

LOW TEMPERATURE PROBE

DIAGRAMS FOR EXTRACTING R and L P

BLOCK DIAGRAM OF FET

DIAGRAMS FOR

RESULT OF V T

RESULT OF V T

RESULT OF V T

RESULT OF V T

V VS. T FOR T

V VS. T FOR T

V VS. T FOR T

V VS. T FOR T

EXTRACTING VT

VS. L AT T- 300K

VS. W AT T- 300K \

VS. L A T T- 77K

VS. W AT T- 77K '

VARYING L DEVICES AT V -0 BS

VARYING L DEVICES AT V -4V BS

VARVING w DEVICES AT vBS=o VARYING W DEVICES AT V -4V

BS

Fig. 6-10 RESULT OF a AND a3 VS. VBS AT T= 300K 1

Fig. 6-11 RESULT OF al AND a VS . VBS AT T= 77K 3

Fig.6-12 RESULT OF a VS. T 1

Fig.6-13 RESULT OF a, VS. T

Fig:6-14 RESULT OF V VS. L AT DIFFERENT V T DS

Fig.6-15 RESULT OF V VS. W AT DIFFERENT V T DS

(vii)

0 r,

Fig. 6 - 16 RESULT OF G vS? T FOR VARYING W DEVICES m

Fig. 6- 17 RESULT OF G -VS. T FOR VARYING ' L DEVICES ,- m

Fxg.6-18 RESULT OF BO VS. T -5'

Fig. 6-19 RESULT OF Bo VS. T-'

Fig. 6 - 20 RESULT OF SURFACE MOBILITY p VS . T 0

Figp-21 RESULT OF SURFACE MOBILITY po VS. T-' c-

Fig.6-22 RESULT OF BB VS. T FOR VARYING L DEVICES ~ i ~ . k - 2 3 RESULT OF B VS. T FOR VARYING W DEVICES

B Fig.6-24 AL AND AW VS. T

Fig.6-25 p VS. T FOR 2 SHORT L DEVICES AT VBs-0, 4V ef f -

Fig.6-26p VS. T FOR2 NARROWWDEVICES A T V -0, 4~ ef f BS

Fig.6-27 R VS. T P

Fig.6-28 S VS. T FOR SHORT CHANNEL DEVICES

Fig.6-29 S VS. TFORNARROWWIDTHDEVICES *

Fig.6-30 RESULT OF S VS. L AT T- 300K

Fig.6-31 RESULT OF S VS. L AT T- 77K

Fig.6-32 RESULT OF S VS. W AT T- 300K

Fig.6-33 RESULT OF S VS. W AT T- 77K

Fig.6-34 COMPARISON OF S WITH L AT T- 300K AND 77K

Fig. 6-35 COMPARISON OF S WITH W AT T- 300K AND 77K \

Fig.6-36 DEFINITION OF VBD

Fig.6-37 V VS. T FOR VARYING L DEVICES AT VG;2.5V BD

Fig.6-38 VBD VS. T FOR VARYING L DEVICES AT V =5.5V GS

Fig. 6 - 39 VBD VS . T FOR VARYING W DEVICES AT V -2.5V GS

Fig.6-40 VBD VS. T FOR VARYING W DEVICES AT V x5.W GS

Fig.6-41 CROSS SECTION OF WIDE AND NARROW WIDTH DEVICES

Fig.6-42 RESULT OF V VS. L BD

Fig.6-43 RESULT OF V VS. W BD

Fig.6-44 I (AT V ) VS. T FOR VARYING L DEVICES SUB BD

Fig.6-45 I (ATV ) VS. T FORVARYING WDEVICES SUB BD

Fig. 6 -46 ISm/IBD (AT VBD) VS . T FOR VARYING L DEVICES Fig.6-47 ISUB/IBD (AT V ) VS. T FOR VARYING W DEVICES

BD

Fig.6-48 V D , SAT

VS. L FOR V -2.5, 5.5V AT T- 300K AND 77K GS

Fig.6-49 V D . SAT VS. W FOR V -2.5, 5.5V AT T- 300K AND 77K GS

Fig.6-50 AL (DUE TO PINCHOFF) VS. L

Fig.6-51 IMPACT IONIZATION COEFFICIENT a VS. L I

Fig.6-52 SATURATION VELOCITY vsT VS T %

(vi i i)

TO.

71.

72.

@ 73.

74.

75.

76.

77.

78.

79.

Fig.6-53 STRESSED V VS L (2 HRS DC STRESS) T

145

Fig. 6-54 STRESSED V VS W (2 HRS DC STRESS) d

T 146

Fig.6-55 STRESSED G VS. T FOR L (2 HRS DC STRESS) m - - ,

148

Fig.6-56 STRESSED G VS. T. FOR W (2 HRS DC STRESS) m

149 -

Fig.6-57 STRESSED po VS. T (2 HRS DC STRESS) 150

Fig. 6-58 STRESSED 6 VS . T (2 HRS DC ISTRESS) 0

151

Fig.6-59 STRESSED S VS. T FOR L (2 HRS DC STRESS) 153

Fig.6-60 STRESSED S VS. T FOR,W (2 HRS DC STRESS) 154

Fig.A-1 ENERGY DIAGRAM FOR CALCULATING FLAT-BAND VOLTAGE - 168

Fig.D-1 CALCULATED LATERAL DEPLETION WIDTH VS. T 176

LIST OF TABLES

Page .

. . . . . . . . . . . . . . . 1. -Table 4-1 NOISE CURRENT OF THE SYSTEM 54

. . . . . . . . . . . . 2. Table 6 - 1 SOME PARAMETERS EXTRA~TED vs T. 155

3. Table 6-2A SOME PARAMETERS EXTRACTED VS. DEVICE GEOMETRY SIZE

. . . . . . . . . . . . . . . . . AT ROOM TEMPERATURE

4. Table 6-2B SOME PARAMETERS EXTRACTED VS. DEVICE GEOMETRY SIZE

AT LN TEMPERATURE 157

CHAPTER 2 INTROC~UCTION

Low temperature operation of MOS provides a means of achieving =P

improved performance, increased reliability, and higher density of+ ICs

for both digital 'and analog applications. In the past, the lack o+f . a -

detailed studies of MOS devices, especially of PMOS devices at cryogenic

resulted in only limited low temperature applications af temperatures,

CMOS circuits and sys tems .

1 .I HISTORICAL OUTLINE \

Although semiconductor devices (e.g, transistors) have been

developed for more than five decades [I-11, a thorough investigation of

the design considerations of MOS devices and circuits for low

temperatures (or cryogenic) applications only began in the late 70's

[I-21. However, a detailed discussion of the advantages and properties

of 'Gryogenic operatipn of semiconductor circuits 'were done by A.K.

~otischer , [ I -31 in 1964. Since then several other authors [l-4 to 1-61

have described the potential advantages of operating integrated circuits

at low temperatures. This research was followed by the first systematic B

study of cryogenic operation of the N-channel MOS (NMOS),devices by F.H.

Gaensselen et a1 of IBM [I-21, in which some of the theoretical problems

such as the carrier freeze-out effect were discussed. After that, a

large number of papers was published ..on the cryogenic operation of MOS

devices, mostly NMOS devices [I-?, 1-83 . There was even a special issue

on ldw temperature semiconductor electronics in IEEE transaction on -

Electron Devices in January 1987. This rapid development of low

temperature MOS circuit operations is in part propelled by the

requirement of very large scale integration ( V L S I ) circuits. The .

recently developed high Tc superconducting materials which can bp

potentially used as interconnect materials [ I - 9 1 will undoubtedly impact

low temperature CMOS technology.

- *

1.2 MOS DEVICES AT LOW TEMPERATURES

To date MOS technology has progressed at an extremely rapid pace,

in terms of both speed and integration level because the silicon ,

technology (used in fabricating MOS devices) is today's most mature -

technology in the semiconductor industry that makes sub-micron channel

length MOS devices possible which greatly increases the speed of the

devices and circuits.

For MOS devices the improvements of low temperature operation ared

due to the change of the physical properties of the materials used in

\ the devices, the major ones of which are briefly described below.

-

Some of the commonly used materials for MOS device? are

crystalline sili'con, a mature semiconductor material, and aluminum, or

polysilicon. In Fig.1-1 is shown the temperature dependence of relative

+ resistivity of aluminum, the n doped silicon and polysilicon. The

resistivities of these materials all decrease with decrea,sing

temperature. The resistivity of aluminum shows the largest improvement

+ by a factor of -10 on cooling from 300K to 77K. For p doped silicon,

+ the variation of resistivity with temperature is similar to that of n

polysilicon. This property of decreasing resistivity w.ith temperature < very useful, since it increases the operational speed of the system

through-a reduced signal transmission delay at low temperatures. Fig.1-2

shows that the thermal conductivity of silicon increases at low

Temperature (K)

Fig.1-1 Relative resistance as a function of temperature for some + +

commonly used materials in VLSI circuits. Note that n or p -doped

silicon used as the drain and source material in MOSFET and guard rings

show a decreased resistance at 77K comparing to that at 300K.

Temperature (,i.O

Fig.1-2 Thermal conductivity of silicon and aluminum, a commonly used

material as interconnect. The rherrnal conductivity (k) of t5ese

macerials decrease as the temperature is lowered to 77K.

4

temperatures, with its peak value dependent on the doping of the

silicon. This variation of thermal conductivity ( k ) with temperature is

very important, because, as the integration level of the circuits

increases, heat dissipation becomes a serious problem. However, by

immersing the ci rcuits into liquid nitrogen (T-77K) , the higher thermal

, conductance of the semiconductors allows a higher degree integration of

circuits [I-101.

At low temperatures, phonon scattering in silicon becomes less

important, when compared to that at room temperature, because, at room

temperature, carrier mobility is dominated by phonon scattering relative

to the other scattering mechanisms. This implies a higher carrier

mobility at low temperatures, resulting in an increase in the

operational speed of the circuits and systems

Any thermal activated degradations, such as electromigration,

chemical reaction and interdifussion, decreases exponentially with - temperature [ I - 2 1 . In addition, low temperature operation of MOS devices

also means a reduced total noise-level of the system, even though noise

mechanisms have complicated temperature dependencies.

Another important advantage of cryogenic environment is the

improved subthreshold region (turn on/off behavior) of MOS devices. More

and more people realized that temperature can be used as a design

parLmeter. This property of sharper subthreshold region is even more

important than the improvement of mobility mentioned above. We know

that, to achieve VLSI and ULSI the individual transistor has to be

shrunk foll~wing certain down-scaleing rule, in which the device

dimensions, applied power level, and oxide thickness are reduced. By

doing so, it is expected that the performance can be improved -

.;'

accordingly. However, some intrinsic non-scaling characteristics hinder

the expected result; for example, the subthreshold slope is almost

independent of geometry scaling down. This non-scaling subthreshold

slope may constrain lowering the power level that prevents further down

scaling of the devices. Low temperature operation of the devices provide <

a uniqtie way to scale down t6is parameter, along with other scaled

device parameters, resulting in a desired higher performance circuits or

systems [l-21.

Because the freeze-out effect occurs in the bulk semiconductor at

low temperatures, the induced-parasitic-bipolar action inside the MOS

device is much reduced, and the latch-up problem can even be neglected

in cryogenic operation.

However, low temperature environments also bring some negative

effects to the device performances, and several degradation effects are

more severe at low temperatures. Among them are the hot carrier-induced .A

-A breakdown and carrier freeze-out effect.

As temperature is lowered, the charge carriers suffer less-

scattering, thus gaining high energies without being scattered, and this

increases the mobility, but, on the other hand, these high-energy

carriers (known as hot carriers) also degrade the performance of the

devices by interacting with interface states and by being trapped in the

oxide, causing the characteristic of the device to be unstable. For more

reliable cryogenic CMOS circuit and system design, special care in

designing these low temperature devices is required [l-111.

Reviewing some concepts of semiconductor physics 12-12 ] , we found

chat, in a semiconductor, the mobile carrier concentration is extremely

sensitive to the temperature; for non-degenerate carriers, the

concentration is related to the tempeGature exponentially. As 'the

temperature is lowered, the number of carriers will decrease

drasticalJy, and this will degrade the devices transfer characteristics,

but careful study [ I -111 shows that, for some optimized design of the

device, the carriers in the channel actually do no; .have significant @ \

\ reduction, and a detailed discussion will be given in chawer 2.

Low temperatures usually mean temperat&re (T) < 100K. In this -

work, liquid nitrogen (LN) was chosen as the coolant so that the minimum

available temperature is 77K. Not operating the MOS devices at even

lower temperatures, for example, T < 50K, is because of the following

considerations. J

1. Because the bulk mobility of silicon peaks at temperatures

abou,t loOK, lowering the temperature further does not improve' the

deSices very much.

2. Too low a temperature will cause more low temperature effects-

e . g . kot carrier effect and freeze-out effect.

3. New type of supercanductors have a transition temperature Tc of

> l o O K . It is not necessary then to cool the devices down to < 50K to -

achieve desired performances.

4. From an economic and engineering point of view, W is much

cheaper a coolant than liquid Helium (Me) , and the cooling system for

M e is much more complicated than that for W. It is thus more practical

to implement LB cohing system than LHe ones. /

1.3 PMOS vs NMOS

CMOS devices (consisting of one PMOS and one NMOS transistor) are

nominal among other MOS structures. It has ~ h e least power consumption S

(no direct current path from ground), symmetric static

charwteristic (higher noise immunity), and excellent power-delay - product.

Due to the complexity of the CMOS structures, NMOS and PMOS

devices are studied individually. However, most of the research to-date

have been carried out on NMOS devices because, the carrier mobility of

conventional NMOS devices is much higher than that of PMOS devices. This

is largely due to the fact that effective mass of electrons is smaller L

> than that of holes. It is, however, not always true for small geometry

devices. Chatterjee et a1 [I-131 have found that; for sub-micron

devices, the saturation mobility of PMOS actually is comparable or even

higher than that of NMOS because i) electrons are more susceptible to

velocity saturation than holes, and hence the velocity of the electrons

reach the saturation value at a lower bias than hole's; ii) electrons

are more susceptible to hot carrier effect than holes, and this will

cause the NMOS characteristics to be unstable.

Some of the comparisons of NMOS and PMOS devices, used as a

reference, are listed below:

1. For conventional devices, NMOS has a higher carrier mobility,

and hence higher operational speed than PMOS.

2. For Sub-micron devices, however, PMOS devices have a comparable

9 saturation mobility with that of NMOS devices.

3. PMOS is less susceptible to high field, thus its characteristic

has less degradation after stress.

4. PMOS has more than twice the breakdown voltage than the same

geometry NMOS' [l-141 , implying tha;: PMOS is more suitable for sub-niicron

devices with the capability of coupling conventional drices (VDD - 5V).

5. PMOS has a comparable subthreshold characteristics with NMOS.

6. PMOS has a higher V than NMOS. D , s a t

7. PMOS has less short-channel modulation because of greater

saturation electr,ic field E . .- - C

1.4 MOTIVATION x

, This research is mostly motivated by the fact that only small

P fraction of the research on MOS devices have been concentrated on PMOS

devices. This clearly creates an imbalance in the development of small

geometry CMOS devices and the cryogenic performance of these devices. It

is also motivated by the improvement of the performance of MOS devices

at low temperatures [I-15 to 1-24]. The purpose of the research is to

carry out a detailed investigation of both short channel and narrow

width PMOS devices under different biasing conditions and at temp.erature

from 77K to 300K. The remaining of this thesis details the relevant

, \ mechanisms of the study and the results.

Chapter 2 described the theories of the MOS devices f ~ m linear to

saturation region of operation, and of small geometry effects and low

temperature effects. Chapter 3 described the devices used for this study

and chapter 4 described the experimental setup for the measurements. In

chapter 5, a description of the two most important software tools

developed for the thesis work was given. Chapter 6, the main chapter, ,

presented and discussed moit of the impo;tant results- obtained;; Finally

chapter 7 gave -the conclusions from this research and also recommended

future work to be undertaken.

CHAPTER 2 THEORY OF MOS TRANSISTORS

2.1 INTRODUCTION

The MOS transistor is one of the most important devices in today's

VLSI circuits. It has some -unique properties th'at other devices do not

have, such as low static power consumption, high degree of integration -

and advantageous cryogenic operation.

The principle of the surface field-effect! transistor (FET) was

first proposed by Lilienfeld [1-11 and Heil [Z-11 in 1930, and

subsequently studied by Shockley and Pearson [2-21 in the late 1940s. -.

Kahng and Atalla [2-31 proposed and fabricated the first MOSFET using a

thermally oxidized silicon structure. The basic device characteristics

have been studied subsequently by Ihantola and Moll [2-4,2-51, Sah

[2-61 , and Hofstein and Heiman [2-71 . The technology, application, and

device physics have been reviewed by

[ 2 - 9 1 , and Brews [2-101.

The basic structure of a PMOS

Wallmark and Johnson 12-81, Richman ( '\

transistor is shown in Fig.2-1. It

of {a-type semiconductor substrate is a four terminal device consisting

+ and two p regions, called source and drain, respectively. The 'metal'

contact on the top is called gate terminal usually made of metals (e.g.

Al), silicides.such as polysilicon material. Under the gate terminal is 4 -

the oxide insulation layer generally made of SiO . Below the oxide and 2

between the source and is a thin layer which forms the device's

channel under appropriat% biasing conditions. The basic device

parameters are the channel length (L) measured as the distance from

drain to source; the channel width (W); the oxide thickness. (d); the

4 channel depth (r,i) and the substrate doping (N in PMOS). In an actual

2 J D

Gate Oxide / D r a i n

subs t ra te

-%

Fig.2-1 Basic s t r u c t u r e of a PMOS t r a re ference [2-111) \

circuit, there is a thick oxide region (field oxide) around each device

to isolate it from other transistors. -

The source terminal is used as a' reference. When a negative voltagP s

is applied to the drain and if a negative voltage is applied to the - gate

so that a surface inversion layer is formed, there will be zi current

flow from source to drain. The amount of current can be controlled by -

,the gate bias. Basically the conductance of the channel is controlled by -

the processing parameters, the terminal bias conditions and the

temperature of operation. 'I

f

hergy band theory can be used here as a convenient way to -

illustrate the operation of the transistor. Fig. 2- 2 (a) shows a

top-to-bottom view of a PMOS transistor. Fig.2-2(b) shows the energy

diagram of the transistor without any biasing, the same diagram for two

diodes connected back-to-back. Fig.2-2(c) shows that under the gate

bias, the channel is in inversion region and the potential barrier is

lowered but still in equilibrium. If a negative voltage applied to the

drain, the charges will flow throllgh the channel to the drain, forming

I (Fig.2-2(d)). The amount of the current is determined by both gate DS

and drain biases. A more quantitative representation of the operation of -

the MOS devices will be given in the next section.

-

The electric potential distribution in a semiconductor can be

described by the Poisson's equation

where $ is the

electric charge

semiconductor.

electric potential in the semiconductor, p ( r ) is the

density in the device, and E is the permittivity of the s

* In the following derihtion, one dimensional. theory was used to i

simplify the derivation, although more rigorous results can be obtained

by solving the 2-D or 3-D Poisson's equation.

consider - a MIS (metal- insulator- semiconductor) structure, under

equilibrium condition, the charge density is

+ where N and N- are the densities of the ionized donor and accepters,

" D A

respectively, p and n are the densities of mobile holes and electrons, n n -

respectively, in the n-type semiconducting material. In' the bulk of

semiconductor, charge neutrality requires

where n and p are the corresponding electron and hole densities in no no

the bulk.

Using solid state physics theory [I-111, for arbitrary electric

, potential $, we have

uhers 9 - q / k ~ , q i's ihe electric charge, k is Boltzmann's constant and

T is teEperature, all in S I units.

Fig.2-2 Two dimensional energy band diagram uf a PMOS d

( d 1

evic e. (a) De

configuration (b) ~n up side down energy diagram of the device at , flat-band condition. (c) Device is in equilibrium condition under a gate

bias. (d) Device is in nonequilibrium condition under both gate and

drain biases (indicated by the split of the Fermi energy of electrons

and holes in the drain depletion region (From reference[Z-111).

Note: In the figure the Energy axis is opposite to conventional

direction.

z4

N o w t h e P o i s s o n ' s e q u a t i o n b e c o m e s , w i t h t h e h e l p o f E q . ( 2 - 2 ) t o

Solving the above equat ion, we have

Because the cu r ren t is- c l o s e l y r e l a t e d t o the charges i n - the

channel, we w i l l der ive the r e l a t i o n between the charge and the e l e c t r i c \ I

p o t e n t i a l .

\

From the above equat ion, we found t h a t t h e t o t a l su r face charge

dens i ty under the oxide Q i s S

where

and

subsc r ip t s i n Eq.(2-7) means t h a t the p o t e n t i a l i s taken a t t he sur face

o f the device.

we are interested most from the Zigure is the strong inversion when 1,6 5 a

$,, and Q -exp(-qtj /2kT). The condition for strong inversion is 8 8 L

ph -.

2kT - n tj S (inv) = 2 t B - g ln[e)

In the above equation, the application of a substrate bias V is easily BS

treated by changing the surface potential $ to ($ + V ) . s s BS

So the minimum gate voltage causing the channel in strong

inversion is

where V is the voltage drop across, the gate capacitor. ox

Generally Eq. (2-11) is not the channel inversion condition because

of the following reasons: 1) the work function of the semiconductor may

not equal to that of gate material; 2) the total trapped charge density

in the oxide; 3) the channel implant. Accordingly V has to change to GS

compensate for these effects.

The work function difference between the polysilicon gate material

and the substrate material in MOS devices 4 ,(see Appendix A), is ms

Q The total oxide charge density Q shifts, the turn-on voltage by - -2

0 C '

(C is the oxide layer capacitance per unit area), thus the total shift ox

in the turn-on voltage due to these two effects of 4 and Q gives: ms 0

h

Fig. 2-3 Variation of the total surface charge density in the channel as

a function of the surface potential $ at T- 300K; as indicated in the S

figure that w h e n $ = 2$B, the surface charge density increases S

abruptly. (From reference[2-111)

where V is known as the flat band voltage, because when V - Vfi, fb GS the

energy band is flat from bulk to the surface of the semiconductor.

The surf ace charge density is composed o f two parts, the inversion

layer charge density Q and depletion layer charge density Q I B '

QI plays the dominant role in the &rong inversion conduction.

The total current in the channel is composed of two parts, namely - -

I = I + I t o t a l ,d.ifussion d r i f t

f - The first term is dominant in weak inversion region, and the second is

dominaqt in strong inversion r.egion. Hence, in strong inversion region,

the current component I d r i f t

[ 2 - 3 8 1 is

a4 ( x ) I = I = W-p-Q,

DS d r i f t ax

here Q is very close to Q in strong inversion region [ 2 - 3 8 1 . I s

Integrating Eq.(2-16) along the channel, we have

which, when evaluated (see Appendix B), gives:

where

-

is called body effect constant.

Eq. (2-18) is the basic equation to evaluate most of the important

linear parameters of the devices. Next we will find its approximate form

under different biasing conditions.

For small V (IvDsl<l$ I ) , Eq. (2-18) reduces to the following, DS

where

and V is called threshold voltage given by T

For even smaller V Eq.(2-20) can be reduced further to give DS '

Substituting 3 in Eq.(2-22) with Eq.(2-lo), we have . 8

This is the well known expression for long channel threshold

voltage. We will see, in the next section, that the expression for small

geometry is a modification of Eq.(2-25).

a-

2.3.1 SATURATION CHARACTERISTICS

In Eq,.(2-20), if VDs was increasing while V is constant, at some GS

point, V = V I no longer increases with VDS. This voltage DS DS,sat ' DS

V called saturation voltage, is extracted by setting dI /dV - DS, s a t ' DS GS

0 in Eq.(2-20), and is given as

v - v v - - GS T DS , s a t

1 + 5

The corresponding saturation current I is DS, s a t

W I - - - DS , s a t L Cox 2(1 + 6)

2.3.2 SUBTHRESHOLD REGION I

In the subthreshold region, the channel is in weak inversion, and

the dominant current component is that of diffusion, This region is

important because it measures the turn-on/off characteristic of the MOS

devices. In particular for scaled devices, this characteristic becomes b

important, because poor subthreshold region will limit the scaling

of the power level and performance of the devices.

This subthreshold current I ' can be written as DS '

where A is the area of the cross section of the channel, and D is the P

diffusion coefficient of holes in the channel.

A very important parameter, the subthreshold slope, S, used to

measure the steepness of the subthreshold region, is defined as

For long channel devices, S can be derived as (see Appendix C)

where C (11, ) is the depletion capacitance evaluated zt the surface D s

potential $ . s

CHANNEL MOBILITY p. -

Mobility is one of the most important performance parameters,

because, not only does it determine the gain factor of the transistor,

but it also is a very important physical quantity used in studying

carrier transport phenomenon since the mobility is very sensitive to

almost all the processing parameters, device dimensions, temperature bf

the operation, biasing conditions a ~ d saturation velocity. Since the

mobility is closely related to the transconductance, the gain factor of

I

the transistor, a detailed study of the mobility is essential. A brief

discussion of the mobility will be given here, and small geometry I

modulation and temperature effects on the mobility will be discussed in

the following sections.

Mobility (p) reflects the resultant effects of different

scattering mechanisms. Among them, phonon scattering, impurity

ionization scattering and surface scattering are the more important

ones .

Mobility decreases with increasing effective transverse field E , X

defined as the field averaged over the electron distribution in the

inversion layer, and is given by

At room temperature, the surface mobility p can be described as S

' " i + e i ~ ) x eff

t

where p is the low fie{d mobility, and 0 is a fitting parameter. 0

With

and

we, have

ti O X l/2+ 1

x e f f E T ( vGs s

Substituting E in Eq.(2-32) with Eq.(2-35), we have X

where B is a new fitting parameter, also referred as the surface 0

1 degradation factor.

In the literature [ Z -381 , it has been suggested that a more

appropriate semi-empirical relation of p on B and 8 is s 0 B

P

where 0 is a fitting parameter. p is sometimes written as p for short. B s

The transconductance G and channel conductance G by definition, m D '

are

and

. .-

respectively, using Eq.(2-23):

f

2.4.1 INTRODUCTION

When ambient temperature is reduced, the device's characteristics

experience a significant change. The change in general is beneficial,

but it also has some broblem~. The most beneficial change of the

device's characteristic is its improved subthreshold slope, carrier

mobility and transconductance. These improvements translate onto a

faster, more reliable and compact electronic circuits and systems.

However, two major effects that may potentially degrade the

performance of the MOS transistors are the carrier freeze-out and hot

carrier effect. ,In the following sections a survey will be given on , .

these two effects and their impact on cryogenic device designs

2.4.2 FREEZE-OUT EFFECT

As the device's temperature is lowered, the mobile charge density I

of a light or medium-doped (also called non-degenerate) semiconductor , I

will decrease drastically, following the Fermi-Dirac statistics [I-111.

At typical doping levels this decrease of the electric conductivity

causes the gain of bipolar devices to degrade to a revel that makes low 1

\ x

\ temperature (T < 100K) operation of these devices unlikely, also makes

some types of MOS transistors nonoperative, for example, the depletion 1

mode MOS transistors. -I

However, the freeze-out effect is not severe for the enhancement

mode MOS transistors, because, the energy %nd bending [l-21 makes the

donor states still higher than the Fermi level, which ensures 85-95%

dopant ionization, resulting in no significant effects on the channel

formation. This is further illustrated in Fig.2-4. We see the upper

graph is ,the energy diagram of a PMOS device at room temperature, and

the lower one the same diagram bdt at 77K. Notice the one at 77K that -elf

the channel region is still almost fully ionized, while the charges in

the bulk region are frozen out. This freeze-out of the bulk (or

substrate) benefits the device, since it reduces parasitic transistor

action in the substrate region which can cause a 'serious device

breakdown at room temperature when devices are driven at certain high

voltages. It is a serious reliability problem in small geometry MOS

designs. At low temperatures, however, because of the charge freeze-out

effect, the possibility of device breakdown is reduced. In addition, the

latchup problem is almost negligible at cryogenic temperatures [2-141. 4

The situation at the source and drain regTons at low temperature

1

is quite different from that at channel region. The source and drain are

usually made of highly-doped (degknerate) p or n-type material opposite

to the bulk material. The doping is so high in the source and drain i

region that the impurity ions are close each other, making the wave

functions being overlapped between the ionized and the neutralized

states [2-141, espe5ially at low temperatures. Thus at low temperatures,

DGO W i '

Fig.2-4 Energy diagram of a PMOS device at (a) T- 300K and (b) 77K.

Notice although at T- 77K, the charges in the substrste are frozen, the

charges i n p e channel are still nearly fully ionized, ensure the proper

operation of the devices at T- 77K.

the competition of freeze-out effect and wave function overlapping makes

the electric conductivity increase for highly doped region. The s

conductivity of sflicon varying as temperature depends upon the doping

concentration, for some not highly-doped sources and drains, the

conductivity may decrease with a decreasing temperature.

2.4.3 HOT CARRIER EFFECT LI

Hot-carrier-induced degradation characterized by the shifting of

threshold voltage, . changing of the subthreshol'd slope and

P transconductance, is considered as a major reliability problem when

operating MOS devices at low temperatures [2-7 to 2-36]. While it is

generally accepted that the degraaation is caused by hi&-energy-charge .%,%

carriers generated near the drain region, there are many different

physical mechanisms involved in the device degradation. Some researchers

attributed the change in device's characteristics ;.to, trapped negative

charge in the gate oxide near the drain [2-7,2-14,2-24, 2-25, 2-34], * some considered the degradation mechanism is the hot-carrier- induced

generation of interface states [Z-l9,2-2l,Z-28] , , or hot-carrier

injection [Z-18, 2-21, 2-23,' 2-2, 2-27, 2-35], and others s.uggested that

all mechanisms are involved [Z-26, 2-31]. A degraded device usually

shows a degraded mobility, transcondfictance, a shifted threshold

voltage, and a shorter life-length. Changes of these parameters can be

measured after DC stress test on the devices, and experimental results

will be presented in chapter 6.

2.5.1 INTRODUCTION

Since the beginning of the integrated circuits era, the minimum -

- device size has been reduced by two orders of magnitude [Z-111. As the

channel length is reduced, the device's characteristics depart &om that

of corresponding long channel devices. These departures, arise as a

result of two-dimensional high electri'c field) distribution in the

channel region and stronger drain induced barrier lowering (DIBL).

For a given channel-doping concentration, as the channel length is

reduced, the depletion- layer widths of the source and drain junctions

become comparable to the channel depth. One-dimensional theory is no

longer accurate to describe the devices hence two-dimensional and even

three-dimensional numerical analysis, such as with MINIMOS device

simulator, must be applied to get accurate results. However, this .

technique requires considerable amount of computer calculation time and

its physics is neither very obvious nor simple. For this reason, It is

necessary to develop simpler theorik, or physical models suitable' for

.both circuit simulation and further detailed theoretical study. A simple

approach is to adapt the long channel device and to modify it to account

for the short-channel or narrow-width effects. \

2.5.2 DEFINITION OF SHORT CHANNEL DEVICE

Sze [2-11] has defined a short channel device from two criteria: -- (1) For long channel devices, the subthreshold current I a 1/L; a DS

device - is short channel device when its I deviation from the 1/L DS

dependence by 10%; (2) For long channel devices, I is not a function DS /

3

of VDs (no DIBL) for VDS > 3kT/q; a device is short channel device when

(1 -I increases to 10%. DS , short DS, long)/'DS. long

2.5.3 V OF SHORT CHANNEL PMOS T

In section 2.2, we have derived V for long channel devices. In T

* this section, we will continue our discussion on short channel devices.

3 From the definition (1) of short channel devices above, the

departure from the 1/L is caused by the decrease of V as the channel is T -

made shorter. A few different models have been developed to explain this

short channel modulation of V [2-391. Yau [2-4C] first. proposed a very T -

simple model, termed charge sharing model.

The charge sharing model uses the charge neutrality concept.

Fig. 2 - 5 is used to describe the model. Fig. 2-5(a) shows that for long

channel devices, the impact of source and drain is small (being far away

from each other), and from charge neutrality almost all the charges in

the channel depletion region are balanced to the gate charge. However,

for short channel devices, the edge effect of the source and the drain. J

can not be neglected, referring Fig.2-5(b), since some of the charges in

the channel depletion region are balanced to the gate charges; others

d being so close to the drain and source, are balanced to ions ia the

-drain or source terminals. Assume that the amount of the gate charges '

are the same in case of Fig.2-5 (a) and (b), then the excess unbalanced

gate charge in Fig.2-5 (b) will balance the charges in inversion region,

making the inversion layer more inverted, in turn decreasing V and T

hence increasing I . DS

\ Jnversion layer

Fig.2-5 Channel diagram of (a) a long channel device and (b) a short

channel device. As we see in (b) that one dimensional model is

inadequate to describe the channel accurately because the channel depth

changes along the channel. (c) A much simplified diagram illustrate the

charge sharing model. (From reference [ Z - 3 9 3 ) !

-

The change in VT can be calculated

write the expression of V in a different T

of Eq. (2-24) is related to the depletion

Eq.(2-7) to Eq. ( 2 - 9 ) , VT now is

where

based on the model. First we

form. Note that the last term

region charge density Qg. ,From

A

The charge sharing model uses the effective depletion denbity QB

to replace Qg in V expression, thus the new V becomes T T

This equation is similar to Eq.(2-25), except the body effect A

Q,' . A

constant y is now changed to - 7 , Qg can be calculated as following. QB

For a short channel device, referring Fig.2-5 (c), the charge A .

density Q corresponding to the area of the trapezoid, and $ is that of B

the rectangular of L by 1 of lower figure of Fig.2-5(c). A simple

geometry derivation yields

where

and

In practice, a simpler form of Eq.(2-44) is used,

where a is an empirical fitting parameter. 1

Thus Eq.(2-43) becomes

Eq. (2-48) is for small V . For large V however, lD and is, the DS DS '

depletion length under the source and drain, are not equal, then

tr Eq.(2-47) must be replaced by

Using Eq.(2-45)' we have

Expanding the second term in the Eq. (2-50) around 4 and using a B '

Fitting parameter a' to replace the exact value 0.25 from the expansion,

The final expression V is T

(2 - 52)

where a is a new fitting parameter to account for drain bias effects. 2

2.5.4 CHANNEL LENGTH MODULATION

Channel reduction in short channel devices can cause the channel

conductance to change ,in the saturation region, that is, because of

saturation-channel-length modulation, Eq.(2-28) is no longer valid.

A much simplified model is used here to describe this short

channel effect [2-391. Fig.2-6(a) shows the channel diagram when channel

* is just at pinchoff, - i.e. V = V and the channel now is in weak

DS DS' *

inversion region at the drain end. If now V increases above V DS

the DS'

pinch-off point of the inversion layer will move to the left as shown in

-

' Fig.2-6(b), and the region between it and drain region is a depletion

region. Like in a bipolar pnp transistor, charges are swept to the drain

under the high field in this region. In Fig. 2 - 6 (b) , the channel - can ,not *

support a voltage larger than V since it becomes pinched-off when DS'

* * vDs' vDsy the excess voltage then (V - V ) appears across the region ,

DS DS

between pinch off point and the drain.

- * At VDs - VDs, the channel saturation current is

I - cons t D,sat L

where the proportionality constant (const) depends on V and V . GS BS

* Considering the case where V > VDs, and let the corresponding

DS *

saturation current be I . From Eq.(2-52), we have, from Eq.(2-52) D , sat

and Fig.2-6,

I* 1 -- (const) L - A L D , sat L.

where AL is the displacement from the drain to the pinchoff point, and

is dependent on the drain voltage. Using Eq . (2 - 53) and (2 - 54) , the

* saturation current of short channel devices I is related to long

D , sat

channel saturation current I D,sat by

I* = L

D , sat 'D,rar L - AL

* Thus I is also dependent on the drain voltage for short

D, sat

channel devices, in other word, there is no 'real' saturation current

* for short channel devices because I depends on V . D S DS

F i g . 2 - 6 Channel diagram of ( a ) a t p inchof f p o i n t and (b) above p inchof f

p o i n t (From r e f e r e n c e [2-111)

2.5.5 VELOCITY SATURATION

Another short channel effect is the velocity saturation of the

channel carriers. The average velocity of ch'arge carriers in the channel

v is related to the channel mobility p by d

where E is the horizontal electric field. X

Fig.2-7 is shown the typical carrier velocity in the channel v vs d

horizontal field E . Referring to this figure and Eq.(2-56), we see that X

as E << E , we have v a E , indicating the mobility is a constant. For x c d x

E r E , v is approximately a constant, and equal to v x c d

. This d , max

phenomenon is called velocity saturation. For short channel devices,

velocity saturation is very significant due to the high E , causing a X

decrease in the transconductance and channel mobility.

, A brief derivation below gives the relation of E on the X

mobility.

An empirical

E is given [ Z - 4 2 1 X

/'

relation of channel velocity v (E ) as a function of d x

as

In general, E and E , can be expressed as fi

X C

1

From the linear characteristics, I can be obtained as follows: DS

where Q is the inversion surface charge density. I

Combining Eq.(2-57), (2-58), (2-62), we have

Integrating above equation, we have

Assume the mobility p is uniform along the channel, we have

The form of IDS in equation (2-66) is the same as Eq. (2 -17 ) ,

except p in Eq. (2-17) is replaced by p . The effective mobility p ef f eff '

is given by (see Eq.(5.3) later)

Normally, a fitting parameter q is inserted in the denominator of

Eq.(2-67). With this change, the total channel mobility becomes

where 0 = 8 + ,6-R 0 P

2.5.6 SUBTHRESHOLD SLOPE (S) OF SHORT CHANNEL PMOS

The short channel effect also affects the subthreshold s\lppe. By

using charge sharing model, we can derive some expressions that describe \

this short channel 'vdulation on S .

For a uniform-doped channel and assuming Eq.(2-30) still valid for

short channel devices, the depletion capacitance C decreases due to the D

charge sharing, and can be calculated as follows.

From the definition of CD

and the fact that Q ;. % in the weak irbersion, we have

C - aQB

all, D ( 2 - 7 0 )

A

For short channel devices, Qg is replaced by Q . According to B

A

charge sharing approximation, C 'will r-eplace C defined as D D '

which is less than CD. E ~ . (2- 30) now becomes '

This equation implies that S is better for shorter channel.devices

of uniformly-doped, than for the long channel devices.

2.6 NARROW CHANNEL WIDTH EFFECTS

L. 6.1 INTRODUCTION

Narrow channel effect is relatively less studied than short

channe& effect. However, narrow channel effect is equally important

since it will decrease the junction capacitance and increase the circuit

density, although it can not increase the transconductance through

shrinking the width of the devices. Due to complex 3-D field

distribution in the channel, seeking simple models for dealing with both

short channel and narrow width devices is very difficult. For this

reason, we shall examine only narrow "width devices, while keep the

channel length long.

For narrow channel width and long channel devices, the high field

effect is small, so the high-field related degradations of the devices

are also small. Because the effective depletion charge distribution" in

the channel is different for narrow width and wide channel devices, V_

and S

1

will not be the same, either.

THRESHOLD VOLTAGE

The charge sharing model is again used to derive an expression for

V because the model provides a simple ,approximation with good physical T '

meaning.

Because the channel is narrow, the effective channel width will

not only be the the drawn gate width, but=also includes the fringe part

of the channel which is ignored for wide channel devices, shown in

Fig.2-8.

Using a simple geometry derivation [Z-111, the effective depletion .

charge density is

where Qi is the depletion charge density of narrow width channel

devices.

Using Eq.(2-43)., and with the help of Eq.(2-74), we have

where a is a narrow-channel width fitting parameter. This equation 3

describes the variation of V with W, and states that as W decreases, V T T

will increase, opposite to that for short channel devices.

This suggests that if the devices are both small in length and

width, the values of W and. L can be chosen to result in no change or a

minimal change in V . This can also be regarded as an optimization T 9

design role for decreasing small geometry devices.

2.6.3 SUBTHRESHOLD SLOPE

Using the same procedure described in last section, we can develop -

the expression of S for narrow channel devices. Without repeating the

same procedure as section 2.5.6, we just present the result as shown in

the following expression:

POLYSILICON GATE Si02

S i

I I ! !

F i g . 2 - 8 Narrow channel e f f e c t due t o l a t e r a l d i f f u s i o n

where

These equations mean that when the channel width is narrower, S is

larger, or worse; opposite to the result for short channel length

devices (see section 2 . 5 . 6 ) .

CHAPTER 3 DEVICES UNDER TEST

3.1 INTRODUCTION

From the analysis in chapter 1 and 2, we considered that only

enhancement mode devices work well at low temperature. In chapter 2, it -

was explained that a device with both narrow and short channel is

difficult to study, because of the complexity of 3-D field distribution

in the channel. Although a few papers have been published on the devices . - with both'short and narrow channel, in which the device is modeled by

combining both short channel and narrow channel models [Z-391, in

reality, the physical description of the device is not so simple.

Because of this fact, the present research concentrated on studying

short channel devices and narrDw channel devices separately. From this,

a good understanding of the behavior of short and narrow channel devices "

can be obtained. This is a sound approach to-_ the •’zture small devices

(devices of both short channel length and narrow channel width).

3.2 TEST DEVICES

To avoid freeze-out effects discussed in chapter 2, all PMOS

devices used in this study were enhancement mode. With standard CMOS

technology, these PMOS devices were fabricated adj acent to , each other,

and were in an n-well in the p-type substrate, with a well doping

16 - 3 + approximately 2x10 cm and n polysilicon was used as gate material.

The gate oxide thickness was 250A, and the source and 'drain junction

depth were -0.2 pm. A thin p- type layer of boron was implanted in the

channel. This doping centered about 0.09gm deep in the channel, with

16 - 2 doping of -3x10 cm .

The 3-D doping profile of the PMOS device is plotted in Fig.3-1.

The doping profile of the device was calculated with Supreme I1 and

MINIMOS I1 simulation programs from the processing parameters provided.

From this figure, we see clearly that the boron implant is peeked at

about 0.09pm deep in the device, and the magnitude of the implant is

about 3~10'~crn-~. The corresponding potential plot is shorn in Fig. 3 - 2. $

This plot shows the device is. not conductive because of the boron

implant is, in the depletion region although the barrier is lowered in

the substrate. The purpose of the boron layer dwping is two fold, first

for V adjustment and secondly for suppressing the punchthrough effect. T

-These small geometry transistor structures are composed of six

short channel devices and eight narrow channel width devices. The six

- short channel devices have drawn gate lengths of 1.2, 1.5, 1.8, 2.1, 8

2.4, 3.O,um, respectively, and a channel width of 24 p n . The varying

width group have drawn gate widths of 0.6, 0.9, 1.2, 1.5, 1.8, 2.1, 2.4,

3.0pm, respectively, and a gate length of 12 pm. Both group of ldevices

have a common gate, source and substrate terminal, but different drains

for individual transistors. The chip layout is drawn 'in Fig. 3-3. It

s:tould be pointed out that -there was no input or output protection

circuits, as shown in the figure.

3.3 PACKAGING OF DEVICES

The varying length and varying width group devices were fabricated

adjacent to each other, and they were wire-bound in a 24 pin ceramic

package. After wire-bonding, the chip was sealed with a metal cap to

avoid light and electromagnetic field influences.

F i g . 3 - 1 A 3-D p l o t of the doping p r o f i l e o f a PMOS device w i t h G0.9pm

and W-24pm, measured from the cen te r of t h e channel. This p l o t and

Fig . 3-2 are generated with the process program SUPREME I1 and 2-D MOS

device s imulator MINIMOS 11, with the processing parameters provided. - r

Fig.3-2 A 3-D plot of the electric potential of the same device in

Fig. 3-1. As shown the boron layer does not form a buried channel, l

because the thickness of the layer is very small.

Fig. 3-3 Chip layout. (a) Array of short channel devices; (b) Array of

narrow width devices. The devices shared a common gate, source and

substrate, but different drains, as indicated by the symbols, the two

shortest devices were not operational due to device punchthrough.

CHAPTER 4 I

EXPERIMENTAL DETAILS

In this chapter, the system with which all the experiments were

performed is described. It has been proven experimentally that the

system is reliable and is easy to use. In the following sections, the

system for room temperature and low temperature measurements will be

presented.

The schematic diagram of the system is shown in Fig.4-1. We see in

the figure that this system is composed of an HP 4145A semicohductor

parameter analyzer, an IBM AT computer, a high precision DC power

supply, two ~ e i k h l e ~ 195A multimeters, and a Keithley 950 CV meter.

SEMICONDUCTOR KEITHLEY 195A MULTIMETERS

KEITHLEY 950 CV METER /

KEITHLEY 614 ELECTROMETER

Fig.4-1 Block diagram of the experimental setup

-.

The semiconductor parameter analyzer is a piece of high precision

(with 2 0.lpA) 'programmable current and voltage measuring equipment with .

four independent channels of multimeters and power supplies. All the

experiments were performed with this analyzer. The IBM AT personal < I

computer controlled the semiconductor analyzer for 'different kinds of

experiments. The computer is also used for acquiring data from the

semiconductor analyzer, data analysis and parameter-extraction from the

acquired data with certain developed software. The interface between 'the

computer and the semiconductor analyzer is through an updated IoTech

IEEE 488 bus interface board.

At room temperature, the test package was mounted in an HP '

16058-6003 personality fixture, to screen off electromagnetic noises.

The fixture was connected to the semiconductor analyzer through

impedance matched coaxial cables. To switch from one transistor to

another, small jump-wires are used inside the fixture. With long

.s

integratdon time in an experiment, the noise current of the system is

less than + 200%~. The procedure to perform an experiment is as follows:

1. Make a configuration file, in which the operator specifies what

type of experiment is to be done by the semiconductor analyzer.

2. Put the paykaged chip into the fixture.

3. Run the control program, called SPA.EXE. This program controls

the semiconductor analyzer; sends the configuration to the

analyzer and downloads the data back to the computer in a data

file with the name specified by the user.

4. Run the program FET to extract all the important parameters,

then analyze the results obtained.

4.2 LOW TEMPERATURE SYSTEM

Because the HP fixture was nQt designed for ' low temperature

measurements, a low temperature fixture - cryo-probe was designed. It

Gas found that low temperature experiment usually generates more noise

than the room temperature one does because at low temper$ture the device

was inserted into the metal dewar through a long cable.

This probe is composed of a shielded multi-wire cable and a

shielded and grounded cryo-probe, in which the test package was mounted.

A silicon diode temperature sensor is attached to the package. The probe -

then is connected to the personality box of the HP semiconductor

P analyzer. The rest of the system for low temperature is the same as that

for room temperature. Fig.4-2 shows the schematic drawing of of the

4.3 SYSTEM CALIBRATION AND ACCURACY

For obtaining reliable results, it is necessary to calibrate the

system and estimate its accuracy. The most important equipment, the HP

semiconcFuctor analyzer, is always set in the self-calibration mode, thus

calibration procedure is saved. The noise, especially at low

temperature, coupled through the probe and the cable can sometimes *

overwhelm the signal in measurements of subthreshold region if the system

is not shielded properly. Table 4-1 shows the noise current in the

measurements for different test fixtures and integration time (I. T. ) 1 In

the table, the noise current for using the HP fixture is 80pA, IpA, and

200fA for short, medium and long integration time in the measurement,

respectively. This shows that medi-m time is sufficient for the HP

fixture. For cryo-probe, however, the noise is lOpA even for long

Cu tube

Ceble

Circuit Boord

7

Fig.4-2 Schematic diagram of the cyro-probe used in the experiments

integr>tion time with nonefficient grounding; with good grounding, this -

noise current is approximately IpA. Thus, for low temperature

measurements, long integration time is necessary. However, considering

the stressing effect of prolonged measuring time, medium integration

time was finally chosen for the experiments at all temperatures.

Temperature was measured through the diode biased at 100pA, then

the voltage reading across the diode was transferred to T by checking

the pre-calibriated data table. The temperature gradient (AT) between

the die and the substrate can be estimated from the following

calculation:

As an estimate, take the size (A) of the die be 0.5cm x 0:5cm, and

the thickness (t) be O.lcm, and maximum testing power (P) 150mW, from

the expression below,

we have, AT = 3K at T=300K and 0.01K at T=77K, so AT across the device

- can be ignored, especially at low temperatures. Note that k was obtained

from Fig.1-2.

Table 4-1 Noise current of the system

(with proper shielding and grounding)

Long

200fA

IPA

Medium

IPA

lOpA

Fixture\I.T.

HP Fixture

L.T. Probe

Short

8 0pA

' 1nA

CHAPTER 5 + SOFTWARE .

&> In this chapter, two major program packages, the parameter

extraction program (FET) and the visual editor (VEP), will be presented.

Because they play such an important role in data extraction from the

experiments, it is worth while to describe them in some detail.

5.1 VISUAL EDITOR PROGRAM (VEP)

The visual editor program - VEP was developed to fill the need for

flexible data manipulation. In data processing, very often we need to

inspect the data visually. For example, when looking for the maximum

value of the derivative of ,a. curve, very small noise in the data can

cause its derivative to become the maximum of the curve, which is not

the value we expected, so we need to ionitof the data in many

calculations to ensure the results are valid, but few commercial

programs are available that can handle the data efficiently. Examples of

available programs are Lotus 1-2-3 or Slidewrite, but they both have

deficiencies. For example, Lotus 1-2-3 can only plot up to 6 curves at a

time and it is also very lengthy and can not 'perform some of the

calculations. Slidewrite can plot up to eight curves with curve fitting,

but it lacks flexibility to perform other mathematical operations such

- - as diffel'entiation and integration, and it is rather slow in handling

data. VEP was developed to solve these deficiencies and to do more. This

program not ,only includes a lot of useful mathematical routines, but it

is also user friendly. It ,does not need a mouse, and also accepts

different kinds of monitors (e.g. CGA, Hercules, EGA), making it usable ' '

/

on virtually any PC, XT or AT computers. VEP is very fast, simple and

easy to use. It was written in Turbo PASCAL (version 4) and it used most

of the advanced Turbo graphics routines.

5.1.1 FUNCTIONALITY OF VEP

The functions'of VEP are the following:

Plots the curves in either linear or semi-log scale.

Manipulates data of up to 5,000 points - (of any size of 'matrix).

Calculates the slope of the curve at desired point(s) using

least square fitting technique.

Zooms in or out function that allows detailed studies of a

particular region of curve. -

Smooths data with three different schemes.

Does curve fitting that includes:

1) Spline fit;

2) Polynomial fit of up to 18th power;

3) Power fitting;

4) Exponential fitting;

5 ) Logarithmic fitting;

Does differentiation - and integration routines.

Calculates the reciprocal of the curves.

Does data interpolation.

Has seven user def iii'sble routines (e. g. square root of data) .

Plots the curves displayed on screen directly to a printer or a

plotter.

Displays curves in either line or dot form.

Has batch mode to allow for dealing with many data files.

I n t h i s s e c t i o n , a b r i e f ' desc r ip t ion of the usage of VEP i s given.

The program is s e l f explanatory, s o t h a t it does no t r equ i re a --

a d d i t i o n a l he lp manual.

To use i t , simply type , under the DOS prompt >,

VEP f i l e name v

where f i l e name i s the input f i l e name. The f i l e ha's t o be a da ta

matr ix . Switches can be added on t o use some s p e c i a l func t ions ; f o r

s

example, use " - " a f t e r f i l e name w i l l p l o t the d a t a wi th negat ive x and

y - a x i s , and i f switch "@" is used it w i l l a c t i v a t e t h e ba tch mode which ,

allow VEP t o dea l with many da ta f i l e s .

I n the program, p res s ing [Esc] key w i l l move the cursor t o the

menu a t t he bottom. Choose the des i r ed funct ion(s ) using [ R i g h t ] , [ L e f t ]

key o r [Space] key, when you decided, h i t [Enter ] key t o execute the *

L - f u n c t i o n ( s ) . There a r e th ree l aye r s of manual, wi th the t h i r d l aye r

being the user def inable func t ions . To e x i t from t h e program wi tho i t

saving the ' ,data, simply p res s [ C t r l - C ] . [Grey+] o r [Grey-] is used t o

increase o r decrease the the s t e p .of c u r s o r ' s movement o n . t h e curve.

To use batch f i l e mode, you have - t o ' t e a c h ' ' the- program once.

F i r s t you process a da ta f i l e ( f i r s t d a t a f i l e ) without us ing switch

" @ " . After e x i t i n g the program, a l l the key s t rokes used i n the program

a r e s t o r e d i n a f i l e . Then suppose you have many f i l e s t h a t you want t o

pro'cess them the same way a s you d i d f o r the f i r s t one, a l l you have t o

do is type VEP f i l e name @, the program w i l l r epea t same procedure

j u s t l i k e doing the f i r s t one, O r you can make a ba tch f i l e t o process

many f i l e s a t once. Any parameter shown on sc,reen such a s t h e s lope and

the c o e f f i c i e n t s f o r curve f i t t i n g were s to red i n a f i l e VEP.DAT.

At the tipe the thesis was written, 1.found it was possible to put ,

spreadsheet into the program VEP, to make it even better, because you

can edit the data in either visual mode or in usua-1 edit mode,_ and this L -

provides more flexibility.

Another improvement is the change of the computer language.

Because VEP is written in Turbo PASCAL, there are some intrinsic

shortcomings, such as 'data, I/0 and screen handling, which make further

improvement increasingly difficult. A better computer language for

improving VEP is the C languagk. 4

35.2 PARAMETER EXTRACTION PROGRAM (FET)

The program FET has been developed for extracting transistor

parameters from the raw data obtained by the Semiconductor Parameter

Analyzer. It then checks those parameters by comparing the calculated

curve with experimental data and at la& gives the results in a report k.

file. Section 5.2.1 introduces the physical and mathematics models used

in the program; sub-section 5.2.2 shows how to use 'the software; and

section 5.2.3 describes the structure of the program.

The feature of the mods1 is that parameters are extracted one by d

one and the main mathematical tool is the linear least square fixting.

The advantage of the method is that it is easy to understand the

physical meaning of each parameter and the accuracy of the extraction is

excellent.

In this section we use model for short channel length MOS device

as an example; the model for narrow channel width MOS is similar will be

given in section 5.3.

5 . 1 1 THE MAIN MODEL

The- physical model used for the drain current of short channel -

device is a modified from Eq. (2-23). In this model, the effect of the

parasitic resistance R is included, and gives P

This equation is valid only in strong inversion and for very small'

vDs (vDs. - 5OmV) . For moderate V a second term in Eq. (2-20) is needed

DS

and this is also included in the program. The program requires the IDS

vs. V data from experiments. Some device processing parameters and GS

measuring conditions are also needed; for example, C oxr VDS

, W and LM (L e = L - AL). FET extracts six principal parameters: V ,AL , Rp , 00, pO M T

and. q .

In the following sections, parameters were extracted from

different blocks for convenience, each of the block extracts only some of

the parameters.

5.2.1.2 EXTRACTING v AND G (BLOCK VTGM) T m dV

GS From the I vs. V curves, we get the derivative G = and

DS GS m dlDS

determine the maximum G , G . From the point m m, max (' I -,mar

. , a straight line with the slope G I l ~ , m a r m, max is drawn. The

X-axis's intercept is V . The physical meaning of the procedure will be T

given in chapter 6.

5.2.1.3 EXTRACTING AL AND R (BLOCK L) P

In general, q in Eq. (5- 1) is small enough to be neglected in the I

first order approximation at small drain bias. Dividing both sides of

Eq. (5-1) by Ills, we have

v D S where R = - \ I

; L is the drawn channel length; AL is the difference M

DS

between L and L. If-we plot R against L with different (V -V,) , from M M ' GS

Eq.(5-2), we will get a series of straight lines crossing the point

( A L , R ) , as illustrated'in Fig.5-1. P

5.2.1.4 EXTRACTING 8, p AND q (BLOCK Mu)

From Eq. (5-1) the following equations can be derived:

where

L, (micron)

L, (micron)

Fig.5-1 Diagram to illustrate the procedure of extracting the channel

length deduction AL and the parasitic resistance R . (a) A full scale P

plot of channel resistance R vs. channel length L; (b) Magnified plot of

(a ) to show the detailed results.

? ', With the help of Eq.(5-3), we have

where

'L From the plot of - v s . (VGs- VT), we will get ,9' and go . Then

d T rn

rewriting Eq.(5-4), we have

1 from the plot of -

B vs. L, p and '7 can be extracted.

0

5.2.1.5 EXTRACTING ND, a AND Vm (BLOCK N ) D

From Eq,. (2-48),

where

where n is the intrinsic concentration of carriers and i

Because both 7 and $B depend on ND, we can use the self-consistent

method to find N and a as follows: D 1

a) From the plot of V vs. 1/L, assume a initial N value, (e .g. T D

2 ~ 1 0 ~ ~ c m - ~ ) , we have 9

slope - -j.c.al.( -2$B+ VBS)

intercept - V + $B+ 74- fb (5 - 12)

b) From Eq. (5-11) we can get a for each V . According to 1 BS

Eq.(5-12), from the plot of intercept vs. , we will get V fb , 4

and 7 by using the linear least square fitting again.

c ) Using Eq.(5-10) we can get N from 7. Then use the new N to D D

replace the old one and repeat the above steps. From Eq. (5-8) we know

that I,$ is not sensitive to N (e. g. when N changes 40% the gB varies B D D

less then 3 % ) , so the convergence of the method is very good.

This block is to get the sub-threshold slope by seeking for the

maximum dVGs/dLog(IDS), K . From the experimental curve of IDS VS. max

V we calculated 1/K , the subthreshold slope S, in mV/decade. GS ' max

This program is also written in TURBO PASCAL (version 4 . 0 ) . You * .

can enter the program by type

Then there will be a menu appears on the screen as below:

Setup VtGm Lef f Mu Result Report Nsub Slope Digitalcheck Graphiccheck

This is an interactive software package. Different routines are

se-lected by moving the cursor around the menu screen, then hit [Return]

key to execute the operation of the routine.

5.2.2.1 THE MAIN MENU LINE

The first line in the menu is referred as the main menu line

Going along the line and select routines sequentially you will extract <

all six principal parameters in Eq. (5-I), using the model described in

the last section. The function of each routine are the following:

a) Setup: Generates the information to be used by other routines.

b) VtGm: ~xtracts V and Grn T

c) Leff: Extracts AL and L.

d) Mu: Extracts p and q .

e) Resu1t:Displays on the screen the experimental and calculated curves

to show the fitting accuracy

f) Report:Generates a report file on the disk which includes

* the information input by the user in routine Setup;

* the parameters extracted; * the fltting error.

5.2.2.2 THE SECOND MENU LINE

The second menu line consists of some useful routines. The models

of these routines are independend of the main model, Eq. (5-1) . If the

user has a new model for extracting some of the parameters, it can be

inserted the in-port in this line.

The functions of each routine are the following:

a) Nsub: extracts *D' Q1

and V Its model is described. in fb'

section 5.2.1.

b)Slope: extracts the sub-threshold slope S. See section 5.2.1.5

for detail.

5.2.2.3 THE CHECK LINE

The routines in the third menu line are used as checking tools, in

which the program L.EXE is used for data checking and the PLOT.EXE for

plotting the data.

5.2.3 THE STRUCTURE OF THE PACKAGE

The structure of the package is illustrated in the Fig.5-2, and it

is fairly straight foryard. -First the user gives information through

Setup procedure, then the program generates some data sent to the

config.dat file. Then the program runs using these data until it is

1) finished. The final results are recorded in a report file.

5.2.4 LATER IMPROVEMENT

Later improvements have been c a r r i e d o u t . The major changes

include command l i n e opera t ion mode and g lobal parameter adjustment.

Some of the important changes a r e described i n the following sec t ions .

. 5.2.4.1 GLOBAL OPTIMIZATION

We use parameters' ex t r ac ted from FET a s i n i t i a l va lues , then

a d j u s t each of these param.eters t o make following e r r o r funct ion become

minimum.

where

- fM

1' i s the I ca lcu la t ed from the E q . ( 5 - 1 ) . j DS

i s the IDS measured i n the experiment. , j

ERR = 1 j

j j

j

e F o n f i g . d a t INFORMATION ..-u-..u-...-u............... -"

,+ p * q . y L v t ? . - dat - i

11 source data 11 1 ' f i l e s I( ... .- . ....... .- ..... -. .... .....-... ... .-

l e f f . dat .- - . -, ............ -. .. ? . - -, .. - ........ - ... - .. - . 1- ............... ......................

Mu. da t ........... "- .... 1-

Y

..... .- ...... .- .. .- -. .

Nsub . dat -. - - - - - -. ....... - - -. ....... - .... l-

.......... -. ............ ...... .- ....................

slope. dat -+ . - .... - . - ........ -. ... - ..... .- .... - - .. -. .. - - - -. . I

Fig.5-2 Block diagram of FET

This g lobal adjustment rou t ine v a r i e s each of the parameter by a

small f i x e d amount. Then it c a l c u l a t e s ERR; i f ERR is sma l l e r , i t v a r i e s

t h e parameter i n the same d i r e c t i o n again, and i f ERR is g r e a t e r , i t -

v a r i e s the parameter i n the opposi te d i r e c t i o n . I t r epea t s the process

u n t i l ERR is minimum upon any f u r t h e r change f o r every parameter. I n

t h i s way, we can g e t a s e t of optimized parameters which f i t the

experimental curves b e s t .

The advantages of t h i s method a r e a s fol lowing.

a ) I t avoids the divergence problem, which i s a t times very complex

b) I t does not allow the parameters change beyond a spec i f i ed

. region.

This quest ion a r i s e because it may happen t h a t although ERR is

very sma l l , some of .the parameters become e i t h e r , t o o l a r g e o r too small ,

with no d e f i n i t e phys ica l meaning'.

Another important parameter i s the s u b s t r a t e b i a s modulation of

mob i l i ty , denoted a s OB'

was implemented i n l a t e r ve r s ions of the

C

program FET. The rev ised vers ion b a s i c a l l y - is the same 'as the o r i g i n a l

except add one more rou t ine of e x t r a c t i n g 6 . B

5.3 THE PROGRAM FETW

I n previous sec t ions I descr ibed the program FET which is used t o

e x t r a c t i n g parameters f o r varying length devices . I n the following

s e c t i o n , I w i l l in t roduce a s i m i l a r program FEW, used f o r ek t r ac t ing

parameter from varying channel width devices . Being s o much i n common

with program FET, I w i l l only expla in the d i f f e rence between FET and

FETW .

The model used in FETW is

where W -. W - AW, W is the drawn channel width, and AW is the channel M M

width reduction. Re-writing Eq.(5-14), we have

where

Having known C , L, VGs, IDS and WM, we can calculate V OX 9 P o d o '

AW and R . P

5.3.1 EXTRACTING P , g o , aw, R IN FETW P

Those four parameters from the R matrix were extracted again uslng

the linear least square fitting method. I

Using Eq.(5-15) and use the data with V = 0, we get the R matrix BS

where

From Eq.(5-18) we see that R is a function of W and X. From R vs. M

(l/X), we get the slope's and the intercept I as 0 0

1 S =Slope = .--- = 1

o Ka IJ KW - KAW M

0 IO - Intercept - Rp + - K W ( 5 -23 )

- iL-,

Then applying linear least square fitting again, we have

a) From (l/So) vs. WM, .

S = Slope = K 1

I I = Intercept - - K-AW 1

1 get AW - - -

S

b) From I vs. (l/W) 0

i !.

S = Slope = 0 get B = S 2 0 0 . 2

In this way we obtain all six parameters.

In the next chapter, the results obtained using these programs

will be presented, showing the success of them in extracting device

parameters.

RESULTS AND DISCUSSIONS

This chapter will describe detailed experimental results using the - programs developed i chapter 5.. It also presents the relev6nt

discussions based on the 'theories presented earlier if chapter * - Because of the length of the chapter, the results and discussions will

be divided into three major sections : those describing the linear, the

saturation, and the stress characteristics, respectively.

In this section, the lineal characteristics that were studied, ,

such as V G , p, ' S, and their dependence on device geometry, biasing T' m

. conditions and temperature are described.

Case A: In ohmic region of operation.for small V . DS

In this sub-section, the results o'f V along with its modulation T' ,

parameters, a a. and parasitic resistance R will be presented. 1' 3 P

The definition of V was previously given in chapter 5, but the T

physics' of it was not clearly described, thus an explanation for the I

extraction of V i~ needed. For very small VDs, Eq. (2-18) becomes T

Eq. ( 2 - 2 3 ) , an equation of straight line about V . Now the problem is GS

how to find the straight line experimentally, because the IDS -V - GS

curves for small geometry devices are not likar. At,present there (

exists no theoretical meth'od to find this line from the experiment

. I

[ 6 - 1 1 , and hence is difficult to determine V . By inspecting the T

- experimental curve- in Fig.6-1, we found that the curve changes from

concave region a to convex region c , and between them is a relativa -5

straight line segment (region b), we will see that V can bk extracted P

from this region. Since region a of the curve is from subthreshold a

&= -"v '

, region to the beginning of the strong inversion region, and region c has*

a strong vertical field modulation on p measured with 0 Eq. (2-23) is 0 '

tlien not a valid approximation in either region. In region b, however,

the vertical field modulation is minimal, and region b is aiso in strong -7 F

inversion region, , thus Eq. (2-23) is a good approximation. To check if;

the inflection point, in section .b of the I -V curve, is at where DS GS

e0*(VGs-VT)<<l, we use G curve. From Eq.(2-38), we know that if rn

* (V -V )SO = 0,'G has maximum, corresponding to the inflection point.

GS T o rn i

Then we look for a straight line represented by Eq. (2-23), and .extract 1

V from the X-axis' intercept. The sequence extracting V is illustrated T T

in Fig.6-1. Fig.6-l(a) is a experimental I -V curve and Fig.6-l(b) DS GS

shows the derivative of curve in which we find G , and the +I

m . max

corresponding inflection point. Then a straight line was drawn-using

least square fitting through the inflection point and a few points at

each side of the inflection point on the curve. This method of

extracting V not only preserve the physical meaning of V but also T

L- T '

proved itself an easy and effective way of finding V in string T

inversion region. All linear measurements are with V - 50mV. DS

( a ) Experimental I -V curve f o r a device with k.2.4pm and DS GS

Fig. 6-1

W-24pm, a t T-300K. The whole region w a s divided i n t o t h r e e s e c t i o n s ,

region b is used t o ex t rqc ted V . (b) The d e r i v a t i v e of t h e .curve i n T

F i g . 6 - l ( c ) P l o t t o show V ex t r ac ted from the i n t e r c e p t of the s t r a i g h t T

l i n e determined i n reg ion ( b ) .

Figs. 6-2 to 6-5 give the measured and calculated results of V of T

short channel and narrow width devices at 77K and 300K, respectively. As 4

shown in Fig. 6-2, when the channel length decreases to about 1.2pm, V T

decreases significantly for all substrate biases (O-4V),,indicating that - .

the short channel modulation is very important if the device channel

length is less than 1.2pm. For narrow channel devices, the narrow width

modulation began when W < 1.5pm, a l t h o d i t was not as strong as in the '

case of short channel devices, referring Fig.6-3. The shape of the

curves in these two figures is almost independent of the temperature

(compare Fig.6-2 with Fig.6-4 and Fig.6-3 with Fig.6-5), implying that

short channel or narrow width effect does not depend on the temperature

significantly, and hence short channel or narrow width devices can be

defined at any temperature. Uqing rq.'(2-52) to . fit the V results of T

these devices, we get channel length and width modulation constant a's,

and substrate doping N . Fig..6-6 gives the results of a and a at 300K. D 1 . 3

It sbqws that the short channel and narrow channel modulation is less at

higher substrate biases. phys tcally this is correct, because at higher

substrate biases, the channel depletion width' is shallower (forward A

biasing the channel p-n junction more), then OJQ, is smaller, and this

leads to a smaller channel length or channel width modulation. . - I

Now let's look how temperature affect V . As we've seen in Fig.6-4 T I D I

and 6-5, V at 77K was higher than at 300K. To further illustrate how V T *x -

'vary with temperature, Fig. 6-7 to 6-10 were drawn to show the variation

, - in V with T at varying VBs? L or W. In Fig. 6-7 and 6-8 are shown tQat

T

Cr V changes with temperature for varying .channel length devices. As T

\

shown, V increases almost lineaYly with decreasing temperature, with a T

slope of 1.8mV/K. This change in V with temperature is mainly caused by , - T 3

Length (micron)

Fig .6-2 P l o t of VT v s channel length a t T-300K, with V -0,1,2,3,4V. The BS

symbols a r e the experimental r e s u l t s and the l i n e s were the ca lcula ted

r e s u l t s from the model and the parameter ex t rac ted .

Width (micron)

Fig.6-3 Plot of VT vs channel width at T-300K, with VBs-0,1,2,3,4~: The

symbols are the experimental results and the lines were the calculated

results from the model and the parameter extracted.

Length (micron)

Fig.6-4 Plot of V vs channel length at T==77K, with V -0,1,2,3,bV. T h e T BS

symbols are the experimental results and the lines were the calculated

results from the model and the parameter extracted.

3

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 *

Width (micron)

F i g . 6 - 5 P lo t of V vs channel width a t T=77K, w i t h VBs=0,1,2,3,4V. The T

symbols a re the experimental r e s u l t s and the l i n e s were the ca lcula ted

r e s u l t s from the model and the parameter ex t rac ted .

the change of Fermi potential. We also notice, in Fig.6-7 and 6-8, that

V is very dependent on channel length, and this will be further T

discussed in terms of a later. The body effect constant y is used to 1

monitor the channel freeze - out. Our experimental results agree with

earlier analysis that freeze-out effect is not significant due to the

energy band bending. In the experiments, N was -1.9~10~~/cm~ at all D

temperatures. Results for. narrow width devices were also obtained and

are shown in Figs.6-9 and 6-10. Fig.6-12 and 6-13 are the plots of a 4 1

and a respectively, as a function of substrate biases and temperature. 3

. .

As expected, the a and a are smaller at 77K than at room temperature, - 1 3

because of the decreased depletion widths around the source and drain at

lower temperatures (See Appendix D) . Fig.6-6 and 6-11 are the plots of

a and a at 3 0 0 K and 7 7 K , respectively. These graphs show the 1 3

dependence of a and a on V at 7 7 K was not as strong as at 300K, and 1 3 BS

this is because the carrier freeze-out in the substrate causes the

effective bias on the back of the channel to be less. This, together

with smaller value of a and a makes V less sensitive to V at low 1 3 T BS

temperature, a very important result for CMOS circuit designs. -

A well known square root dependence of VT on V is observed at BS

all temperatures, particularly the results of room temperature and

liquid nitrogen temperature data are illustrated in Figs.6-2 to 6-5. The

lines in these figures were calculated using Eq.(2-52) and the other

parameters extracted.

F i g . 6 - 6 Results of V modulation fac tor fo r shor t channel e f f e c t a and T 1

narrow width e f f ec t a vs. V a t T-300K 3 BS

50 100 150 200 250 300 350

Temperature (K)

Temperature (K)

Fig.6-8 Plot of VT vs. temperature for varying channel length devices at

v - 4v. as

Temperature '(Co

Fig . 6 - 9 P l o t o f * VT vs. temperature f o r varying channel widch

v - ov. BS

dkvices a t ,

. I

I.

Fig . 6 - 1 0 P l o t of VT vs . temperatdre f o r varying channel wSiETi3iZrices a t

V =4v. BS

Fig.6-11 Results of V modulation factor fo r short channel e f f ec t a and T 1

narrow width effect a? vs. V at T-77K. BS . . .

Temperature (K)

Fig.6?12 a, vs. T ac d i f f e r e n t V 9s

Temperature (I.0

F13.6-13 a= vs. T at d i f f e r e n t V - BS

Case B: or larger V in non-saturation region DS

The above results wexe t.aken for the very small V (5OmV) to DS

avoid high field effects, but it is very important to know the V at T

different VDs; for example, in analog circuit designs, we need to know

how V changes wi<h V in order to obtain accurate simulation results. T DS

At larger V Eq. (2-18') can not be $implified - to Eq. (2-23) any more, DS '

- -

instead, a different approach must be applied. Fortunately, if we \

inspect Eq.(2-18) carefully, with some reasonable assumptions, we can

still use the linear extrapolation method to get VT, in the ohmic *

region. 4

Eq.(2-18), rewritten below,

if we use 1

linear extrapolation method, we will get V - -* (1+6)VDs - 4,

T 2

rather than V . T

-?,-

1 Then a':sirnple subtraction of -* 2

(l+6)VDs will yield the 'tr

correct V where 6 could be calculated using Eq.(2-19). This method has T'

been previously used with excellent V results at larger V biases T DS

11-21. The Notation V and V are interchangeable in the thesis, they SB BS

can be arranged to give

all mean IvBSI.

9, - Casee-e C : In saturation region

In case of V -4V, the devices are operating in the saturation DS

region and equation (6-2) is invalid. Now we have to use Eq. (2-26) , and

give,

1 -*p.C; DS , sat L OX

2(1 + 6)

Note that Eq. (6-3) is a quadratic equation. Taking the square root of

it, we get linear variation of &- with V D S GS '

DS, sat L 2(1 + 6)

- -

V is then extracted using the linear extrapolation method again, T

and the result is plotted along with the results of Case A and Case B in

Fig.6-14 to Fig.6-15. Note that the results for VDs =0.05V and 0.2V ,

do not show a significant difference. However the result of Case C shows

a quite clear deviation when L < 1.5pm from those in Case A and Case B, ?

comparing with Sze's definition of short channel devices discussed in

chapter 2, we know that the devices with L < 1.5pm are actually. short

channel device % .- 3

G is a very important parameter to circuit designers, because it m

is related to the gain factor of the devices. As such we must provide

this needed information for accurate circuit simulation and subsequent

circuit design. Mobility p , being closely related G , also plays as m

Length (micron)

Length (micron)

Fig. 6-14 V at VDs T

-0.05, 4V for short channel devices. (a) at T-300K

and (b) 77K. These results suggest that the short channel effect is

important when L 5 1.5pm.

Width (micron)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Width (micron)

Fig.6-15 VT at V -0.05, 4V for narrow width DS

and (b) 77K.

devices. (a) at T-300K

important a role as G in circuit ,performance, in additi'on to m

demonstrating many fundamdentah properties of the material as well as of

the device. In the rest of this section, I will present the results and

discussions of the variation of both p and G under differerlt devices m

operating conditions and temperatures.

The transconductance G defined in chapter 2, is restated as , m -

where p is 5

we can extract parameters p 0' O O ,

and 6' to characterize the device B

performance at different tempe,ratures .

Also from Eq. (6-6) and (6-7) we see that many temperature effects

are included in the expression for mobility, thus by studying p we can s

determine G . m

Some results are illustrated in Figs.6-16 and 6-17. These two are

the typical results of the variation of G with temperature , for m, max

Temperature (CO

Fig. 6 - 16 Extracted G as function of temperature for short channel m , max

devices at V - 0. BS

Temperature (t-0

Fig.6-17 Extracted G a s funct ion of temperature f o r narrow width m,max

--

devices a t V - 0 . BS

short channel length and narrow channel width devices, respectively. In

these figures, we notice that, i) G is much higher at 77K than at m . rnax

300K due to the larger carrier mobility; ii) G depends on the , max

geometry of the- devices; and iii)' G degradation in short channel m,max

devices is more severe at 77K than at room temperature due to the

surface degradation of the mobility (at 77K surface degradation factor

B o is higher): Quantitatively, G increase 3.3 and 4.7 for device - m , m p

+with L -0.6,um and are 2.4pm , $espectively, as the temperature is .-

lowered to 77K. The results for both narrow width and short channel

devices were extracted and listed in Table 6.1. It is interesting

note that V has larger influence on G BS m , m m

for shorter and d e r

devices than the longer and wider devices, and also for lower 0

temperatures. The surface degradation factor 0 is used to measure the 0

silicon surface roughness scattering. Its dependence on temperature (See

Fig.6-18) shows an increase with decreasing temperature, and potting 0 0

vs. 1/T results in almost a straight line as shown in Fig.6-19. From

this figure, we see that the surface degradation 0 for short channel 0

length devices are greater than the narrow width ones, caused by the

I

larger horizontal field in the channel interacting with the vertical

field. The rate of change as temperature is also different, as listed in

Table 6-1.

As stated in chapter 2, three main different scattering mechanisms - contribute to the effective mobility. Fortunately, the model used in

Eq(2-68) allows us to separate these mechanisms making a detailed study

possible. The quantity p measures the bulk scattering mechanisms, 0

namely the Coulomb scattering and phonon scattering. Tnus,- it is

expect,ed that ,u should be the same for all devices, and not depend on 0

+ 'Length Width

Temperature (i-0

Fig.6-18 Surface mobility reduction factor B e varies as temperature for

short channel and narrow width devices. i

A Length Width

INV. TEMP.(K) X1E+2

Fig. 6-19 B o vs. T-' shoving almost a linear dependence in temperature.

any dev ice paramete rs , except t he temperature. F ig .6 -20 shows v a r i a t i o n

of po wi th temperature . The reason t h a t p f o r vary ing channel width 0 - I

devices i s s l i g h t l y d i f f e r e n t from t h a t f o r s h o r t channel l eng th devices

is because I of t h e former i s about 100 t imes smal le r than t he l a t t e r DS

a

because of d i f f e r e n t device geometry, and hence d a t a f o r varying width

device a r e more no i sy . However, they both show the same t emperap re

dependence, a s i l l u s t r a t e d i n F ig .6 -21 , and t h e r a t e i s a l s o c a l c u l a t e d

and l i s t e d i n Table 6 -1 . I n Fig .6-22 and 6-23 a r e shown t h e r e s u l t s of

t h e s u b s t r a t e b i a s degrada t ion , measured with 0 fo'r s h o r t channel and 'B '

narrow width dev i ce s , r e s p e c t i v e l y . This degradat ion a r i s e s because

i n c r e a s i n g V a l s o i nc r ea se t h e v e r t i c a l f i e l d i n t h Whannel a s s t a t e d BS a@

i n chap t e r 2 ( s e e E q . ( 2 - 3 5 ) ) . Notice i n t he f i g u r e s tha.t a l l BB1s- have

t h e same temperature dependence f o r varying width dev i ce s , and a r e q u i t e

d i f f e r e n t f o r t h e vary ing leng th dev ices . This i s moreso f o r sho r t

channel dev i ce s , a s shown i n t he F ig .6 -22 ; when L > 1.2prn, the

- dependence i s almost t h e same a s F ig .6 -23 , b u t a s L < 1.2pm, t he shape

of t h e curve is changed, and dependence is weaker, a s f o r L - 0.'6pm

dev i ce , t h e dependence is very weak. This can be exp la ined by t he f a c t

t h a t f o r s h o r t e r channel dev i ce s , t he d r a i n and source a r e so c l o s e each

o t h e r t h a t t h e s u b s t r a t e has l e s s l c o n t r o l over t h e channel . A t lower .- <

t empera tures , t h e h o r i z o n t a l dep l e t i on width of t he d r a i n and source i s

narrower , so t h a t t h e c o n t r o l of t he s u b s t r a t e over the channel

i n c r e a s e s , v e r i f y i n g by t he r e s u l t s i n F ig . 6-2k. This f i g u r e showed the

v a r i a t i o n of channel l eng th and width modulation due t o t he d r a i n and

source d e p l e t i o n reg ion width . The r e s u l t agreed wi th a n a l y s i s t h a t

h o r i z o n t a l d e p l e t i o n width of t he d r a i n and source decrease with

lowering of t h e temperature . ( s ee Appendix D ) .

Length Width

Temperature (i-0

Fig.6-20 Measured low field mobility p as function of temperature, 0

extracted from short channel and narrow width devices, respectively.

A Length Width

INV. TEMPAK) X I E+2

- Fig.6-21 Mobility vs. T-' showing the tkmperature dependence of po

Temperature (K)

Fig.6-22 The. 'back gate' b i a s modulation factor 9 vs temperature for B . e

short channel devices. Note the dependence is a function of channel

length

Temperature (K)

Fig.6-.23 The 'back gate' 'bias modulation factor 9 vs temperature for B

narrow width devices. Note the difference between this figure and that

for the short channel devices shown in fig.6-22.

Length O Width \

\

Temperature (K)

Fig.6-24 Channel length and width reduction as function of temperature.

Details are given in Appendix D

The effective mobility peff (defined in Eq.(2-67)) is sometimes

more useful than p and p especially in the analog circuits. Fig. 6-25 s 0'

and Fig.2-26 are the results calculated using Eq.(2-36) and the

parameters extracted, at V - V = 4V. The result indicates the GS T

effective mobility increases for at least 3 times for lowering the

temperatures for all the devices.

For small vDs,

the saturation velocity does not affect

significantly the mobility and the transconductance, but when V is DS

larger, the term with V in Eq. (2-67) can not be ignored, and more of . DS

these will be discussed later in section 6.3.4

The parasitic resistance 'and the channel length and width

modulation are also measured along with G and VT. In particular, the m

parasitic resistance R includes the resistance of the drain and the P

source, the resistance of the depletion width of the source and drain, -

and interconnect resistance. Fig. 6-27 shows the results of R vs. T. As &, P

expected, the total resistance is a decreasing function of temperature,

the reason was described in chapter 2.

6.2.3 SUBTHRESHOLD SLOPE S

The substrate slope S, is considered to be a very important

parameter in down scaling CMOS devices, for reasons described earlier in

chapter 2. In chapter 2 we have seen the small geometry effect on S and

derived the expression for small geometry devices of uniformly-doped

channels, but the devices used in this study'are nonuniformly doped, so - \--

their behavior is different from those predicted by Eqs. (2-73) and

Temperature (K)

Fig.6-25 Effective channel mobility as function of temperature extracted

from experiment with V -0,4V for L-0.6, 2.4pm. BS

50 100 150 200 250 300 350

Temperature (K)

Fig.6-26 Effective channel mobility as function of temperature extracted

from experiment with V -0 ,4V for W-1.0, 3.4pm. as

Length * Width

50 100 150 200 250 300 350

Temperature (Go

Fig.6-27 The parasitic resistance vs temperature. As expected, the total

parasitic resistance (including that of interconnect resistance, drain

and source resistance, a n d contact resistance) decreases as the

temperature, this will reduce the RC delay of the devices. The left

scale (L) is for length and the right scale (R) is for width.

The typical plots of S vs. temperature for short channel and

narrow width devices are shown in Figs.6-28 and 6-29. These figures

showed that S was almost linearly dependent on temperature, in agreement

with Eq. (2-30) in which S is proportional to the temperature. As stated

earlier,. because I for narrow channel devices is much smaller than DS

that of short channel ones, , the noise had more impact on narrow width

devices than short channel ones. he theory described by Eq.(2-73)

predicted that for short 'channel devices, S should be smaller than the

long channel ones, but the resalts showed the S is greater for shorter

channel devices. This can be qualitatively explained as due to a

combination of nonuniform doping of the devices and

drain-induced-barrier-lowering (DIBL) effect. Following the same

analysis 'of Brews [6-2, 6-31, and noting that the channel doping is

opposite to that of substrate, we conclude that S is larger for

nonuniformly doped short channel devices.

Fig.6-30 showed the results of S as a function of channel length

for different substrate biases at 300K. The figure showed that S is

better for higher VBs, because higher VBS will decrease CD (refer

Eq.(2-41) and (2-69)), thus decreasing S. Also from this figure, we

see clearly that when L < 1.5pm, the short channel modulation is

significant. Similar results were also obtained at 77K and these are

shown in Fig.6-31.

For narrow width devices, the narrow channel modulation causes S

to degrade with decreasing channel width, as seen from Figs.6-32 'and

6-33. These two plots along with Fig.6-30 and 6-31 showed that the lower

temperature of 77K can improve S by a factor of about 2.5, although

the factor is less than the theory predicted. The discrepancies may _be

Temperature (1.0

~ i ~ . 6 - 28 Plot of measured subthreshold slope S as temperature for short

channel devices. Notice only L-O.6pm device showed some degradation at

all temperatures, and the others were almost independent of channel

length.

Temperature (K)

Fig.6-29 Plot of measured subthreshold slope S as temperature for narrow

, width devices. The results are different from whose in Fig. 6-28 in i) S

is almost independent of channel width; ii) results are 'noisy', this is

because the level of the drain current is about a 100 times smaller due

to different device geometry, when compared to the short channel

devices, and hence the environment has more impact to the device than

those short channel length devices.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Channel Length (micron)

- Fig.6-30 Plot o f S vs channel l eng th a t different V w i t h T-300K.

BS

Fig.6-31 Plot of S vs channel length for varying V at T-77K. BS

11 3

Channel Width (micron)

C

F i g . 6 - 3 2 P lo t of S vs channel width f o r d i f f e r e n t VBs at T-300K

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Channel Width (micron)

F i g . 6 - 3 3 P l o t o f S vs W f o r d i f f e r e n t V a t Tm77K. BS

caused by the nonuniform channel doping and quality of t h e e d e layer. . +

Fig.6-34 and 6-35 further showed the improvement of S at 77K to that at

300K for both short channel and narrow width devices at zero substrate

bias. More results are listed in Table 6-1.

This section will cover the results of saturation characteristics

of the devices, especially the breakdown voltage (VBD) , saturation

voltage (V ) , substrate current (ISuB), ionization coefficient (a ) DS, sat I

and saturation velocity ( v ) . s a t

6.3.1 BREAKDOWN VOLTAGE (vBD)

The main breakdown mechanism of the devices is the avalanche

breakdown. In chapter -2 the hot carrier effect was extensively

discussed, so here we only present the experimental results.

Avalanche breakdown occurs when the hot carriers (holes) injected

into the drain region create some electron-hole pairs, and these pairs

in turn create more new pairs. This resultant chain reaction leads.to an *

abrupt increase in drain current, causing the device to breakdown, The

avalanche action is enhanced at lower temperatures, because the mean

free path of the charge carriers is longer.

V at varying gate biases are determined by using the IDS-VDs BD

curves. In these experiments, V -2.5V and 5.5V, maximum V applied GS DS

depended on the devices, but for most of the devices, maximum V was DS

taken as 15-20V. The breakdown voltages (VBD) were determined by

measuring the drain voltage at which the drain current was 10% higher

than the prbjected "linear" saturation value [2-20,2-211 , as shown in

Fig.6-36.

Channel Length (micron)

Fig.6-34 A comparison of the variation of S (V -0 ) with L at T-77K,, 300K. BS

Channel Width (micron)

Fig.6-35 A comparison of the variation of S (V -0) with W at T=77K, 300K. BS

Fig. 6-36 Typical IDS-V curve (taken from b2.4pm and W-24pm device at DS

T-300K) to show the definition of VgD. The substrate current rises

abruptly due to the electron current from electron-hole pair generation.

This is shown as the top curve of the figure.

Figs. 6-37 and 6-38 are the plots of VBD for short channel devices

at VGs -2.5 and 5.5V, respectively, while Fig.6-39 and 6-40 are for

narrow width devices. These figures showed that V is higher at lower BD

temperature for narrow width and long channel length deviees than that

at 300K, and opposite is true for very short channel (L<1.5pm) >devices.

The temperature dependence of V is not strong for all the cases. We BD -

also observed that shorter channel and narrower width devices have less

V because, for shorter channel length devices, the horizontal field is BD

stronger, thus VBD is smaller; for narrower devices, the effective

vertical electric field applied to the channel is less, as illustrated

in Fig.6-41. This figure shows for narrow channel ,devices, only part of

the field lines terminated in the channel due to the fringe effect, thus

the effective field is weaker compared with wider channel devices. This

equivalent to apply a smaller V to the gate, from the relation between GS

vGS and VBD (explained later), we know this will lead to a smaller V .

BD -

Fig.6-42 and 6-43 were used to display VBD at 300K and 77K, for VGs

-2.5V and 5.5V. These two graphs further illustrate -the dependence of

devices size on V and different V in which the dependence of L an BD BS '

1. V 1.9 much larger than W, implying that snort channel devices are more BD

susceptible to high field induced breakdown. The temperature dependence

is not so strong for narrow channel width and for devices with L >

1.5j4m; when L < 1.5pm, V is small at 77K. The reason that VBD BD

decreases with V is that the low vertical field causes I smaller. GS DS

From the definition of VBD, we know this means that a smaller IDS rise

is enough to get 10% higher IDS, and hence results in a smaller V . BD

Temperature (K)

Fig.6-37 Results of V as temperature for short channel devices at BD

V - 2 . 5 V . As seen from the graph, V was found very sensitive to the GS BD

channel length, because the shorter the channel, the higher is the field

in the channel.

Temperature (C-0

Fig. 6-38 Results of V vs temperature for six varying channel length BD

devices at V -5.5V. GS

Temperature (K)

Fig. 6 - 39 Results of VBD as temperature for short channel length devices at V - 2 . 5 V . The results show weak channel width dependence of VBD.

GS

Temperature (K)

F i g . 6 - 4 0 Results o f VSD vs temperature f o r narrow channel width devices

a t VGs=5. 5 V .

Wide Channel

(b) Narrow Channel

- . r 1 g . 6-41 3ertical cross secsion of (a) a wide channel and (b) a narrow

t:?annel w i d t h PXGS de-:ice. As seen in this figure that as channel width

sacs narrower, s o m of field lines will not end to the charmel, and the

e5fecc of the gace f L e l d so control the channel is less for the same

e b i b , co.rsared co vile - charnel devices. u

0.0 0.6 I .2 I .8 2.4 3.0

Channel Length (micron)

F i g . 6 - 4 2 Resu l t s of V as func t i on o f c h a m e l l eng th a t V - 2 . 5 .and 9 D GS

5 . 5 V a t T-77K and 300K.

0.5 I .O 1.5 2.0 2.5 3.0 3.5 4.0 f

Channel Width (micron)

Fig.6-43 Results of V,_ as f u n c t i o n of channel w i d t h at V = 2 . 5 and d d GS- -

S.SV a? T=77K and 300K.

This temperature dependence of V can be explained as following: BD

At low

a lower V . BD '

longer, and

that when L

temperature, hot carrier effect is stronger, this will lead

but on the other hand, the effective channel length is

this will lead a higher VBD. From the results we conclude

< 1.5pm, hot carrier effect is stronger than the channel '

length extension; when L >-1.5pm, the opposite is true.

As shown in Fig.6-36, that when IDS begins to deviate from the

projected straight line, the substrate current I increases abruptly, SUB

too. This sugges'ts that I can also be used as a parameter for SUB

measuring the device breakdown. Fig. 6-44 and 6-45 showed the resultsu of

I sm (at V D S 4 ) versus temperature for both varying L and W devices. BD

These two figures shows an increase in I with temperature for all the SUB

devices, indicating avalanche electron-hole generation is enhanced at

low temperatures, as predicted. ~ u t a more profound results are plotted

in Fig.6-46 and 6-47. These two figures shod the

(at V -V ) being almost a constant of about 0.03 DS BD

channel length from 0.6 to 12p1, and is almost

temperature. These results supports our proposed

that of using I to define V .- For example, if SUB BD

ratio of I to I SUB DS

to 0.045 as varying

independent of the

breakdown criteria,

we define I - SUB'IDS

0.04 as a new breakdown condition, we basically can get the same V as BD

those obtained using the 10% IDS rule used in the thesis. This new

definition (ISUB/IDS) is more accurate than the earlier criteria,

bacause it is difficult to find the 10% greater I than projected DS

linear saturation current exactly, especially for shorter channel

devices due to the channel length modulation.

Temperature (K)

- 5 - 1 ( a c V ) .;s. t e s ? e r a t l x e f o r na r rov channel width d e v i c e s . i - z , . - 5-3 E 2

Temperature (K)

F i g . 6 - 4 6 ISJd"DS

(at V ) vs. temperature for short channel length 33

deTr i ce s .

Temperature (K)

Fig.6-67 I SUB'IDS

(at V ) vs . temperature f o r narrow channel dev i ce s . BD

Althou~h I s va ry with -dev ice geometry, IsuB'TDs

i s a lmost independent sm on & v i c e geometry.

6'3.2 'DS, s a t

For analog applications, V is an important parameter which DS, s a t

determines how large the dynamic range will be. Eq. (2-26) states that

the greater the threshold voltage, the smaller the V DS, s a t

but

Eq.72-26) did not include the velocity saturation effect, which is

dominant for short channel devices. Taking this effect into account, the

expression [6-41 is modified to give:

VGS - VT u L v - - s a t + DS, s a t

1 + 6 ps 1 + 6

where p is the surface mobility, and u is the maximum velocity (or s s a t

saturation velocity) of the charge carriers in the channel which will

be discussed.in the later section. The first term is due to the pinchoff

effect and the second term is due to the velocity saturation. When first

term is much smaller than the second term (e-g. for long channel

devices), V DS,sat

approaches to the first term, and vice versa.

Experimentally, it is difficult to determine the value of V s o sat

V in this work is calculated from the above expressipn, and the DS, s a t

results are shown in Fig.6-48 and 6-49.

As shown in Fig. 6-48, for larger V (e. g. V -5.5V), the GS GS

saturation velocity decreases with channel length, as predicted by

Eq. (6-8), since if V is large, the second term in Eq. (6-8) is larger GS

than the first one, so the dominant is the second; i.e. V DS, s a t

, decreases with channel length. At V =2.5V, the competition of these two GS -

causes the dependence of L on V weaker. At low temperatures, DS, s a t f

- important even at V - 2.5V, as shown in Fig. 6-48. Fig. 6-49 showed

GS

V essentially were controlled by the pinchoff effect, and DS,sat

decreases with the channel width, because V increases with the'channel T

width.

These two figures also showed that V was less at low DS, sat

temperatures. Fro3 Eq.(6-8), we realize that this is inevitable because,

1) the saturation velocity does not increase as much as ps

as

temperature decreases from 300K to 77K, (v only.increases-20%, see sat

6

section 6.3.4); 2) V normally decreases with temperature, because the T

surface potential is sensitive to the temperature; resultlng in a

smaller V DS , s a t

at 77K.

6.3.3 I,, AND aI

As mentioned in section (6.3. I), substrate current I could be SUB

used to monitor the degree of degradation and breakdown at high drain

biases. A more commonly used parameter, the

coefficient, a is also used to monitor breakdown I'

[2-111, a was given as I

impact ionization

of the devices. From

where AL is the length of the pinchoff region given in chapter 2.

Channel Length (micron)

~ i g T 6 - 4 8 Saturation voltage V vs. channel length for V -2.5 and DS, sat GS

5.5V at 300K and 77K. The results show V decrease with channel . DS, sat

length, indicating saturation velocity is a dominant factor in .

determining V DS , sat

0.5 1 .O 1.5 2.0 2.5 3.0 3.5 4.0

Channel- width (micron)

Fig.6-49 Saturation voltage V vs. channel width for VG5=2 . 5 and. DS, s a t

5 . 5 v .

All the paaeters in Eq.(6-9) were extracted experimentally from

the I -V curve in the saturation region at V -4V, V - 0,2,4V. IsuB DS GS DS BS

here is the maximum I SUB ' and IDS is taken at the VGS with' which IsuB is

% maximum. B~cause maximum I occurs in saturation region, AL was SUB

extracted from the saturated I -V curves at V -4V, and is described DS DS DS

as follows:

From Eq.(2-53)

A DS, s a t

I * - DS,sat 1 - AL/L

* where I and I are the saturation drain current for lo& and

DS,sat DS,sat

short channel devices, respectively.

Taking the derivative of Eq.(6-lo), we have

a I* DS,sat

a I DS, s a t

= - a v

D s a v ~ s [ 1 - AL/L ] L'lds. s a t

a AL

Experimentally "the conductance of the short channel devices was

almost a constant in the saturation region, so integrating Eq.(6-12), we

have

I

where V is a drain voltage above V and below V . D S DS BD

Carrying out the integration, we have

finally @

This method of getting AL is more accurate than directly extr,acted b

from Eq.(6-10).

From Eq. (6-14) , we see AL is only significant for short channel

devices, because when L is long, gD is so small that AL is almost

negligible and I was also not significant below V thus in our SUB BD'

experiments, only a for short channel length devices was extracted. I

The extracted AL for 300K and 77K is plotted in Fig.6-50. ..This

figure shows AL is larger at 300K than at 77K, caused by the decrease in

the effective channel length at 300K (referring Appendix D).

Fig. 6-51 is the result of the measured ionization coefficient a I

at 300K and 77K. This figure indicated that at 77K the impact ionization -7

coefficient a increases 6.3 times as temperature decreases to 77K from I

300K, due to the hot carrier effects, which agrees with our previous V BD

results. a is very sensitive to V when V increases from 0 to 4V, I B6 ' BS

a increases -2.3 times at 77K and -2.1 tim& at 300K. This suggests I -

that unless proper design for low temperature operation is done, hot

carrier effect will cause a long term reliability problems at cryogenic

- temperatures. Another interesting result is to note that a is higher . s . I

Mask Length (micron)

F i g . 6-50 Variat ion of AL due t o pinchoff with drawn channel length. As . expected, AL i s l a r g e r f o r shor t e r L devices.

Channel Length (micron) "

Fig. 6-51 Impact ionization coefficient a vs. channek length, with I

V -0,2,4V, and T-300K and 77K, as indicated in the figure. The figure 9s

showed that a is almost proportional to L and larger for higher VBS or I

low temperatures. i

for longer channel length because, the impact' ionization coefficient a I

electric field dependent. A simple model [ 6 - 5 1 gave the relation between

a and electric field strength as I - , .

where E is the horizontal field in the drain depletion region, and n is X

between 1 to 2. From Fig.6-48 and 6-50, we see that the electric field i

(V -V )/AL is weaker for short devices, and according to DS DS, s a t

Eq.(6-15), a is smaller for short channel devices. I b

Saturation velocity u is considered very important because this s a t

f

paremeter will ultimately limit the speed of a MOS device, For electrons

and holes, v is the same-, this suggests the maximum operational speed s a t

of a PMOS and NMOS device should be the same. When device size is \

smaller, PMOS devices show a larger improvement in sdeed over that of -

NMOS devices because of the same v . s a t

The v and critical horizontal electric field E are related by s a t c

v = p-E . s a t c

e

so knowing v and p we can calculate E . s a t c

v was extracted from the I -V curves with vDS = 4V. Firstly, s a t DS GS

the saturation transconductance G was .extracted from the G -V m,max m GS

curve. Then using the equatim below [ 6 - 6 1 , we solve for u s a t

iteratively .\.

G = W*C * U rn , rnax ox s a t

where B and p were extracted in the ohmic region previously: The 0 0

d

result for the variation of u with temperature is plotted in sat

Fig. 6-52. The dasheh line above the experimental data is the theoretical

results from [Z-111, and the solid line represents the same result as

that of dashed line but shifting down its value by 2x10~ cm/s to fit the

experimental result. The disagreement is probably due to the surface

roughness which Powers the saturation velocity as well as the mobility. )i

In the reference [2-111, however, u was calculated in bulk silicon, s a t

so the value is higher. It is interesting to note in the figure that

u does not change as much as p does with the as lowering of.the s a t 0

temperature; u only increases by about 1.2 times, while p increases s a t 0

about 7 times. The other item that the figure did not show but more

profound is the fact that theoretical u is the same for both s a t

electrons and holes. This means that because of velocity saturation in

very short channel devices, the saturation current or tRe load drive

capability (measured by the saturation drain current) of PMOS is

comparable to NMOS devices with same device geometry. At low

temperatures, we see the drive capability is even higher than at 300K,

and this may result in the same device W/L ratio for both NMOS and PMOS

devices of very short channel lengths. Some of important results are

also listed in Table 6-2.

Saturation Ve ity in PMOS vs. Temperature

Temperature (K)

-. ils.6-52 Saturation velocity of holes versus temperature. The s p b o l is

tke experimental result, ar.d lines are the theoretical results. The

clashed line is tht in bulk silicon, and the solid line is the Slt

rasult ' of che same cheory but shifted down by 2 x 1 0 ~ cm/s to fit the

es7erimental resul?.

6.4 STRESS CHARACTERISTICS

The measured stress characteristics here cover the linear

characteristics of the devices after stressing,' particularly VT, G , m

po , d o and S .

It has been suggested that the hot carrier effect is more severe

at lower teffperatures, and presumably can cause more degradation to the

characteristics of the device. So this experiment-was to investigate how

the degradation depended on temperature and device dimensions. I

All stress test were done at room temperature, then the devices

were measured at different temperatures. The stress conditions were:

apply a -4V DC to the drain ,and gate terminals, while keeping other \

terminals grounded. The stress- time are 15, 150, 1500, ?and 7200 seconds,

respectively. However, the experimental results showed little change for

15 and 150 seconds stress time. The stress voltage applied to the drain

and gate was chosen to be -4V, because at higher stress voltage, i.e.

- 5 V , a few of the devices were destroyed, -4V then was chosen for the

stress experiment. In the following sub-sections, the results of

important linear devices parameters, VT, G , p , and S were presented and

discussed.

The results were demonstrated in Fig.6-53 and 6-54 for four' short

channel devicis and four narrlw channel width devices, respectively. It

was found that V shows only a slight decrease after over 2 hours of T

stress and this change is insensitive to temperature for both varying

channel length and channel width devices. These results indicate that

Temperature (K)

t=O L=0.6

t=O L=0.9

t=O L= 1.2

t=O L=2.4

t=2 hrs L=0.6

+=2 hrs L=0.9

t=2 hrs L= 1.2

t=2 hrs L=2.4

Fig .6 -53 V v s . T , f o r s h o r t . channel dev i ce s o f L-0 .6 , 0 . 9 , 1 . 2 and T

2 . 4 p m , be fo re and a f t e r 2 hours ' s t r e s s . V . s l i g h t l y decreases and this T

change does n o t dependent on t he ope ra t i ng temperature .

' Temperature (Go

t=O W= 1 .o t=O W= 1.3

t=O W= 1.6

t=O L=3.4

t=2 hrs W= 1 .o t=2 hrs W=13

t=2 hrs W= 1.6

t=2 hrs W=3.4

Fig.6-54 Variation of V before and after stress for two hours, as a T

funccion of temperature, for narrow width devices. V slightly decreases T

and the change does not dependent on the operating temperature.

t he ho t c a r r i e r e f f e c t on V is small . It a l s o shows t h a t under the T

s t r e s s condi t ion ( -4V on the gate and d ra in te rminals ) , the devices have

s t a b l e V ' s . T

Fig. 6-55 and 6-56 showed .experimental r e s u l t s of G . . In m . max

Fig. 6-55 we observe two r e s u l t s : one i s t h a t G f o r shoreest devices m,max

decreases a t a l l temperatures, the o the r i s t h a t a l l devices degrade

more a t 77K_ than a t higher temperatures. These r e s u l t s conformed our

e a r l i e r d iscuss ion i n chapter 2 t h a t ho t c a r r i e r e f f e c t i s more severe

a t lower temperatures. Since the hor izonta l e l e c t r i c f i e l d i s s t ronger

f o r s h o r t e r channel devices , these these devices a r e more suscept ib le to

degradat ion, a s v e r i f i e d by the r e s u l t s of Fig.6-55 Fig.6-56 shows the

s t r e s s r e s u l t s f o r varying width devices . Fig.6-57 shows the r e s u l t of

before and a f t e r s t r e s s i n g . I n t h i s f i g u r e , the low f i e l d mobili ty

decreases s i g n i f i c a n t l y a f t e r the s t r e s s , e s p e c i a l l y a t low

temperatures, a s some of the charges trapped near the d ra in region

c r e a t e s a c o n s t r i c t i o n t o the cur rent flow, and hence decreases G . The m

r e s u l t of Fig.6-58 indica ted the surface s c a t t e r i n g modulation was

a f f e c t e d very l i t t l e a f t e r the s t r e s s . The decrease i n G ' and p can m,rnax 0

be explained by some of the charges t h a t a r e trapped i n the d ra in end,

and these trapped charges cons t ra in the cur rent flow, r e s u l t i n g i n a '

reduced G and p . m.max 0

+ +

* A

Q " ' A A

8 v

7

Temperature (K)

t=O L=0.6

t=O L=0.9

t=O L= 1.2

t=O L=24

t=2 hfs L=0.6

t=2 hrs L=0.9

t=2 hrs L= 1.2

t=2 hrs L=2.4

Fig.6-55 G vs temperature for G 0 . 6 , 0 . 9 , 1 . 2 an& 2.4prn, before and m , max

after 2 hours' stress. The result shows the degradation is only

important for very short channel devices ( G 0 . 6 p m ) .

Temperature (K)

hrs .O hrs .3

hrs

Fig.6-56 G vs temperature for W-1.0,1.3,1.6 and 3 . 4 p r n , before and m,max

after 2 hours' stress. The result shows little degradation has occurred.

I emperature '(K)

Fig.6-57 p vs temperature, before and after 2 hours' stress.It is 0

extracted from for 4 short channel and 4 narrow length devices. The

results show that the degradati~n is more pronounced at 77K than at

higher temperatures.

Temperature (K)

F i g . 6 - 5 8 B o v s . temperature , be fore and a f t e r 2 hours ' s t r e s s . I t shows

t he s u r f a c e modulation i s n o t a f f e c t e d by t h e s t r e s s .

S is also measured after stress, because we wanted to check if the

subthreshold region is degraded because of the stress. This is important

since we know the improved subthreshold behavior is one of the most

important properties for low temperature operation of CMOS devices. The

results were obtained with the procedure introduced in chapter 5, and ,

shown in Fig.6-59 and 6-60. For short channel length devices, S decrease

very slightly after the stress, and the degradation due to the stress at

low temperatures was even smaller than at higher temperatures. Fbr

longer channel devices and narrow channel width devices, S was slightly

larger after stress, but not significantly. This result shows that not

only the diffusion current (in strong inversion region) is affected, but

also the drift current (in sub-threshold region) is lowered slightly

because of trapped charges. It implies that in order to m.inimize the hot '

carrier effect, eithepneed new device structure or some new material

which is less susceptible to high field degradations.

Temperature (Go

t=O L=0.6

t=O L=0.9

t=O L= 1.2

t=O L=24 --

t=2 hrs L=0.6

t=2 hrs L=0.9

t=2 hrs L= 1.2

t=2 hrs L=2.4

Fig.6-59 S before and after stress for 4 short channel length devices,

as a function of tempsrature. Only for shortest device S is worse after

stress, the other devices don't show much degradation. .

Temperature (K)

t=O W= 1.0

t=O W=13

t=O W= 1.6

t=O W=3.4

t=2 hrs W= 1 .o t=2 hts W=13

t==2 hrs W=1.6 *

t=2 hrs W=3.4

Fig. 6-60 S before and after stress for 4 narrow channel width devices,

as a function of temperature.

Table 6-1 Some of the Physical Parameters as a Function of Temperature

--- -- -

Physical quantity

lSUB/lDS

v DS, sat t

U sat

Q -

- Relation with T

1.532 - 0.0018T (V)

1.24 +l. 7xl0-'~ (V)

- 0.42 + 9. ~ x ~ o - ~ T (V)

0.35 + 0.0012T

0.24 + 0.0014T

-219 + 1 . 1 0 ~ 1 0 ~ ~ (cm2/Vs)

-0.034 + 41/T (l/V)\

-0.02 + 23/T (l/V)

0.01+9.6/T (lp)

0.01+14.9/T (1p)

28.4 + 0.087~ (n) 1

3.63 + 0.007T (kn)

(N/A) ('.'m/v )

- 4 2 41.4-0.076T+9x10 T (mV/dec)

-6 2 18.8+1. ~XIO-~T- 9.2~10 T (V)

- 7 2 0.035+5.6~10-~~-1.6~10 T

(N/A) 0')

2.1~10'/(1+0.8e (Tl600) 1 (cm/s>

( N/A

$,The data is for device with Li2.4p1, W-24pm

4 The data is for device with G12pm, W=3.4pm

Jalues at 300K, 77X

Table 6-2A Some Physical Parameters as a Function of Device Geometry

Physical quantity

I t SUB

1 t StlB

v DS, sat 4

Relation with Geometry

1.03 - 0.041/~' (V)

1.04 + 0.136/W (V)

78.76 + 6.59/L2 (mV/dec)

92.9 - 1.35W (mV/dec)

20.5 - 3.86/L (V)

18.3 - 0.35/W (V)

0.029 + 0.13/L (A)

- 3.67~10-~+ 0.59x10-~~ (A)

0.022 + 0.0069L

0.046 + 0.0002W

3,31 - 0.496/L (V)

3.31 + 0.023W (V)

t The data is varying channel length.

4 The data is varying channel width

Values at two ends

0.92 j 1.02

TabTe 6-2B Some Physical Parameters as a Function of Device Geometry

Physical quantity

I t SUB

I f SUB

ISUB/IDS

v DS , sat" f

Relation with Geometry

1.43 - 0.041/~' (V)

1.47 + 0.124/W (V)

28.5 + 4.5/~' (mV/dec)

34.3 - 2.94W (mV/dec)

20.87 - 4.36/L (V)

18.6 - 0.43/W (V)

0.05 .+ 0.176/L (A)

-4.74~10-~+ 1.67~10-~~: (A)

0.022 + 0.007L

0.047 + 8. ~ ~ X I O - ~ W

2.91 - 0.756/L (V)

3.03 + 0.028W (V)

- 3.86x10-~ + 1.54x10-~~

t The data is varying channel length.

Jalues at two ends

$ The data is varying channel width.

CHAPTER 7 " CONCLUSIONS AND RECOMMENDATIONS

In this chapter, I will give a summary on the work finished and

important results which potentially can be used in future PMOS and CMOS

device and circuit designs. As a continuation of this research, I will

also suggest the future works based on this research.

7.1 CONCLUSIONS

In this work, the DC characteristics of small geometry PMOS

devices were studied in detail. In general, small geometry effects on

the device characteristics A were extensively investigated, and the most

important results were listed at the end of chapter 6. I will, in this

' section, give a short summary of the results and implications for future

VLSI .

At low temperatures, some new effects that a device designer

should know are 1) at low temperatures, the effective channel length of

the PMOS devices is longer than that at room temperature, due to the

decrease of the horizontal depletion widths; 2) hot carrier effect is

stronger at low temperatures and 3) p and G are higher due to reduced 0 m

carrier scattering in the channel. The first two effect compensates each

other to certain extent, that short channel effect is less at 7 7 K ; for

example, measured short channel effect on V S, B g and IsUB/IBD for a T'

short channel PMOS device is smaller at 7 7 K . This means that the device

size can be made even smaller without suffering too much small channel

effects. On the other hand, however, the more severe hot carrier effect

at 77K degrades 3 and VBD, suggesting new technology or device 0

structure is required (e.g. to reduce surface roughness, use a buried

channel structure).

The important numerical results of device parameters and their

dependence on the temperature are especially important for cryogenic

circuit designers, and they are provided below as a guide:

A) p in ear characteris tics

i) VT increased with T at a. rate of 1.8mV/K, small geometry

effects are pronounced when L < 1.5pm, or W < 1.5pm at all

temperatures.

ii). G increased by a factor of 3 for shortest device and 4.8 rn

for longest device on lowering T to 77K from 300K. a =

iii) p increased 7 times; %f f

increased more than 3 times for 0

all devices at (VGS-VT) =4V, and VBS = 4V. At the same time,

surface degradation factor 9 increased 5 times. 0

iv) S increased 2.4 times for shortest device and 3 times for

longest device. S degraded significantly when L ' < lpm;'

B) Saturation characteristics \

i) V varied from 14V to 19V with increasing the chafinel BD

lengths. V increased with temperature when L < 1.5pm, and BD

decreased with T when L > 1.5pm, but the dependence with

temperature was weak. (These results were taken at V - 5.5V) GS

I (at VBD) increased 1.4 times for shortest device and 2.8 SUB

times for longest devices. However 'SUB''SD (at V ) seemed BD

insensitive to T.

ii) V was lowered at 7 7 K , by 23% for shortest and 18% for DS, s a t

longest devices.

6 iii) u increased from 9.2~10 (cm/s) at 300K to 1 . 1 ~ 1 0 ~

sat

(cm/s) at 77K, and the dependence on T was almost linear.

iv) a changed linearly with channel length, and increased 6.3 I

times at 77K for G0.6pm devices, indicating a pronounced hot

carrier effect at low T.

C) Stress characteristics

DC stress results showed a slight degraded in G , po and 0 the o '

effect on VT and S

believed to be the

oxide interface).

was not very significant, and degradation is

trapped charges in the channel (not at the

7.2 RECOMMENDATIONS

Based on this thesis, and work previously accomplished at

SFU by other researchers, new research can be continued in the

following areas:

1. Propose model(s) for breakdown voltage especially at cryogenic

temperatures.

2. Do stress test with longer stressing time (e.g. a few days or

weeks) at 77K to study its degradation and charge relocation.

3. Check thermal recycling of these devices between 300K and 77K, 1

re-measure some of the physical parameters as recycling time at

different temperatures.

4. Study DIBL effect of the short channel devices [ 6 7 ] . Some

preliminary investigation of DIBL effect on short channel PMOS devices

showed DIBL effect was weaker at 77K, but more work is needed, and new

model(.s) may be proposed.

Reference

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[I-151 M.J. Deen "Digital characteristics of CMOS devices at cryogenic Temperatures", IEEE J. Solid-state Circuits, vo1.24 (I), pp158-164 (1989)

[I-161 M.J. Deen " Cryogenic temperature dependence of voltage transfer characteristics of CMOS inverters", Solid State Electronics, vo1.31(8), pp1299-1308 (1988).

[I-171 M.J. Deen, C.Y. Chan and N. Fong "Operational characteristics of a CMOS microprocessor system at cryogenic temperatures", Cryogenics, - vo1.28(5), pp336-338 (1988).

[l-181 M.J. Deen "Operational characteristics of CMOS op-amps at cryogenic temperatures" Solid State Electronics, vo1.31(2), pp291-297 (1988).

[l-191 J. Wang, Z.P. Zuo and M.J. Deen "Performance characteristics of short channel PMOS devices: Implications for CMOS VLSI", Canadian Conference Electrical Engineering, Vancouver, BC, pp776-780, (November 1988).

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[I -211 J. Wang and M.J. Deen "Analyzing short Channel Effects in PMOS Devices", accepted at Canadian ~onfeience on Electrical and Computer Engineering, Montreal, 17-20, September (1989).

[I-221 Z.P. Zuo, M.J. Deen and J. Wang "A New Method for Extracting Short Channel Length and Narrow-Channel Width MOSFET Parameters", accepted at Canadian Conference on Electrical and Computer Engineering, Montreal, 17-20, September (1989).

[I-231 Z.X. Yan and M. J. Deen "A New Method of Measuring the Threshold Voltage for Small Geometry MOSFETH,,accepted at Canadian Conference on Electrical and Computer Engineering, Montreal, 17-20, September (1989).

[l-241 M.J Deen, J. Wang, Z.X. Yan, and Z.P. Zuo "Substrate Bias Effects in Short Channel Length and Narrow Channel Width PMOS Devices at Cryogenic Temperatures", Proc. of the IEEE Workshop on Low Temperature Electronics, Vermont, August (1989).

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[6-71 M.J. Deen and Z.X. Yan, "Substrate Bias Effects on Drain Induced Barrier Lowering in Shsrt Channel PMOS Devices", submitted for publication (1989)

An easy way to describe the work function is to use the energy

band diagram of the metal-semicogductor interface. At equilibrium, the

energy band diagram of the interface is illustrated in the Fig.A-1. b

The work function difference between a piece of metal and a .,

semiconductor (4 ) is defined as ms

where 4 , 4 is the work function of metal and semiconductor, m 8

respectively.

From the figure, 4 for a p-type material is given by S

where K, is the electron affinity of the semiconductor; E is the energy B

band-gap, and Ip is the potential difference between the Fermi level E B F

and the intrinsic Fermi' level E. of the semiconductor. I

Thus &

Sometimes the metal is replaced by a heavily-doped semiconductor

+ material, e.g. n doped silicon. In this case, 4 is the work function

m

of the n+ doped silicon. The conductivity of the semiconductor may

change as the temperature depending on the doping and type of S.

semiconductor.

* i . \ Vo.cuurn Leve l

Semiconductor .

Fig.A-1 Energy diagram for calculating the work function [Z-111

In strong inversion, the total surface charge density is given by - ' .

where $(Y)~ is the depletion surface charge density, given by [2-111

and Q (y) is the inversion charge density given as I

Substitute Q (y), we have s

In strong inversion region, the dominant current component is the

drift current, calculated easily as following.

The conductivity of the channel u(x)~ can be approximated by

>/' \ where p(x) is channel mobile charge density.

The channel*conductance G is, by integrating Eq.(B7) along then D

channel,

Under the assumption that channel mobility. is constant along the - ,

channel, G becomes D

b

Integrating the above equation again with respect to V we get DS'

One thing remained is the assumption that the channel mobility is

a constant along the channel. This assumption is good for long channel

devices, in sub-micron devices, the electric field distribution is

two-dimensional, and the channel mobility may vary along the channel.

Under this circumstance, a numeric result is needed.because of the

complex nature of electric fields dependence of mobility.

t - The x-y coordinate system was indicated in Fig.2-1. c&-

A approximated expression for surface charge

inversion can be written as

density Q in weak

The inversion capacitance C is given by D

where a 2 ( r / r , ) (d/LD) s . S1

The voltage relation in a MOS device gives

Using Eq.(C2), Eq.(C6) can be expressed as

a $ Next step is to calculate A . av

GS

r" Taking the derivative of Eq.(C.7) with respect to V and with -

GS'

Eq.(C.S), we have <

hence we have

Since the drain current in the weak inversion is given [6-2, 6-31

by

a[Ln(ID,)l Now we calculate

- a ( $ > . From Eq.(C10), we have

Taking square on both sides of the Eq.(CS),

Substitute Eq.(C.11), we have

From the definition of the subthreshold slope S, we have-

The horizontal deplotion width of at the drain end (yd) and the

source end (y ) are given, respectively by [Z-111 s

and

4 where Vbi is the build-in potential of the p-n junction, here is of the

+ junction of degenerated doped p and the substrate.

By definition, V is b i

where 'F,s(i)

is the Ferrni potential of either p- or n-type

semiconducting material. In our case, 4 is the Fermi potential of F, sl

the drain or source, and 4 is that of the substrate. F,s2

For degenerated doped- semiconductor, the Fermi energy 4 is F,sl

given by

where E is the energy gap of the substrate material. g

The Fermi potential of the substrate ( is given by F, s2

where n i'

the charge density of the intrinsic semiconductor, and a

numeric expression for n is [ Z - 3 9 1 i

16 312 '

n- - 3.87~10 T exp i ( -',0•‹ 1 .

Using these values, and took VDs = 0. O ~ V , (y + y ) is calculated and t d

plotted in Fig.D-1.

Temperature (K)

Fig.D-1 Plot of the horizontal depletion width of 'the drain and the

source, calculated for V - 0.02V. DS