Chapter4 - Combinational Circuit Building Blocks

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Transcript of Chapter4 - Combinational Circuit Building Blocks

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    Week Group 1 Group 2 Remarks

    Week 1 No Class Dr. Sofian Assignment 1

    Week 2 Mr. Mahazani Dr. Sofian

    Week 3 Dr. Sofian Dr. Sofian Assignment 2Week 4 Dr. Sofian Dr. Sofian

    Week 5 Dr. Sofian Dr. Sofian Assignment 3

    Week 6 Dr. Sofian Dr. Sofian

    Semester Break

    Week 7 Dr. Sofian Dr. Sofian Mid-Term Test

    Week 8 Mr. Mahazani Mr. Mahazani

    Week 9 Mr. Mahazani Mr. Mahazani

    Week 10 Mr. Mahazani Mr. Mahazani

    Week 11 Mr. Mahazani Mr. Mahazani

    Week 12 Mr. Mahazani Mr. Mahazani

    Week 13 Mr. Mahazani Mr. Mahazani

    Week 14 Mr. Mahazani Mr. Mahazani

    Revision Week

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    Final Exam

    Saturday (10 Jan 2015)

    Venue - not yet decided

    11:30 1:30 PM

    4 Questions

    Answers all

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    Reference books

    Main texbook:

    Fundamentals of Digital Logic with Verilog Design, 3rd

    Edition, Brown and Vranesic, McGraw Hill, 2013.

    Other textbooks:

    Digital design: with an introduction to the Verilog

    HDL, 5thEdition, Mano and Cilleti, Pearson, 2012.

    Digital design and computer architecture, 2nd

    Edition,David Harris and Sarah Harris, Morgan Kaufman, 2013

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    Time Table (Group 1)

    Mon 2:00 4:00 PM DK8

    Tue 12:00 1:00 PM DK8

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    Short revision

    Truth table

    Logic gates

    Boolean algebra Synthesis (SOP & POS)

    Karnaugh map

    Number representation

    Adder

    Multiplier

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    Chapter 4

    Combinational-CircuitBuilding Blocks

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    Combinational Circuits

    Combinational circuits are stateless

    Output is dependent only on its inputs

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    Multiplexer

    Combinational circuit that selects binary

    information from one of many input lines

    and directs it to one output line

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    Figure 4.1. A 2-to-1 multiplexer.

    (a) Graphical symbol

    f

    s

    w0

    w1

    0

    1

    (b) Truth table

    0

    1

    f

    fs

    w0

    w1

    (c) Sum-of-products circuit

    s

    w0

    w1

    (d) Circuit with transmission gates

    w0

    w1 f

    s

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    Figure 4.2. A 4-to-1 multiplexer.

    f

    s1

    w0w1

    00

    01

    (b) Truth table

    w0w1

    s0

    w2

    w3

    10

    11

    0

    0

    1

    1

    1

    0

    1

    fs1

    0

    s0

    w2

    w3

    f

    (c) Circuit

    s1

    w0

    w1

    s0

    w2

    w3

    (a) Graphic symbol

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    Figure 4.3. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

    0

    w0

    w1

    0

    1

    w2w3

    0

    1

    f0

    1

    s1

    s

    Larger multiplexer can also be constructed from

    smaller multiplexers

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    Figure 4.4. A 16-to-1 multiplexer using 4-to-1 multiplexer.

    w8

    w11

    s1

    w0

    s0

    w3

    w4

    w7

    w12

    w15

    s3

    s2

    f

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    Figure 4.5. A practical application of multiplexers.

    x1 0

    1

    x2 0

    1

    s

    y1

    y2

    x1

    x2

    y1

    y2

    (a) A 2x2 crossbar switch

    (b) Implementation using multiplexers

    s

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    Figure 4.6. Synthesis of a logic function using multiplexers.

    (a) Implementation using a 4-to-1 multiplexer

    f

    w1

    0

    1

    0

    1

    w2

    1

    0

    0

    0

    1

    1

    1

    0

    1

    fw1

    0

    w2

    1

    0

    (b) Modified truth table

    0

    1

    0

    0

    11

    1

    01

    fw1

    0

    w2

    10

    f

    w2

    w1

    0

    1

    fw1

    w2

    w2

    (c) Circuit

    1

    2

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    Figure 4.7. Implementation of the three-input majority function

    using a 4-to-1 multiplexer.

    w3

    w3

    f

    w1

    0

    w2

    1

    (a) Modified truth table

    (b) Circuit

    00

    0

    1

    1

    1

    0

    1

    fw1

    0

    w2

    1

    0 0

    0 1

    1 0

    1 1

    0

    0

    0

    10 0

    0 1

    1 0

    1 1

    0

    1

    1

    1

    w1 w2w3 f

    0

    0

    0

    01

    1

    1

    1

    w3

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    Figure 4.8. Three-input XOR implemented with

    2-to-1 multiplexers.

    (a) Truth table

    0 00 1

    1 0

    1 1

    01

    1

    0

    0 0

    0 1

    1 01 1

    1

    0

    01

    w1w2w3 f

    00

    0

    0

    1

    1

    11

    w2 w3

    w2 w3

    f

    w3

    w1

    (b) Circuit

    w2

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    Figure 4.9. Three-input XOR function implemented with

    a 4-to-1 multiplexer.

    f

    w1

    w2

    (a) Truth table (b) Circuit

    0 0

    0 1

    1 0

    1 1

    0

    1

    1

    0

    0 00 1

    1 0

    1 1

    10

    0

    1

    w1w

    2w

    3f

    0

    0

    0

    0

    11

    1

    1

    w3

    w3

    w3

    w3

    w3

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    Standard MSI Multiplexers

    Standard MSI Multiplexers

    74151A (8-to-1)

    74150 (16-to-1)

    74153 (2-bit 4-to-1)

    74157 (4-bit 2-to-1)

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    Standard MSI Multiplexers 74151A

    74151A

    8-to-1 multiplexer

    Output equation

    Strobe (~G) acts as enablesignal

    2ndoutput W is just

    complement of Y

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    Standard MSI Multiplexers 74150

    74150

    16-to-1 multiplexer

    Output equation

    One strobe signal (~G)

    Only one output (W)

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    Standard MSI Multiplexers 74153

    74153

    2-bit 4-to-1 multiplexer

    (contain two 4-to-1

    multiplexers)

    Have 1 enable signal.

    Module behavior:

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    Standard MSI Multiplexers 74153

    Alternative Symbol

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    Standard MSI Multiplexers 74157

    74157

    4-bit 2-to-1 multiplexer

    Have only 1 control signal

    (S) Have 1 enable signal (~G)

    Multiple 74157 can be used

    to create other multiplexer

    configurations of different: Path widths, and

    Number of inputs.

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    Standard MSI Multiplexers 74157

    Extending path widths

    Two 74157s are used to

    create 8-bit two-input

    multiplexer.

    Both modules are

    controlled with the same

    select signal (S).

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    Standard MSI Multiplexers 74157

    Extending number of

    inputs.

    Two 74157s are used to

    create 4-bit four-inputmultiplexer.

    S1 selects only 1 module

    (and turns off the other)

    S0 selects of one of the two4-bit input of the enabled

    module.

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    28

    Decoders

    n-to-2n decoder is a multiple-output

    combinational logic, with:

    n input lines, and

    2n output lines.

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    Figure 4.14. Binary decoder.

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    Figure 4.15. A 3-to-8 decoder using two 2-to-4 decoders.

    w2

    w0 y0y1y2y3

    w0

    En

    y0w1 y1

    y2y3

    w0

    En

    y0w1 y1

    y2y3

    y4y5y6y7

    w1

    En

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    Figure 4.16. A 4-to-16 decoder built using a decoder tree.

    w0

    En

    y0w1 y1

    y2y3

    y8y9y10y11

    w2

    w0 y0y1y2y3

    w0

    En

    y0w1 y1

    y2y3

    w0

    En

    y0w1 y1

    y2y3

    y4y5y6y7

    w1