Chapter 10shodhganga.inflibnet.ac.in/bitstream/10603/23054/... · Chapter 10 OTA-based Analog...
Transcript of Chapter 10shodhganga.inflibnet.ac.in/bitstream/10603/23054/... · Chapter 10 OTA-based Analog...
Chapter 10
OTA-based Analog Multiplier
1 O.J Introduction
In this chapter application of OTA as a multiplier is presented. Analog multiplier
plays un imponnnt role in analog signal processing system. In this chapter lir.;t n review
of different analog multiplier architectures, which have been proposed over the Inst
fillecn year:,, is given. Few low-power multiplier structures an~ simulated in Cadence
Virtuoso Design cnvirowneni to obtain their characteristics such as input range, linearity.
input noise and power consumption.
The new structure is proposed for the unnlog multiplier using cross-coupled OT A
that has low power dissipation while at the same time keeping good linearity, low supply
voltage and low noise. The quantitative analysis on linearity, power consumption and
noise for proposed multiplier is also presented, which is verified by Spectre Simulatot
from Cadence tools [69-71 ). Simulation results showed that the proposed multiplier is
showing good performance.
10.2 Analog Multiplier
Real time analog multiplication of two signals is one of the most imporlam
operations in analog signal processing. /\. multiplier is an active network. lhe output of
which is proportional to the product of two input signals. A general rcprcscnlation of
multiplier is
Z= K. X.Y ( 10.1)
136
where X and Y are the two input signals with K being multiplier constant with
suitable dimensions. All signals, i.e. X, Y and Z are measured with respect to ground.
The signals can be either voltages or currents.
The multiplier is used not only as a computational building block but also as a
programming element in systems such us filte~. neural networks und as mixer and
modulators in communication systems. Verities of multipliers have been designed for
different objectives and some of them are driven by the early work of Gilbert (71-73]. A
general idea behind these designs is to use electronic devices to process input signals in
analog domain, followed by cancellation or minimization of error caused by non-linearity
of devices. Tht: CMOS multiplier implementation is sti ll a challenging subject especially
for low-voltage and low power coni;umption (71 ).
10.2.1 Basic Idea of Multiplier
The basic idea of multiplier implementation is illustrated in Fig.10.1. Two signals
v,(t) nnd vz(t) urc upplled to nonlinear device, which can be characterized by a high order
polynomial function. This polynomials function generates second order, third order and
many others tenns beside the desired v1(t).v2(t). Then it is required to cancel the
undesired components. This is accomplished by a cancellation circuit configuration. The
differential ci rcuit structure is widely used for nonlinearity cancellation [71) .
..------- "\
Nonlinur Device
i.e.,
;0 = av, +bv,2
+cv,>+/\
Nonlinearity i., = /cv1 (t )v1 (t)
cancellation scheme
Figure 10.1 Basic idea of multiplier
137
For a multiplier circuit with two inputs there are four combinations of two
diff1::rcntial signal::;, i.e., (x, y), (-x, y), (X, -y), (-x, -y). Two example topologies for
multiplier implementalion are shown in Fig.10.2 [71].
x+y I 2 l x + xy+ y
x 2 2 ,
·x+y x - xy+y
I l x +2xy+ y
l 2 l x - xyt y
(u) (b)
Figurel0.2 Example topologies to implement analog multiplier structures
The topologies, shown in Fig. I 0.2, achieve multiplication and simultaneously
cancel out all the higher order and common-mode components (X and Y) based on the
relation (10.2) for Fig. 10.2(a) and relation (10.3) for Fig. 10.2(b) (x and y represent
small signals).
[(X+x)(Y+y) + (X-x)(Y-y)]- [(X-x)(Y+y) + (X+x)(Y-y)] = 4x.y (I 0.2)
[ {(X+x) + (Y+y)}2 + {(X-x) + (Y-y)} 2] - [ {(X-x) + (Y+y)} 2 + {(X+x) + (Y-y)}
2]
= 8x.y (10.3)
138
10.3 CMOS Multiplier
As th~ digital technology dominates in modem electronics, 3nalog 1,;ircuits are
required to use the same standard CMOS process for low-cost fabrication. Due to the
popularity of advanced CMOS technology, with 1,;mphosis on low power consumption,
MOS transistors are a natural choice for the devices, while differential circuit is widely
used for non-linearity cancellation [73J. For CMOS analog multiplier des ign, the simple
MOS transistor model is expressed as relation (I 0.4) and ( I 0.5).
Id= K [Vos- Vr- Vos/2]Vos for Yvs >Yr, Vos < Yes- Yr ( 10.4)
for VGs >Yr, Vos> Yes- VT (I 0.5)
For MOS in its linear nnd saturation region, respectively, K ""µo. Cox (W/L) and
VT are the conventional for the transconductance par3mctcr and threshold voltngc of the
MOS trans istor, respectively. Fig. 10.3 shows the application methods for two signals (x
and y) in a MOSFET. Jn Fig. 10.3 the small circle on the transistor terminal represents a
fixed biasing voltage, x and y are time-variable voltage signals, disregarding the bins [711.
The first three methods are used for MOSFET's operating in their linear region and the
rest are for transistors operating in saturation. The signal injection methods (b), (d) and
(g) in Fig. 10.3 require a voltage summing circuit. This voltage summation can be
implemc:111c:d in different ways, ulthough the perfonnancc of the swruncr directly affects the
perfonnance of multiplier [71].
139
±y ±.x±y ±r~ ±x±y
:!:x-l~y ~~;· ~;. ±y-f
(a) (b) (c) (d)
sli. f ±x-i ~id :tx4 ±x±y-1 ±y
(e) (f) (g)
Figure 10.3 Voltage signals injection methods
10.3.1 Multiplier Characteris tics
Accuracy: Accuracy is specified as the deviation of the actual output from char of ideal,
for any combination of X and Y input within the specified operating range of the
multiplier r73J.
Linearity: The accuracy of multiplier is usually expressed in term of its linearity. A
graph of output voltage as function of one of the input voltage is obtained, with the other
input voltage kept at some constant value. The input voltage that is kept constant is
usually set to its maximum or full-range value. Linearity is most commonly defined as
the maximum percentage deviation from ''best straight line" data at the output,
corresponding to equal magnitude input at the X and Y terminals.
Linearity error is plotted dilTerent for X and Y input, when these plots are
combined, they present an error surface. Hence linearity error can also be defined as the
maximum absolute deviation of the error surface. Some time linearity error is also
140
defined as a pt:rccntage of full-scale output, as the maximum devintion from linearity
occun-cd at lhc extreme;: t:nd of multiplier dynamic range as shown in relntion (10.6).
Linearity Error "' (6 Vz I Vz tr.ti ... 1,>I (10.6)
where 6 Vz - actual value;: uf oucput - expected value of output and Vz is output voltage
of multiplier. Linearity error cannot be reduced and places a lower limit on multiplier
accuracy.
Quadrant: This indicate~ whether the device will accept bipolar signal. If it accepts only
positive signals, it is a First quadrant: if it accepts only one bipolar signal, it is Two
quadrants; if it accepts two bipolar signals, it is a Fnur quadrant dc::vicc.
Scale Factor: Scale factor is defined to be the proportionality constant, relating the
output voltage and the product of the input voltages as given in relation (I 0. 7).
K=Z / XY ( 10.7)
ln equation (10. 7), K is found at particular value of X, Y and Z.
The measurement of multiplier performance can include input range, linearity,
power consumption, &equency range, and noise and so on. Since all these performance
measure are strongly application dependent, there is not an absolute standard comparison
metric. Also, it is not wicommon that some metrics need to be tru.dcd for other. for
instance, as the power consumption of multiplier is lo be optimized, its linearity gets
worse. This required reasonable tradeoff between the two. Herc the attempt is made to
compare three multipli~r structures according to different criteria such as input range,
linearity, noise and power consumption etc [73).
141
l 0.4 Common Multiplier Structures
This section includes comparative study of some common multiplier strucrur~s
proposed in f7 I]. Fig. I 0.4 shows 1hcsc: mulliplicrs structures.
Y+y-1 t-Y+y
X-x x+x X-x
(a) (b)
X+x
(c)
(d) (c)
Figure 10.4 Common multiplier Structures
142
These five multipliers havo been des igned without considering a specific
performance for rough comparisons [71]. The circuit of Fig.10.4 (b) and (c) have low
transconductance. The multiplier circuit of Fig. I 0.4 ( e) signifi cantly consumes higher
power than any other circuits. The output current of circuit Fig. I 0.4 (b) and Fig. 10.4(c)
have high sensitivity on device mismatch. From complexity of circuit topologies
conclusion is (71]
• the circuit Fig. I 0.4 (b) has low transconductance, is sensitive to mismatch, and
has poor linearity
• Lhe circuit Fig. l 0.4 (c) is sensitive to mismatch anel has low transconduclance
• tin~ circuit Fig. l 0.4 (e) con!;umcs high power and has poor linearity
The linearity of circuit Fig. I 0.4 (a) improves as the source follower use larger
W/L ratio. This effect is not clear in the case of circuit Fig.10.4 (<.I). For the !;ame input
range and output node voltage swing, circuit Fig. l 0.4 (a) requires lower power supply
than Fig.10.4 ( d). So multiplier structure of Fig. I 0.4 (a) seems to be most attractive
structure for low voltage and low power applications, also has good performmce metrics
as compared to other structures [71). In this thesis the two architectures (Fig.10.4 (a) and
fig. I 0.4 (b)) were simulated using Cadence's Custom lC Design Tools in 0.35um CMOS
technology with process parameters given in table 7.1 and their performance was
compared to with the multiplier, proposed in this thesis. These structures arc called as
structure I and structure II in this thesis.
143
t 0.4.1 Multiplier Structure I
Fig.10.5 shows multiplier structure I, which is the most recom1mmdcd multiplier
structun:, provided in L 71].
Figure 10.S Multiplier s tructure I
A folly differential configuration improves the linearity because a better non
linearity cancellation is achieved. The folly differtmtinl configuration using four MOS
transistor i.e., N l - N4 operating in linear region and upper four MOS transistor i.e., Ml
- M5 are operated in saturation region. For the cin.:uit shown in Fig. I 0.5, the differential
output current is given by equation (10.8) which gives the multiplication of two signals.
l ou• = 101 - 102 = lout - K [((Vy+ ZVx) 2
- (Vy · 2Vx) 2] ~lout= 4 K VxVy (10.8)
10.4.1.1 Input Range
The input range of a multiplier circuit is obtained from its bias conditions.
Constraint set ( I 0.9) gives the required bias conditions for the structure I.
144
VT < X :!: x
vi= Y ± Y - vT VT< y ± y
y ± y - Vr < V4
l 0.4.1.2 Linearity Analysis
< x ± x - VT
( 10.9)
!'ht: DC transfers characteristics of (lo1- Io2) versus x and y is shown in Fig. 10.6 (a)
and (b). A DC transfer characteristic shows that the structure in Fig. I 0.5 is four-quadrant
multiplier. The structun.:: is able to accept two bipolar signals as input.
,,.., ...
Su •· •••
6u ·· .......
···. H- 0~ ......... ~
-· .. ....... ···
4u ......... • •• •..••
~II •· ............ .......... '• ••• ., • •. • ,. •••• •••• ••••••• - ······· ,_. - •·
i .:.. ···········-·· .. ······- .... -.: ... :::::::~~~;/!=:··· .. (=:::::~::::·::: .. -~- .:: ...... .
.,., .....
.................. ......
·····-···········
~ ·· •..
· I 0<'.0·'"=2------0 I ----~O~------,O~l-)11")
·~ . ,__, 0 2
Figure 10.6 (a) DC trun~fcr churn<:tcrbth.::s l out versus y for Structure I
The linearity error versus y and x inputs is shown in Fig. 10. 7 (a) and (b)
respectively. The linearity error increased as the value of both x and y inputs increases. In
particular, when x= 0.12 and y=0.2V, the linearity error is measured to be 4.8 % and
when x = 0.2V and y = 0.12V, the linearity error is measured to be 0.89 %.
145
I OU f S u .
!
6u 1 .tu ;
.-,.. ~u f ~o[ lS ~
- - :?u t
~·= - ( t.:
4 u i . · Gu l r=u.:?
!
-811 i.
-!Ou !. ~.:_. -----· -0. ~
Figure 10.6 (b) DC tr:ansfer characteristics l 0 u1 v ersus x for structure I
Linearity Error
6 ---- ---- ----·- - - ---- -------- -------------- !
5 +--- -----------------------;! _,...--------------... ~ 4 +--- ----,--"'"----- -- - ---- --- ------.., ~ /,.---' ~ 3 +----"7"------------------; ·E • ~ 2 +------------------- ----l
:.:J
0 +---- --,--------.---------,-------; ODB 0 .12 0 .16
X• 0.2V y(v)
Figure 10.7 (a) Linearity Error versus y for structure I
1
0 .9 * 0 .6 ':::"' 0 .7
.E 0 .6 ~ 0 .5 ·.., 0 .4 ~ 0 .3
:.:J 0 .2 0 .1
0 o.c ~
Linearity Error
------· ___ .. --- ----
0 .08 0 .12 0 .16
x(v)
Figure 10.7 (b) Linearity Error versus x for structure I
146
The Total Hannonic Distortion (THD) is calculated when a constant DC voltage
is applied to x (or y) while a 100 KHz 0.2Vp-p sinusoidal wave is applied to y (or x) [73)
is shown in Fig.10.8 (a) and (b).
THO
8 7
ae .. 8 !5 ---t 8.< -----~ 8 3 --8 2 8.1
8
;9 o~ 0' 0 1 ~ 0 2
! IV i
Figure 10.8 (a) THD of signal y with x == 0.2 V for structure I
THO
3
2. ~
~ 2 -
~ 1 5
~ 1
0.5
~
o o~ 0 1 o ,e o: x (v;
Figure 10.8 (b) THD of output signal with y = 0.2V for structure I
Fig.10.8 (a) and (b) shows the multiplier has good linearity with respect to x input.
147
10.4.1.3 Power Consumption
for given constant power supply, the power consumption of multiplier can be
estimated by looking at the total supply voltage (Vdd) current, which is given by relation
(10.10).
(1 0.10)
I..,..,1 - (K,10/2)[ Y -y-V ut - Vr]2 + (K,..n/2)( Y-y- Y 112 - VrJ2 + (K MJl2)(Y+y- V a3 - Vr)2 +
(KM,12) [Y+y-Ya~ - Vr)2
where Val to V 114 are the voltage at the source terminal of transistors MI to M4,
respectively. S ince V 01 V 04 arc very small compured w ith the input signals and K M1 =
K .112 = Kw= K,..u, I 1o1a1 can be approximate as shown in relation (I 0.11).
( 10.11)
Relation ( I 0.11) indicates that tho power consumption has nothing to do with signal x
anJ DC b ins X for transisto rs N 1-N 4 .
The Fig. I 0.9 shows the total current with both x and y being a 100 kHz 0.2Vp-p
sinusoidal wave. The total power consumption of first multiplier structure is 34uA when
power supply is Vo.i = 1.5 V.
30n
.12u
Hll tlOn I OQ\I
Figure 10.9 Total current consumed by the circuit for structure I
148
10.4.1.4. Noise Analysis
A thermal noise current power density of a MOS transistor is conventionally
modeled as relation (I 0.12) for transistor op~rating in saturation.
(I 0. 12)
and ( I 0.13) for transistor operated in linear regions respectively [71 ].
(10.13)
The total output current noise current is given by relation ( 10.14)
(10.14)
(10. 15)
The noise performance of structure I was simulated. Fig. I 0.10 shows the
equivalent input noise within range I 0 Hz to I 00 MHz, which is 1 l 4.234n V /sqrt (Hz).
·-·-- ···--·-·-·-·-·-·. ·-·-·-·-·-·-····· ·---·--·----···-· •····-------·-.' ··" ·-· '·----.... 114 ~3311
114 H~n
111 :' Un
114 ~~!h11.,..o -~-,o-o ~--1 .. -· -~-,u-... ---1-ooK--1-M fr<Q (Hz)
··· .. , \
\ i '
i \ I
l I
i !
Figure 10.10 Equivalent input noise simulation result for structure I
149
10.4.1.5 Multiplication of Analog Sign9ls
Fig. I 0. 11 shows the multiplicalions of two sinuc:oidnl w:1voo with ~u~u1.ic:i I 00
KHz and 500 KHz., applied to the multiplier structure I (Fig. 10.5). Simulation results
confim1ed that the circuit carries out the multiplication of two signols.
1 10 . , ""'
~;-
Figure 10.1 I Multiplication of two sinusoidal waves using multiplier structure I
I0.4.2 Multiplier Structure II
The multiplier strucLUre, shown in Fig. 10.12, shows a low-power multiplier
reported recently (73]. The ba~ic idea in designing this low power multiplier is to fit most
transistors into linear region und PMOS devices LO operate in saturation region,
considering the focl that PMOS transistor needs less drain current with large overdrive
voltage compared with NMOS transistor. In linear region the overdrive voltage can be
biased to increase the input range.
The drain current can remain a proper value by decreasing Vos• keeping the
power dissipation at same level (73]. Fig. I 0 .12 shows a low power CMOS analog
150
multiplier structure, proposed by [73), which consist of four PMOS transistors (P1-P4)
opernting in Si:ltW-atiun region and eight NMOS transistors (Nl-N4 and Ml-M4)
operating in linear region.
Considering channel length modulation effect for MOS transistor, the drain
CUITent in Saturation region is given b y re lation ( I 0. I 6 ).
In = KJ2 (V cs - V r)2 ( l -1 A.Vos) (10.16)
where K = uCox (W/L) is the Transconductance parameter, Yr the threshold
voltage of device and A. is the channel length modulation effect for device.
\-01.J
VOi \'O~
..i Pl IJ>.j X+x Y+y
\'111.-----' .___ _ _.vv~ \ 'p3 _ _ __,
~---''J>-t
~D
1...--------------~•'----------,GND
Figure 10.12 Multiplier structure II
Assuming that all the transistors in fig.10.12 arc biased to operate in proper
region, the relation for diff~rential voltage can written as (10.17) which results in the
multiplication of two signals x and y.
V o1 - V 02 oc (K,v K M/ K,.) x*y (10.17)
151
10.4.2.1 lnput Range
The= required bias conditions, to obtain the input range, for multiplier structure n
can be written as relation ( I 0. 18) and (I 0.19).
for Pl - P4
forNI -N4
(10. 18)
(10.19)
The bias voltage of Ml - M4 is chosen to be V DD in order to keep V p as low as
possible, allowing Pl - P4 for larger input range.
l 0.4.2.2 Linearity Analysis
The DC transfer characteristics of (VO! - V02) versus x and y for multiplier
structure IJ wiLh X =- 0.5 1111d Y = 1.5 are ploned in Fig. I 0.13 (a) and (b). DC transfer
characteristic; shows that second multiplier structure is four-quadrant multiplier and the
multiplier is capable to accc=pl two bipolar signals as input.
\m ... ................. l111 ......... . ... .... ·· ...
~ .. ............ - 1111 p
-: 0
.....
p ~-Im
~ .-_ ....... ... . ... - .. ··
0 ::111 •• ...... -··
-411l ..... ...
...... ··
-o: .0 I
..• ·. !.1- •!::; :~.:·:~
0 .....
,,.·· ) -.o .. : ...... ·
. ..... ·· ······· -......
. ..... _ -- ........... ... ........
~·
.. ....
··· ... .... ..... 0 I 0:
Figure 10.13 (a) The DC transfer characteristics (V01-V02) versus x for multiplier structure II
152
4 111 ... · ··· .... _,.-· ... -..... . .. ..
...... .. .. .• ··... '(• -0 : ... ••. - ···· ......... ··... . .. ··· ......
8' Jn1
:..; 0
?" G ·t in
- !111 ••
..... ··· -4m
·O.:
..... --····
... ·
. ......... ...... ..· .. ......... - ... .... ::::::~_:)~~)·-·111~~=:}~'.:· :.: - ······-············-······
..... • .....
x•O 1 •· ..• -..... ... .....
• .. ·· ...
.o l 0 ~(I)
0 l o:
Figure 10.13 (b) The DC transfer characteristics (VOI-V02) versus y for multiplier structure Tl
The linearity error of second multiplier structure fur both .y and x inputs are
shown in Fig.10.14 (a) and (b). In particular, when x = 0.12 and y = 0.2V, the linearity
error is 1.62 %. And for y = 0.12 and x = 0.2 V, the linearity error is 1.1 %.
Linearity Error
1 2
---------- -- -~-
.//
/~ _,,
~ 'c:' 0.8
~ ~ 0.0 ·c:
"' ~ 0 .4 .:J
02
0 0 04 0.06 u 12 0.16
x• 0.2V Y(V)
Figure 10.14(a) Linearity error versus y for multiplier structure II
153
1 B
1 6 -- .- ~,
~ 14 / · .....,,__
~ 12 /
---. ~ 1 _ _,,/' ~OB ~ 0 6 = 0 4
02
0 0 .04 0 08 0 12 0 16
y= 0 2V x(V)
Figure I0.14(b) Linearity Error versus x for multiplier structure ll
7.~ T"'""---------------------, ~~4 +----------------------~ ------i.:-3 r-------------=- :C::::-------l
~ ~- +---------.--=--~-------'--------------1 - -'- .,,.,.,, g - 7• _,,.,,,
~ I - 'f-----~--,,7"""----------------~ -, +----..,::....-----------------~
•.is +------.----------------...!
..,~ '•'
Figure 10.15 (a) THD of output signal with x = 0.2 V for multiplier structure II
44) !> 4 ~
~ ;9~ o~
~
4 ;s! c 0 03 :J: 4 ~7 5 I-
Oi
......__ .....__
------- ..........,__ -- ---.._
n~~
o~ 4 ?.~ ! - .
~ .... : . "
Figure 10. IS(b) THD of output signal with y = 0.2 V for multiplier structure II
154
The Total Harmonic Distortion {THO) is calculated when a constant DC. voltage
is applied to x (or y) while a 100 KHz 0.2Vp-p sinusoidal wave is applied toy (or x) is
shown in Fig. I 0.15 (a) and (b). The structure hus good linearity with respect to x input.
10.4.2.3 Power Consumption
The total supply current for multiplier stnicturc II, i.e. I1o11 = lri + IP2 HrJ+IP4,
is given by relation ( 10.20).
I101a1,..,, KPl/2 (Vno-X-x-Vr)2 [ l+'A (YrJll-VPJ)] + Kn/2 (VDrrX+x-Vr)2 [ l+A. (VDl)'.Vn)]
~ KrJl2 (VnrrX-x-Vr)2 [ 11-f,(Vov-VpJ)] + Kpi2 (Voo-X-lx-Vr)2 r l+l..(Voo-VN)J
(10.20)
Since V Pl - V ,,, arc very small compared with input signals (if circuit is properly biased),
the relation wi II be approximated as (I 0.21 ).
1,.,.., oc 2Kr [(V vu- X-Vr)2 + x1] (10.21)
This indicates that the power consumption has nothing to do with signal y and DC
bias Y for transistor N 1- N4. The Fig. I 0.16 shows the totaJ supply current with both x
and y being a 100 kHz 0.2Vp-p sinusoidal wave. The circuits exhibit lower consumptions
as compared to multiplier structure I. The total power consurnplion of the circuit of
multiplier structure II is 28uA, which is less as compared to that of multiplier structure I.
Figure 10.16 Total current consumed by the circuit of multiplier structure II
155
l 0.4.2.4 Noise Analysis
The total output no ise for multiplier structure 11, shown in Fin. I 0.12. is given by
relation set (10.22).
(10.22)
This suggests that KM, K N and K p should be well defined lo improve the noise
performuncc. Also, the input noise depends on gm and gds that vary with the value of (X-
Y). Pig. 10.17 shows the equivalent input-referred noise integratt:d within I 0 Hz to I 00
MHz. The equivalent input noise of second multiplier structure is 867n V/sqrt (Hz).
on.
"""" -... ~ .. -·· ......... .
"""" e•~n
~
t 029n
oien ;, - ......
709n
79t>n
770<1
70lln 19 -
\ \
\
\ \,
•• frftq ( H1) '"" , ...
Figure 10.17 Equivalent input noise for multiplier structure II
10.4.2.5 Multiplication of Analog Signals
Fig. I 0.18 shows the multiplications of two sinusoidal signals, applied to the
multiplier circuit of structure II with frequencies 100 kHz and 500 KHz. The simulation
result confirms that the circuit carries out the multiplication of two signals.
156
~:~~~~ ~:~~ ~~!JfliDAMM1
e 0(1 2e.0u .. , ,...., $11.li'\I 80 e~ '~" ~ .... (.)
Figure 10.18 Multiplication of two sinusoidal signals by multiplier structure lJ
I 0.4.3 Proposed OTA Multiplier
The simplified schematic diugmm of proposed OTA multiplier, based on two
cross-coupled differential MOS pair, biased by current 21 and is shown in Fig.10.19.
Transistor Ml - M4 having same (W/L) ratio, Y+y is one input and X+x is second input
of Cross-Couple OTA multiplier, and bias current 21 can be obtained sing programmable
current source.
Vdd Proy Cun em Source
\"•
• - Y-y
.--~~~~--t~~1
M1
~r~ x+x ...
l I,
Figure 10.19 Proposed OTA Multiplier Structure
157
10.4.3.I Theoretical Analysis
OT A is a Voltage Controlled Current Source (VCCS) device and hence the output
of OTA multiplier structure shown in Fig. I 0. 19 b lout= 101 - 102. Also lo1 = IoM 1 + IoM 4
and 10 2 :: loM 2 + IoM 3. Therefore Io1and 102 can be written as relation (I 0.23) and (I 0.24).
101 ~ K (Vp VT1')2 + K ( Vo-Y·VTP)2 = K (VPT)2 + K (VoT- Y)2
Im= K (VQ- V rP)2 + K (Vp-Y-V rp)2 = K (Vor)2 -r K (VPT- Y )2
(10.23)
(10.24)
where Vp and VQ arc the gntc to source voltages of M l and M2 respc~tively, K - 0.5
uCox (W /L). The I"'n current is given as lout =- 101 + 102
10111= 2K (Y+y) (X+x) (10.25)
The output equation ( I 0.25) p1ovt:s that above OTA structure can be used as fou r-
quadrant multiplier.
10.4.3.2 Linearity Analysis
The DC transfer characteristics of lout versus X and Y arc shown in Fig. I 0.20 (a)
and (b). A DC transfer characteristic shows that multiplier has four-quadrant response .
. . i • . ... -·
·-"' -· .....
o:
Figure 10.20 (a) DC characteristics: 10 • 1 versus Y (proposed multiplier)
158
611
~II f'--..., ~:: f ~ -......... . :11 - · ...... ~
;: . ~ Ill I . :;. l°' I flt-ctl. i
:~:: lj . : . . ~ . -·4u \•OJ
'"'hi
.,II
-No·04--0T--.o·:~···-:oi--··6· -·-~t-·.,;r- ... 0.1-0'1
l • ·H
Figure 10.20 (b) DC characteristics: 10• 1 versus X {proposed multiplier)
The linearity error of proposed OT A multiplier with respect to inputs X and Y an:
shown in Fig. l 0.2 1 (a) and (b). In particular, when Y ::::: 0.2 and X = 0. 15, the linearity
error is measured to be 1.5 %, which is very Jess as compared to multiplier stn1ctw-cs I
und II.
Figure 10.21 (a) Linearity Error versus X ,proposed multiplier)
o~~------------------11 l 04 +---------~=--------
~ ./
! 03+-~~~~~~--~-~?~~~~~~ f 02 +-~---,,...::.~~~~~~~~-l 0 1 4------- ·- ------- --'
0.0~ 0 I 0.2 0.2!
YiV)
Figurel0.21 (b) Linearity Error versus Y (proposed multiplier)
159
The Total Harmonic Distortion (THD) when a constant DC voltage is applied to x
(or y) and a I 00 KHz 0.2Vp-p sinusoidal wave is applied to y (or x) is shown in
Fig. I 0.22 (a) and (b). The structure of proposed OTA multiplier has good linearity with
respect to Y input. The value ofTHD increase as the input X incn:msed.
0 10
0 14
() 12
~ 0.1 ~ 008 ... 0 00
0 .0q
0 02 0
-
0 1
THO
() :
x (V)
/ /
//
/
-------
Figure 10.22 (a) THD of signnl x (proposed multiplier)
THD
o. ~ ...-------------------, 0(5 t--.~====:=;:===-----------1 04 +---------------__;~----=-----------::..-----1 o~ +------------=-...-._::;-----;;,_ __ -;
~ 0.3 +-------------------; b' 0 l!i
~ 0 .2 +---------------- ---; 01~+------------------~ 01 +---------- ---------; o~ +------------------~
O +-----.----r----..----.----~
0.0~ 0.1 0 ~. 0'
YM
Figure 10.22 (b) THD of signal y (proposed multiplier)
160
10.4.3.3 Power Consumption
For constant power supply, the power consumption can be estimated by
calculating the total current. In case of OT A multiplier structure the current consumption
is almost the bias current provided by the current source, i.e. 42uA.
10.4.3.4 Simulation of Noise Performance
Fig. 10.24 shows the equivalent input-referred noise from 10 Hz to 100 MHz. The
equivalent input noise of proposed OTA multiplier structure is 11 J7 uV/sqrt (Hz), that is
slightly high as compared to previous two multiplier structures.
11.J/81.11· E.Ql.t"""~~ 11 .. UHh.•
11.J50u
11.J'4A1.1
it1..1JQ1u
~ $1t.J2ltJ >"
, , .)10\J
11.Jellu
11 ?99u
11.288u - .... . ....._......... • •• • , ._ ..... 1e 109 1t<
Noin Rnponst
- - -._
. . . . ···;flt< • ' , ....._ .. ,.00K• ' • ••••• ,..M ~-. '' "10+,, • - . "" 'l00u froq ( Hi )
Figure 10.24 Equivalent input noise (proposed multiplier)
10.4.3.5 Multiplication of Analog Signals
foig. l 0.25 shows the multiplications of two sinusoidal signals, one of frequency of
100 kHz and amplitude of 0.2Yp-p and another with frequency of 500 KHz and
amplitude of 0.2Vp-p. As a result it was confirmed that the proposed circuit carries out
the multiplication of two signals.
161
In proposed OT A multiplier y input had considered n.c: n quodrntic input so it
::1hould required some biasing voltage in order to keep transistor M3 and M4 in saturation
region, while performing multiplication of two sinusoidal waves. That's why a 0.2V de
and 100 KI I~. 0.2 Vp-p sine wuvc is applie<l us other input where 0.2V de is biasing
voltage.
s:~ ~WrlrlV±dtMffl·M~~rl~ , ~:: rinAAMA~A/\;
l.~&
' · ''~ 2 1.65
1.6<' .............._~~ ............... ~ ... • 1.7:> IV•
1.5!> 0 ~011 ~ 011 6011 8011 lOOl1
1111\C(~l
Figure 10.25 Multiplication of two sinusoidal signals (proposed multiplier)
10.5 Comparison of Three Multipliers
The comparative study of three multipliers wi th n:spccl lO <lilicrcnl pcrfonnuncc
metrics is given in Table l 0.1 w1d it shows that the proposed OT A multiplier structure
has good pcrfonnnncc in tcnn of input range, linearity and power consumption but more
input noise, as compared to multiplier structures 1 and 11. The total supply current can be
further reduced by some design considerations in order to achieve less power
162
consumption. The input noise can be further improved by optimizing the de value of y
and gm or transistors.
Table 10.1 Comparison of three multipliers (Vdd=3.3V)
- -Performance First Multiplier Second Multiplier Proposed OT A
Mctrh: structure structure Multipli\:r
Linearity Error of x 4.8% 1.62% 0.4& o/., - -
Linearity Error ofy 0.87 % 1.1 % 0.18 %
THD (%) ofx 2.7 4.3 0.04 -THD (%) ofy 8.6 7.3 0.388
Input Noise ll4.134n
(v/sqrt(f-12)) 867n I I .37u
Current 34uA 28uA 42uA
Consumption -~
The most important point is that OT A multiplier can be designed in two extreme
cases as for low-power (power minimization) or for low THO (THD minimization). Each
one will lead to a separate design.
163