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Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5...
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Transcript of Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5...
![Page 1: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/1.jpg)
Chapter 9 High Speed Clock Management
![Page 2: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/2.jpg)
Agenda
• Inside the DCM
• Inside the DFS
• Jitter
• Inside the V5 PLL
![Page 3: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/3.jpg)
The Digital Clock Manager
![Page 4: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/4.jpg)
Delay Lock Loop Block Diagram
Key ideas: All clocks look the same (more or less)Future clocks resemble current clocks
(ie, they are interchangeable)
![Page 5: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/5.jpg)
Simplified DLL Diagram
![Page 6: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/6.jpg)
Simplified Clock Tree Driving Four CLBs
CLKIN
F: Exact User Clock Frequencies : Unknown
d: Chip clock delay: Known
D: Amount of delay need to insert: Unknown
CLKIN
FBCLK (B)
F
d D
D“d”B
CLKIN
F: Exact User Clock Frequencies : Unknown
d: Chip clock delay: Known
D: Amount of delay need to insert: Unknown
CLKIN
FBCLK (B)
F
d D
DD“d”B
![Page 7: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/7.jpg)
Aligining FBCLK with CLKIN
FBCLK
CLKIN DLL
FBCLK (B)
GCLK
(B)FBCLK
CLKIN DLL
FBCLK (B)FBCLK (B)
GCLKGCLK
(B)
![Page 8: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/8.jpg)
Compensating for Setup Delays with DLL
Without DLL:
Tco = Td_C + Td_ff + Td_out
Tsu = (Td_D - Td_C) + Tsu_ff
Th = (Td_C - Td_D) + Th_ff
With DLL:
Tco = Td_ff + Td_out
Tsu = (Td_D - 0) + Tsu_ff
Th = (0 - Td_D) + Th_ff
DFF
Td_C
Td_out
GclkTd_ff
Td_DD
Without DLL:
Tco = Td_C + Td_ff + Td_out
Tsu = (Td_D - Td_C) + Tsu_ff
Th = (Td_C - Td_D) + Th_ff
With DLL:
Tco = Td_ff + Td_out
Tsu = (Td_D - 0) + Tsu_ff
Th = (0 - Td_D) + Th_ff
DFF
Td_C
Td_out
GclkTd_ff
Td_DD
Basic idea:We can setTd_C = 0
![Page 9: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/9.jpg)
Feedback from End Cell to Center Cell
FBCLK
GCLK DLL
A
GCLK
FBCLK (B)
Tco(A) = Tco(B) - Td (A B)
Tsu(A) = Tsu(B) + Td (A B)
Th(A) = Th(B) - Td (A B) (more neg)
Tco(B) = Td_ff + Td_out
Tsu(B) = (Td_D - 0) + Tsu_ff
Th(B) = (0 - Td_D) + Th_ff
B
A
FBCLK
GCLK DLL
AA
GCLK
FBCLK (B)
Tco(A) = Tco(B) - Td (A B)
Tsu(A) = Tsu(B) + Td (A B)
Th(A) = Th(B) - Td (A B) (more neg)
Tco(B) = Td_ff + Td_out
Tsu(B) = (Td_D - 0) + Tsu_ff
Th(B) = (0 - Td_D) + Th_ff
B
A
![Page 10: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/10.jpg)
Additional Skew Reduction
GCLK DLL
GCLK DLL
Place DLL outputCentrally, minimizeExtra delays
![Page 11: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/11.jpg)
Completing the Picture
GCLK DLL
GCLK DLL
Clock tree Geometry is Crucial.
Delivering clockUniformly to largeArea is the mainIdea.
Can deliver toHundreds of LUTFlip flops withVirtually identical“skew”
![Page 12: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/12.jpg)
DLL “Zoom In”
ck27
0
DLL power supply Pump / regulator
No-glitch counter
Huge coupling caps
For DLL power supply
Z1
ck0
ck90
ck18
0
clk2xclkdiv
Phase Detector2
Phase Detector1
FBCLK
LockgenCLOCK TREE
DELAY
clk0clk90clk180clk270
. . . ......
. .. . ...
clkgen
clk360
clkz
Very Complicated
State machine
p1
p2
Z2
RST
CLKIN
No-glitch counter
LOCKck
270
DLL power supply Pump / regulator
No-glitch counter
Huge coupling caps
For DLL power supply
Z1
ck0
ck90
ck18
0
clk2xclk2xclkdivclkdiv
Phase Detector2
Phase Detector1
FBCLK
LockgenCLOCK TREE
DELAY
CLOCK TREE
DELAY
clk0clk0clk90clk90clk180clk180clk270clk270
. . . ......
. .. . ...
clkgen
clk360
clkz
Very Complicated
State machine
p1
p2
Z2
RSTRST
CLKINCLKIN
No-glitch counter
LOCKLOCK
![Page 13: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/13.jpg)
Z2 Delay Exposed
Path 0: 1 unit-delay
Path 1: 3/4 unit-delay
Path 2: 1/2 unit-delay
path 3: 1/4 unit-delay
1 unit-delay
From very complicated State machine
CLK0
CLK180
CLK90
...clkz
CLK0
CLK90
CLK270
CLK180
...
...
CLK360
CLK270
Path 0: 1 unit-delay
Path 1: 3/4 unit-delay
Path 2: 1/2 unit-delay
path 3: 1/4 unit-delay
1 unit-delay
From very complicated State machine
CLK0
CLK180
CLK90
...clkz
CLK0
CLK90
CLK270
CLK180
...
...
CLK360
CLK270
![Page 14: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/14.jpg)
Main Delay & Trim Detail
...Path 0: 1 unit-delay
Path 1: 3/4 unit-delay
Path 2: 1/2 unit-delay
path 3: 1/4 unit-delay
1 unit-delay
From very complicated State machine
clkz
INCLK
Trim unit
...Path 0: 1 unit-delay
Path 1: 3/4 unit-delay
Path 2: 1/2 unit-delay
path 3: 1/4 unit-delay
1 unit-delay
From very complicated State machine
clkz
INCLK
Trim unit
![Page 15: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/15.jpg)
Configuration & Lock Process
General idea:
Don’t assert “Locked”To outside world untilDone is asserted fromThe configurationState machine
Looks like instantaneousLocking as part powersup
![Page 16: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/16.jpg)
Clock Doubling
CLKIN
CLK90
CLK180
CLK270
CLK360
CLK2X
S1 R1 S2 R2
CLKIN
CLK90
CLK180
CLK270
CLK360
CLK2X
S1 R1 S2 R2
Capture a periodIdentify end pointsIdentify middle (50%)Identify 25%, 75%Reassemble pieces
![Page 17: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/17.jpg)
Board Deskewing
We seek the idealSituation with A,BAnd C all tracking.
However, differentEnvironments.
Takes two DCMsTo lock B to A, andC to A, but can Make outside trackInside the chip
![Page 18: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/18.jpg)
More on Board DeskewingForeward pathdelay
Note howLocked is usedTo enable/Disable theRight handdevice
Synchronization trick delivers four clocksWorth of reset to the DCM and stops
![Page 19: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/19.jpg)
System Synchronous Applications
The Classic, single clocked synchronous system. Looks good, but doesn’taccount for clock arriving skewed all over the place to the right hand block(s)
![Page 20: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/20.jpg)
Source Synchronous Applications
More common these days. The clock is recreated by the middle boxand forwarded to the boxes on the right. This is what DDR SDRAM does, making whichever device is blasting data, also provide the clockfor that data to the receivers. You may receive in one case, but transmitin another case, so often both boxes can transmit data and clocks. Depends on which one is Sourcing the Data.
![Page 21: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/21.jpg)
Compare System and Source Synchronous Timing
Most Source Synchronous devices have DLL units inside.Data centering can select appropriate setup time by phaseShifting the clock.
![Page 22: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/22.jpg)
Duty Cycle Correction
DLLs have ability to correct duty cycle to 50%. This meansdata clocking with the rising edge has same setup windowas data clocking with the falling edge.
![Page 23: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/23.jpg)
Digital Frequency Synthesizer Capabilities
Its nice to distribute slow, external clocks and be able to increasespeed within the device. Frequency synthesis allows this.
![Page 24: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/24.jpg)
Basic Internal DFS Structure
Variable Ring OscillatorOutput
Control
CLKFX
CLKIN
M
D
Up/Down Variable Ring OscillatorOutput
Control
CLKFX
CLKIN
M
D
Up/Down
Output Control manages Up/down signalTask: adjust variable ring oscillator so:
CLKFX = CLKIN M D
![Page 25: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/25.jpg)
Some Common DFS Applications
![Page 26: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/26.jpg)
Fixed Value Phase Shift
See XAPP 462: ISE software lets you place a phase shift constantInto the programmable phase shifter, to assign clock edges
![Page 27: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/27.jpg)
Dynamic Fine Phase Shift Control
Can also do it dynamically, on the fly.Status feedback gives indicator of where youAre in the phase shifting
![Page 28: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/28.jpg)
Dynamic Phase Shift Controls
![Page 29: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/29.jpg)
Spartan 3 DCM Restrictions
![Page 30: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/30.jpg)
Clock Jitter
Jitter comes from many sources: clock crystal drift noise VCC ripple SSO ground bounce temperature drift, gain change
![Page 31: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/31.jpg)
Cycle to Cycle Jitter
![Page 32: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/32.jpg)
Peak to Peak Period Jitter Distribution
Period jitter captured with digital sampling scope (typically)
![Page 33: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/33.jpg)
Period Jitter Spec. as % Unit Interval
Another point of view: consider the amount of time allocated for a dataBit on a line. Call it a Unit Interval. Identify the amount of peak to peakJitter as a percentage of that Unit Interval.
Jitter is a “performance thief”, you must assume it subtracts out of your setup time (usually). Leaves less time available to handle data properly
![Page 34: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/34.jpg)
Peak to Peak Jitter Calculation
Adding more devices is done by squaring the device jitter and addingunder the radical. Deviation gets divided by “n” as number increases
![Page 35: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/35.jpg)
Jitter for DCM Cascades
![Page 36: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/36.jpg)
Virtex 5 Clock Management Tile
V5 Clock tile doesn’tHave PMCDs, itHas PLLs, instead.
![Page 37: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/37.jpg)
V5 PLL –High Level
PFD = Phase & Frequency DetectorCP = Charge PumpLF = Low Frequency FilterVCO = Voltage Controlled OscillatorD = Divisor counterM = Multiplier counter
![Page 38: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/38.jpg)
V5 PLL – More Detail
![Page 39: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/39.jpg)
PLL/DCM Cascades(preferred)
![Page 40: Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.](https://reader031.fdocuments.net/reader031/viewer/2022031905/56649ce45503460f949b103e/html5/thumbnails/40.jpg)
Conclusions
• Clocking resources simplify design• DCMs cover standard user domains working with
the global clock networks• DFS adds in extra clock multiplication• Phase shifting allows “tweaking” clocks to better
center to data• PMCDs are quick/cheap ways to make more
clocks and track together• Jitter can be identified, managed and predicted• PLLs can extend the frequency range and reduce
overall jitter• Virtex 6 and Spartan 6 resemble Virtex 5 DCMs