Chapter 9 Asynchronous Sequential Logicgn.dronacharya.info/itDept/Downloads/Question... ·...
Transcript of Chapter 9 Asynchronous Sequential Logicgn.dronacharya.info/itDept/Downloads/Question... ·...
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Asynchronous Sequential Logic
UNIT-5
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Introduction
• Synchronous Sequential Circuits The change of internal state occurs in response to the
synchronized clock pulse.
• Asynchronous Sequential Circuits
The change of internal state occurs when there is a
change in the input variables.
Memory elements are clocked flip-flops.
Memory elements are unclocked flip-flops or time-
delay elements.
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Introduction
• Synchronous Sequential Circuits
Timing problems are eliminated by triggering all
flip-flops with pulse edge.
• Asynchronous Sequential Circuits
Care must be taken to ensure that
each new state is stable even though
a feedback path exists.
Higher speed , More economical
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Introduction
• Asynchronous Sequential Circuits
When an input
variable changes in
value, the y
secondary variables
do not change
instantaneously.
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Introduction
• Asynchronous Sequential Circuits
In steady-state
condition, the y's
and the Y's are
the same, but
during transition
they are not.
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Introduction
• fundamental mode
fundamental mode :Only one input variable can
change at any one time and the time between two
input changes must be longer than the time it
takes the circuit to reach a stable state.
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Analysis Procedure
Transition Table
Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2
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Analysis Procedure
Transition Table
Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2
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Analysis Procedure
Transition Table
For a state to be stable, the
value of Y must be the same as
that of y = y1y2
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Analysis Procedure
Transition Table
The Unstable states,
Y ≠ y
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Analysis Procedure
Transition Table
Consider the square for x = 0
and y = 00. It is stable.
x changes from 0 to 1.
The circuit changes the value of
Y to 01. The state is unstable.
The feedback causes a
change in y to 01. The circuit
reaches stable.
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Analysis Procedure
Transition Table
In general, if a change in the
input takes the circuit to an
unstable state, y will change until
it reaches a stable state.
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Analysis Procedure
Flow Table
Transition table whose states
are named by letter symbol
instead of binary values.
Flow Table
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Analysis Procedure
Flow Table It is called primitive flow table
because it has only one stable
state in each row.
It is a flow table with more than
one stable state in the same row.
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Analysis Procedure
Flow Table
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Analysis Procedure
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Analysis Procedure
Race Conditions
Two or more binary state variables
change value in response to a change
in an input variable
Noncritical Race:
State variables change from 00
to 11. The possible transition
could be
00 11
00 01 11
00 10 11
It is a noncritical race. The
final stable state that the
circuit reaches does not
depend on the order in
which the state variables
change.
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Analysis Procedure
Race Conditions
Critical Race:
State variables change from 00
to 11. The possible transition
could be
00 11
00 01 11
00 10
It is a critical race. The
final stable state depends
on the order in which the
state variables change.
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Analysis Procedure
Race Conditions
Cycle
It starts with y1 y2 =00,
then input changes from
0 to 1.
00 01 11
When a circuit goes through a
unique sequence of unstable states,
it is said to have a cycle.
The sequence is as follows,
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Analysis Procedure
Stability Consideration
Column 11 has no
stable state. With input
x1 x2 = 11, Y and y are
never the same.
This will cause instability.
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Circuits with Latches
SR Latch
The circuit diagram and truth table of the SR
latch are shown as follows,
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Circuits with Latches
SR Latch
The circuit diagram of the SR latch can be
redrawn as follows,
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Circuits with Latches
SR Latch
Y = [(S + y)' + R]'
= (S + y)R' = SR' + R'y
SR' + SR = S ( R' + R ) = S
SR = 0 SR' = S
Y = SR' + R'y = S + R'y when SR=0
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Circuits with Latches
Analysis Example
S1 = x1 y2
S2 = x1 x2
R1 = x'1 x'2
R2 = x'2 y1
S1 R1 = x1 y2 x'1 x'2 = 0
S2 R2 = x1 x2 x'2 y1 = 0
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Circuits with Latches
Analysis Example
Y1 = S1 + R'1y1 = x1y2 + (x1 + x2)y1
Y2 = S2 + R'2y2 = x1x2 + (x2 + y'1)y2
There is a critical race
condition
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Circuits with Latches
Latch Excitation Table
A table that lists the
required inputs S and R
for each of the possible
transitions from y to Y
The first two columns list
the four possible
transitions from y to Y.
The next two columns specify the required input
values that will result in the specified transition.
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Circuits with Latches
Implementation Example
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Circuits with Latches
Implementation Example
S = x1x'2 R = x'1
Circuit with
NOR latch
Circuit with
NAND latch
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Design Procedure
Design Example
Design a gated latch circuit with two inputs G (gate)
and D (data), and one output Q.
State
Inputs Output
comments D G Q
a b c d e f
0 1 1 1 0 0 1 0 1 0 0 0
0 1 0 0 1 1
D =Q because G = 1 D =Q because G = 1
After state a or d After state c
After state b or f After state e
Gated-Latch
Total States
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Design Procedure
Design Example
State
Inputs Output
D G Q
a b c d e f
0 1 1 1 0 0 1 0 1 0 0 0
0 1 0 0 1 1
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Design Procedure
Reduction of the Primitive Flow Table
Two of more rows in the primitive flow
table can be merged into one row if
there are non-conflicting states and
outputs in each of the columns.
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Design Procedure
Reduction of the Primitive Flow Table
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Design Procedure
Transition Table and Logic Diagram
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Design Procedure
Circuit With SR Latch
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Design Procedure
Assigning Output to Unstable States
1. Assign a 0 to an output variable associated with an
unstable state that is a transient state between two stable
states that have a 0 in the corresponding output variable.
2. Assign a 1 to an output variable associated with an
unstable state that is a transient state between two stable
states that have a 1 in the corresponding output variable.
3. Assign a don't-care condition to an output variable
associated with an unstable state that is a transient state
between two stable states that have different values in the
corresponding output variable.
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Reduction of State and Flow Tables
Equivalent States
Two states are equivalent if for each possible
input, they give exactly the same output and go to
the same next states or to equivalent next states.
The characteristic of equivalent states is that if
(a,b) imply (c,d) and (c,d) imply (a,b), then both
pairs of states are equivalent.
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Reduction of State and Flow Tables
Implication Table
Two states are equivalent if for each possible
input, they give exactly the same output and go to
the same next states or to equivalent next states.
The characteristic of equivalent states is that if
(a,b) imply (c,d) and (c,d) imply (a,b), then both
pairs of states are equivalent.
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Implication Table
X1X2 Sn
A
00 01 11 10
B C D E F G
H
D/0 D/0 F/0 A/0 C/1 D/0 E/1 F/0
C/1 D/0 E/1 A/0 D/0 B/0 A/0 F/0 C/1 F/0 E/1 A/0 D/0 D/0 A/0 F/0 G/0 G/0 A/0 A/0 B/1 D/0 E/1 A/0
S n+1/Zn
Example
A B C D E F G
B
C
D
E
F
G
H
Without
the last
BD
AF
DG
AF
AF
DF
AF
BC
AF
DF
BC
BD
BG
AF
DG
AF
BC
DF
Reduction of State and Flow Tables
Without
the first
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A B C D E F G
B
C
D
E
F
G
H
BD
AF
DG
AF
AF
DF
AF
BC
AF
DF
BC
BD
BG
AF
DG
AF
BC
DF
X1X2 Sn
A
00 01 11 10
B C D E F G
H
D/0 D/0 F/0 A/0 C/1 D/0 E/1 F/0
C/1 D/0 E/1 A/0 D/0 B/0 A/0 F/0 C/1 F/0 E/1 A/0 D/0 D/0 A/0 F/0 G/0 G/0 A/0 A/0 B/1 D/0 E/1 A/0
S n+1/Zn
example
Implied Pairs
Reduction of State and Flow Tables
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Reduction of State and Flow Tables
A B C D E F G
B
C
D
E
F
G
H
BD
AF
DG
AF
AF
DF
AF
BC
AF
DF
BC
BD
BG
AF
DG
AF
BC
DF
The equivalent states:[A,F]、[B,H]、[B,C]、[C,H]。
The largest group of
equivalent states
[A,F], [B,C,H],
[D], [E], [G]
S n+1/Zn
X1X2 Sn
A
00 01 11 10
B
D E
G
D/0 D/0 A/0 A/0 C/1 D/0 E/1 A/0
D/0 B/0 A/0 A/0 B/1 A/0 E/1 A/0
G/0 G/0 A/0 A/0
Denoted by A Denoted by B
Combined
into [B,C,H]
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Race-Free State Assignment
The primary objective in choosing a proper
binary state assignment is the prevention of
critical races.
Critical races can be avoided by making a binary
state assignment in such a way that only one
variable changes at any given time when a state
transition occurs in the flow table.
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Race-Free State Assignment
Three-Row Flow-Table Example
This assignment will cause a
critical race during the
transition from a to c.
00
01
11
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Race-Free State Assignment
Three-Row Flow-Table Example
The transition from a to c
must now go through d, thus
avoiding a critical race.
00
01
11
10
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Race-Free State Assignment
Multiple-Row Method
In the multiple-row assignment, each state in the
original flow table is replaced by two or more
combinations of state variables.
Note that a2 is
adjacent to d2, c1,
b2.
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Race-Free State Assignment
Multiple-Row Method
The original
flow table
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Hazards
Hazards are unwanted switching transients that
may appear at the output of a circuit because
different paths exhibit different propagation
delays.
Hazards occur in combinational circuits, where
they may cause a temporary false-output value.
When hazards occur in sequential circuits, it may
result in a transition to a wrong stable state.
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Hazards
F1
F2
Hazards in Combinational Circuits
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Hazards
Hazards in Combinational Circuits
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Hazards
Hazards in Combinational Circuits
The hazard exists
because the change of
input results in a
different product term
covering the two
minterms.
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Hazards
Hazards in Combinational Circuits
The remedy for
eliminating a hazard is to
enclose the two minterms
in question with another
product term that overlap
both grouping.
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Hazards
Hazards in Combinational Circuits
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Hazards
Implementation with SR Latches
Consider a NAND SR latch with the following
Boolean functions for S and R:
S = AB + CD
R = A'C
S = (AB + CD)' = (AB)' (CD)'
R = (A'C)'
Since this is a NAND latch,
we apply the complemented
values to the inputs:
Q = (Q'S)' = [Q' (AB)' (CD)' ]'
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Hazards
Implementation with SR Latches
Q = (Q'S)' = [Q' (AB)' (CD)' ]'
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Design Example
The Recommended Procedure
1. State the design specifications
2. Derive a primitive flow table
3. Reduce the flow table by merging the rows
4. Make a race-free binary state assignment
5. Obtain the transition table and output map
6. Obtain the logic diagram using SR latch
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Design Example
Design Specifications
It is necessary to design a negative-edge-
triggered flip-flop. The circuit has two inputs, T
(toggle) and C (clock), and one output, Q.
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Design Example
Primitive Flow Table
State
Inputs Output
Comments T C Q a b c d e f g h
1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1
0 1 1 0 0 0 1 1
Initial input is 0 After state a Initial input is 1 After state c After state d or f After state e or a After state b or h After state g or c
Specification of
Total States
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Design Example
Primitive Flow Table
Primitive Flow
Table
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Design Example
Merging the Flow Table
Implication
Table
The compatible pairs:
( a, f ) ( b, g ) ( b, h )
( c, h ) ( d, e ) ( d, f )
( e, f ) ( g, h )
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Design Example
Merging the Flow Table
The maximal compatible
set:
( a, f ) ( b, g, h ) ( c, h )
( d, e, f )
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Design Example
Merging the Flow Table Reduced
flow table
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Design Example
State Assignment and Transition Table
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Design Example
Logic Diagram
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Design Example
Logic Diagram