Chapter 8 Sequential Circuit Design:...
Transcript of Chapter 8 Sequential Circuit Design:...
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Chapter 8
Sequential Circuit Design:
Principle
ECOM 4311
Digital System Design using VHDL
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Outline
1. Overview on sequential circuits
2. Synchronous circuits
3. Danger of synthesizing asynchronous circuit
4. Inference of basic memory elements
5. Simple design examples
6. Timing analysis
7. Alternative one-segment coding style
8. Use of variable for sequential circuit
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Overview on sequential circuit
Combinational vs sequential circuit
• Sequential circuit: output is a function of
current input and state (memory)
Basic memory elements
• D latch
• D FF (Flip-Flop)
• RAM
Synchronous vs asynchronous circuit
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Overview on sequential circuit
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Overview on sequential circuit
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• Timing of a D FF:
D Flip Flop
Clock-to-q delay (Tcq): Delay required for sampled d value to show up on q
Setup time (Tsetup): time interval that d must be stable for before the rising edge
of clock
Hole time (Thold): time interval that d must be stable for after the rising edge.
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Synch vs asynch circuits
Globally synchronous circuit: all memory
elements (D FFs) controlled (synchronized) by
a common global clock signal
Globally asynchronous but locally synchronous
circuit (GALS): Used in cases in which the
components of the design are spread too far
apart to allow a single synchronous clock.
Globally asynchronous circuit
• Use D FF but not a global clock
• Use no clock signal
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2. Synchronous circuit
Basic Block diagram:
State registers (state_reg) represent the memory
elements
Next state logic represent the combinational circuit that
determines state_next
Output logic represent the combinational circuit that
generates the external output signal.
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• Operation o At the rising edge of the clock, state_next sampled
and stored into the register (and becomes the new value of state_reg
o The next-state logic determines the new value (new state_next) and the output logic generates the output
o At the rising edge of the clock, the new value of state_next sampled and stored into the register
• Note that the clock period needs to be large enough to
accommodate the propagation delay of the next-state logic, the clock-to-q delay and the setup time of the FFs
Synchronous circuit
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Advantages of synchronous design
A single global clock makes the task of
satisfying the timing constraints of a design
with of thousands of FFs manageable.
The synchronous model separates the
combinational components from the memory
elements, making it possible to treat the
combinational part by itself
Propagation delay anomalies such as
hazards can be dealt with easily by focusing
on the worst case timing behavior
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Types of synchronous circuits
Regular sequential circuit
• State representation, transitions and next-state logic
have a simple, regular pattern, as in an incrementor or
shift register.
Random sequential circuit (FSM)
• More complicated state and no special relationship
between st ates transitions and their binary
representations -- next-state logic is random
Combined sequential circuit (FSM with a Data
path, FSMD -- RTL)
• Combines regular sequential circuit and an FSM, with
FSM acting as control for the sequential circuit
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Danger of synthesizing asynchronous
circuit
Consider the D Latch described earlier
We can write VHDL code as follows to represent
it
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Danger of synthesizing asynchronous
circuit
•Here we see the
implementation is
combinational except for
that the output is looped
around as an input
•Unfortunately, there is a
serious timing problem with
this circuit
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Inference of basic memory elements
VHDL code should be clear so that the pre-
designed cells can be inferred
VHDL code
• D Latch
• Positive edge-triggered D FF
• Negative edge-triggered D FF
• D FF with asynchronous reset
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D Latch
• No else branch
• D latch will be
inferred
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Pos edge-triggered D FF
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Neg edge-triggered D FF
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D FF with async reset
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Register
•Multiple D FFs
with same clock
and reset
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5. Simple design examples
• Follow the block diagram
oRegister
oNext-state logic (combinational circuit)
oOutput logic (combinational circuit)
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D FF with sync enable
• Note that the en is controlled by clock
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D FF with sync enable Conceptual diagram
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T FF
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T FF
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Free-running shift right register
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Free-running shift right register
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Free-running shift right register
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Universal shift register
• 4 ops: parallel load, shift right, shift left, pause
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Universal shift register
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Universal shift register
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Arbitrary sequence counter
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Arbitrary sequence counter
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Free-running binary counter • Count in binary sequence
• With a max_pulse output: asserted when
counter is in “11…11” state
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Free-running binary counter
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• Wrapped around automatically
• Poor practice:
Free-running binary counter
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Featured Binary counter
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Featured Binary counter
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Featured Binary counter
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Decade (mod-10) counter
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Decade (mod-10) counter
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Programmable mod-m counter
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Programmable mod-m counter
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Programmable mod-m counter more efficient
implementation
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6. Timing analysis
Combinational circuit:
• characterized by propagation delay
Sequential circuit:
• Has to satisfy setup/hold time constraint
• Characterized by maximal clock rate
(e.g., 200 MHz counter, 2.4 GHz Pentium II)
• Setup time and clock-to-q delay of register and
the propagation delay of next-state logic are
embedded in clock rate
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• Setup time violation and maximal clock rate
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• E.g., shift register; let Tcq=1.0ns Tsetup=0.5ns
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• E.g., Binary counter; let Tcq=1.0ns Tsetup=0.5ns
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• Hold time violation
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Using Variables in Sequential
Circuit Descriptions
A variable can also be assigned under the
clk’event and clk = ’1’ condition, but
whether a FF is created or not depends on
how it is used
If a variable is assigned a value before it is
used, it will get a value on each invocation
of the process and therefore, there is not
need to remember its previous value