Chapter 8 MEMORY MANAGEMENT (1)...Memory Management Unit (MMU) through a register known as a...

MEMORY MANAGEMENT

(1)

Chapter 8

Dr. Soha S. Zaghloul

CSC227: Operating Systems

Fall 2016

Dr. Soha S. Zaghloul 2

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Memory Management

Instruction Cycle

Basic Hardware

Base and Limit Registers

Address Binding

Physical vs. Virtual Addresses

Dynamic Loading


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TBackground

A memory of width n bits, can accommodate 2n addresses.

These are numbered from 0 to 2n – 1.

.

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0

2n - 1

Word =n bits

Each address is occupied by a word.

Therefore, the width of the memory is one word.

The number of bits in the word depends on the

architecture (hardware).

Currently, a word is usually either 32 or 64 bits.

A number of words, depending on the architecture,

consists a block. For example, the block size may be

16 words or 32 words.

The memory consists of a number of blocks.

Therefore, the number of blocks in memory is equal

to:

2n

Number of blocks = -----------------

Block Size

A word may be either an instruction or data


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TInstruction Cycle

An instruction goes through a 4-stage cycle after being saved in memory till its

completion.

The four stages of an instruction cycle are:

Fetch

Decode

Execution

Store

The CPU reads the value of the address stored in the Program Counter (PC).

The CPU fetches the instruction at the corresponding address from memory.

This is performed by the Instruction-Fetch Unit (IU).

The Instruction then goes through the Instruction Decoder (ID).

In this stage, the instruction is decoded.

In addition, operands are fetched from the memory in this phase.

Then, the decoded instruction with its operands pass through the relevant

Functional Unit (FU).

Adders, subtractors, logical manipulators are altogether known as FUs.

This stage is performed for store commands only.

The instruction results are stored in memory.

The storage address is specified in the store command as an operand.


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TBasic Hardware

The CPU accesses the on-chip registers within one cycle of the CPU clock.

In order to avoid long stall times, a cache memory is provided between the CPU and

the main memory. In modern computers, caches are on-chip.

Protect the operating system from being accessed by user processes.

On the other hand, the CPU accesses the main memory in many clock cycles via the

memory bus. During this time, the CPU is stall.

Not only we are concerned with the relative speed of CPU accessing the physical

memory, but we should also ensure correct operation.

For proper system operation, we must do the following:

Protect user processes to access each other in a multi-user environment.

Providing such protection by software (through the OS) is time-expensive.

Therefore, it is provided by hardware to ensure enough speed.

Base Register and Limit Register are used for such purpose.


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TBase & Limit Registers (1)

In memory, each process is given one or more contiguous memory space.

A contiguous memory space is defined by a lower limit (lower address) and an upper

limit (highest address).

The Base Register: holds the smallest process’s legal physical memory address

Non-contiguous memory spaces will be discussed later.

Two registers are therefore provided:

The Limit Register: specifies the range up to the highest allowed memory address

The following figure illustrates the concept:

Addre

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Lowest Adrs= base

Highest Adrs= base+limit


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TBase & Limit Registers (2)

Protection is performed by comparing each address attempting to access the

memory.

If the address is outside this area, then a trap to the OS takes place, which treats

the attempt as a fatal error.

Each address sent by the CPU is compared against the values stored in “base” and

“base + limit”.

The following figure illustrates the concept:

The base & limit registers are loaded only by the OS in the kernel mode: this is a

privileged instruction (An instruction that is executed only in the kernel mode).

Only the OS has the authority to change the values of the base & limit registers.

The OS prevents user programs from updating the registers’ contents.


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TAddress Binding

There is a part in the main memory reserved for the OS. This cannot be used by user

programs.

The following facts are valid for a compiled program:

Each instruction of the machine-language code will have a physical address

(location) in memory

Variables – such as count, flag, turn – used in your program are known as symbolic

names.

Each symbolic name will have a physical address in the main memory.

The compiler uses relative addresses or virtual addresses. The first instruction is

given the address zero, the second instruction is given the address n+1 where n is

the memory width, and so on.

When the executable file is run, it is first loaded into memory. The first physical

address of the first instruction is not 0 as assigned by the compiler. However, the

OS assigns a base & limit registers to the process in memory.

Therefore, a kind of address binding is needed to relocate the virtual address

(generated by the compiler) to the physical address (generated by the OS).

A virtual address is also known as a logical address.


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TPhysical Address vs. Virtual Address

A virtual address is mapped to a physical address by a hardware device called the

Memory Management Unit (MMU) through a register known as a relocation register.

The value in the relocation register is the difference between the values of both

addresses for the running process.

Therefore, when the CPU is going to fetch a data/instruction, the value in the

relocation register is added to each virtual address to get the physical address.

The value stored in the relocation address is the same as that stored in the base

register.

The following figure illustrates the physical layout of the previously mentioned

hardware:

Note that the program user is not concerned about the value of the physical address.

Example:

The logical address space (as generated by

the compiler) is from 0 to max.

The physical address space (as assigned by

the OS) is from R to R+max.

The value of the relocation register is R.

The value of the base register is R.

The value of the limit register is max.


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TDynamic Loading – Problem Statement

In order to execute a process, the following entities should be loaded into memory:

On the other hand, the following notes should be highlighted:

The process to be executed

The data that the process needs to work on while execution

The total size of the process and its data will be limited to the memory capacity.

This is not practical nowadays with the invasion of multimedia files.

A running process actually executes one or a few instructions (if parallelized), and

the rest of the code instructions reside in the memory waiting for their turn for

execution.

An instruction is executed when the value of the Program Counter (PC) equals its

address in the memory (physical address).

Therefore, the memory is full with non-executing instructions that can be loaded

at a later point in time; thus allowing other processes to be executed.

A professional code is written using modules such as methods, libraries, etc…

Not all methods are running at the same time.


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TDynamic Loading – Solution

Dynamic Loading is therefore introduced to resolve the previously mentioned

problem.

A routine (method, for example) is not loaded until it is called.

So, the main program (main method) is first loaded into memory and executed.

R1 sends an interrupt to the OS.

The aim of dynamic loading is to load the minimum possible number of instructions

that make the corresponding process run.

This is actually performed by making use of modular programming as follows:

R1 checks to see if R2 is previously loaded into memory.

If R2 already resides in the memory, then nothing happens to the

memory image (status) and execution resumes.

If R2 is not in the memory, then the following steps take place:

The OS calls the loader: a module in the OS responsible to locate the

routine R2 on offline storage (ex. Hard disk), and loads the routine R2

into the main memory.

The program’s address tables are also updated to reflect this change

accordingly.

Control is passed to the loaded routine R2, so that it starts executing its

instructions.

When a routine R1 calls another routine R2, the following steps take place:


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TDynamic Loading – Notes

According to dynamic loading, processes are equivalent to routines.

A routine is loaded only when the program logic needs it; ie. When it is called in the

code.

This is specially useful when large amounts of code are needed to handle

infrequently occurring cases, such as error handling routines for example.

Dynamic loading does not require special hardware.

Moreover, it does not require special support from the OS.

However, it is the responsibility of the users to design their program in a modular

way to take advantage of this technique.

Note that dynamic loading is applied to the OS software itself: we have a very large

number of interrupt handlers; however, these are loaded and executed only when

needed. The need to an interrupt handler is expressed by a sent interrupt.


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Swapping

Swapping is the technique of bringing a process into memory, running it for a while,

then putting it back on the disk.

In fact, memory allocation changes as processes come into memory and leave it:

(a)-(c): Processes A, B & C are created and swapped in from disk to memory.

(d): Process A is swapped out from memory to disk.

(e): Process D is swapped in from disk to memory.

(f): Process B terminates execution and deallocates the memory.

(g): Process A returns back (swapped in) in a different location in memory.

Refreshment


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Medium-term Scheduler (2)

Consider the following figure:

(1) The long-term scheduler selects P1 to be added to the ready queue.

(2) The short-term scheduler selects P1 to be dispatched.

(3) The medium-term scheduler selects P1 to swap out (from memory to disk).

(4) Later on, the medium-term scheduler selects P1 to swap in (from disk to

memory).

Obviously, swapped out processes wait in a dedicated queue (swap queue) in order

to be re-assigned to the CPU by the medium-term scheduler.

Refreshment


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TSwapping (Revisited) – Backing Store

A process may be temporarily swapped out of memory to a backing store; and then

brought back into memory by the medium-term scheduler to continue execution.

Therefore, the total required memory space of all processes - active in memory plus

inactive in the back store – may exceed the physical memory capacity.

As a result, swapping increases the degree of multiprogramming.

A backing store is commonly an offline storage media, such as the hard disk.

A backing store should have the following properties:

Large enough to accommodate copies of all memory images for all user processes.

Fast enough to reduce the swapping overhead as much as possible.

Must provide direct access to these memory images.

The following figure illustrates the role of

the backing store in the swapping process:


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TSwapping – Notes

The following points about swapping should be taken into consideration:

The total amount of swapping time is directly proportional with the size of the

swapped-in process.

Processes may have dynamic memory requirements during their execution.

A process to be swapped-out should be in the Ready State

Therefore, it is important to know the exact memory requirements of the

process to be swapped-in. This will avoid any unnecessary swapping overhead.

For example, a process may allocate memory for dynamic structures such as

linked lists, queues, etc…

Such process issues system calls request_memory() and release_memory() to

inform the OS about its changing memory needs.

Assume a process P1 in the waiting queue of an I/O device (wait state). If we

swap out P1, and swap in P2, the I/O operation will use the memory space that

belongs now to P2.


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TSwapping – Overhead

The overhead resulting from swapping is fairly high.

Consider the following example:

A user process has a size of 100 Mbytes. The backing store is a hard disk with a

transfer rate of 50 Mbytes per second. What is the actual transfer time of the

process during swapping (swapping overhead)?

Solution:

Actual Transfer Time= 100 Mbytes / 50 Mbytes per second= 2 seconds = 2,000 msec.

Total Swapping Time (in & out) = 2,000 x 2 =4,000 msec.

Problem:

Process Size

Actual Transfer Time = -----------------------------

Disk Transfer Rate


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TA Global Image (1)

The Ready Queue contains the following processes:

The processes that are ready to run and reside in the main memory.

Processes whose memory images are on the backing store: ie. were previously

swapped out.

These are brought into memory by the long-term scheduler (job scheduler) from

the job pool.

Some of these processes may have run for a while and brought back to the Ready

Queue because of:

An interrupt (Run-Ready)

Completion of an I/O event (Run-Wait-Ready)

Resumed after a suspension (Run-Block–Ready)

These are brought into memory by the medium-term scheduler from the swap

queue.

Whenever, the CPU becomes idle, the CPU scheduler is invoked to select a process.

When a process is selected, its PCB is checked:

If the process is previously swapped out, then the medium-term scheduler is

invoked to swap it in.

Then, in all cases, the dispatcher is invoked.

If there is no enough space, then the medium-term scheduler is invoked to swap

out a selected process. Control is then returned to the loader, then to the

dispatcher to handle the newly selected process.


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TA Global Image (2)

When a routine is called, the OS checks if the required process is already in memory:

If the process exists, then the dispatcher is invoked, a context switch takes place,

and the dispatcher jumps to the address registered in the Program Counter.

If the process does not exist in memory, the loader is invoked.

The loader checks for the available free memory region:

If there is enough space, the required process is loaded and control is given to the

dispatcher to make a context switch, and jump to the address value as recorded

in the Program Counter.

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