Chapter 8: Main Memory - IISPL() … · · 2011-11-29Overlays for a Two-Pass Assembler ... » PC...

Hanbat National Univ. Computer Eng. Dept. Y.J.Kim © 2010 Operating System Concepts – 8th Edition,

Chapter 8: Main Memory

8.2 / 62 Hanbat National Univ. Computer Eng. Dept. Y.J.Kim © 2011 Operating System Concepts – 8th Edition

Chapter 8: Memory Management Strategies

Background

Address binding : Compile time, Load time, Execution time

논리주소,물리주소. MMU: relocation registers : base, limit

Dynamic Loading, Dynamic Linking, Overlays, Swapping

Contiguous Memory Allocation

Memory mapping and protection : MMU

Single partition,

multiple partition:고정크기,가변크기:first,Best,Worst fit

Fragmentation : 외부,내부단편, compaction

Paging

기본개념,

Logical address : page number(p) and page offset(d)

Page table 구현 : register, memory, Associative memory(TLBs, cache), memory

protection(v,i)

Shared code pages & private code and data pages

Advantages: Easy to allocate, page out, protect, and share pages, No external Framgment.

Disadvantages : internal fragment, memory reference overhead, Too many memory might

be required for page table.

Structured page tables : Hierarchical paging, Hashed page table, inverted page Tables,


Segmentation

개념,

Example: The Intel Pentium


Objectives

To provide a detailed description of various ways of

organizing memory hardware

(메모리하드웨어를 조직하는 방법의 상세기술)

To discuss various memory-management techniques,

including paging and segmentation

(페이징과 세그멘팅을 포함한 메모리 관리기법)

To provide a detailed description of the Intel Pentium, which

supports both pure segmentation and segmentation with

paging

(인텔 펜티엄의예)


1.Background

Program must be brought (from disk) into memory and placed

within a process for it to be run

Main memory and registers are only storage CPU can access

directly

Register access in one CPU clock (or less)

Main memory can take many cycles

Cache sits between main memory and CPU registers

Protection of memory required to ensure correct operation


He coded (defined)

I use (reference)

Separate Compile


Binding


1.1기본하드웨어

한쌍의 기준(base) 과 한계(limit) 레지스터로 주소공간을 정의한다.

Monitor mode 에서 OS는 monitor 와 사용자 메모리 전체에 무제한 접근권한 가짐

기준 (base)과 한계 (limit) 레지스터 적재 명령은 특권 명령임


1.2주소의 할당(address Binding)

주소의 할당(Address Binding)

한 주소 공간에서 다른 주소공간으로의 사상(mapping)

주소 바인딩 시점

① Compile time : 시작 주소 미리 아는 경우

compile후 absolute code 생성, 시작주소 바뀌면 recompile

(예) MS-DOS, COM programming

② Load time : 시작 주소 모를 경우

compile 후 relocatable code 생성(binder가 주소 바인딩),

시작주소 바뀌면 reload만

Load tkl absolute 주소 생성

③ Execution time : 한 프로세스가 수행도중 다른 memory

segment로 이동하는 경우

동적 재배치(dynamic relocation)

H/W지원 필요 : relocation register 가진 MMU(그림 8.4)

X 14(bytes offset)

74014(R+14)


그림 8.3 사용자프로그램의 단계별 처리과정

main()

printf()

a.out

Relocatable absolute absolute


1.3 논리적 주소공간과 물리적 주소공간(Logical vs. Physical Address Space)

논리주소 ---MMU H/W- 물리주소

논리주소(logical address) :

program generated. Virtual address

generated by the CPU; also referred to as virtual address.

물리주소(physical address) :

memory address register에 적재되는 주소

Memory mapping H/W = MMU(Memory Management Unit)

Hardware device that maps virtual to physical address

Relocation register 이용

생성된 모든 주소 + relocation register value 물리주소

R : base value in relocation register : 재배치레지스터

logical address : 0 ~ max

physical address : R + 0 ~ R + max

Ms-DOS 운영체제 (intel 80x86): 4개의 재배치 레지스터사용


Dynamic relocation using a relocation register


Some Terminologies

Dynamic Loading

Dynamic Linking

Overlays

Swapping


동적적재(Dynamic Loding)

Routine is not loaded until it is called

Better memory-space utilization

Useful when large amounts of code are needed to handle infrequently

occurring cases.

No special support from the operating system is required

implemented through program design.

Without Dynamic Linking – must be loaded to same place

(next page)

Loading – occupy memory space


동적연결(dynamic linking)

At every load – that same address space is not occupied?

Must run in any address space…

Linking postponed until execution time.

Small piece of code, stub, used to locate the appropriate memory-resident

library routine. (eg: printf(). main() is already loaded)

Stub replaces itself with the address of the routine, and executes the

routine.

Operating system needed to check if routine is in processes’ memory

address.

Linking – Symbolic address vs. Physical address


Overlays

Keep in memory only those part when actually needed.

Useful when process is larger than memory.

Coded by user – ―Manual Overlay‖.

Overlays for a Two-Pass Assembler


Swapping

CPU scheduler : 순환 할당 스케줄링 : swap-out/swap-in

우선 순위 스케줄링 : roll-out/roll-in (우선순위에 따라)

CPU scheduler dispatcher :프로세스선택, 필요하면 swap out and swap in

swap-back 위치(메모리)

같은 위치 : compile time 또는 load time binding

다른 위치 : execution time binding

processes 위치

실행 중(ready queue) 시 Memory에

아니면 backing store에

Context switch 시: swap-out & awap-in

swap time (대부분이 전송시간)

» swap context-switch time =

(transfer time + latency time) x 2 = ?

» 회전지연시간(latency time) = 8ms

» 프로세스 크기(process size) = 10M

» 전송율(transfer rate) = 40MB/sec

» 전송시간(transfer time) = (10/40*1000+8)*2=516ms

» no head seek 가정

※ RR 1-time quantum > 516ms

modified swapping

» Unix : system load가 클 때 OS가 swapping(멀티프로그래밍 정도를 낮춤)

» PC Windows 3.1: user가 swap-in 선택, swap time 결정

» PC Windows/NT : OS가 full swapping


8.3 연속메모리할당(Contiguous Allocation)

Main memory usually into two partitions:

Resident operating system, usually held in low memory with

interrupt vector

User processes then held in high memory

Relocation registers used to protect user processes from each

other, and from changing operating-system code and data

Base register contains value of smallest physical address

Limit register contains range of logical addresses – each

logical address must be less than the limit register

MMU maps logical address dynamically



3.1 메모리 사상과 보호(memory mapping and protection)

Memory mapping

MMU가 사상 : 동적으로 코드의 논리주소에 재배치 레지스터의 값을 더하여

물리적 주소의 코드를 만들어 메모리에 적재한다.

Memory protection

CPU scheduler가 프로세스를 교체할때 dispatcher가 context switch안에 limit

register과 relocation address를 저장 및 적재하고

CPU가 생성하는 모든 주소가 limit register과 relocation address를 점검하므로

다른 프로그램의 접근을 막는다.

Hardware Support for Relocation and Limit Registers



3.2 메모리 할당(memory allocation)

단일 분할 할당(Single-Partition Allocation)

배치주소 고정 :

relocation register + limit register → 가변 OS size가능

실행 시간에 필요한 device driver만 load : transient OS code

다중 분할 할당(Multiple-Partition Allocation)

고정 크기 분할

여러 개의 고정크기 분할

다중 프로그래밍 정도(degree of multiprogramming)를 제한

(예) IBM OS/360 MFT2(Multiprogramming with a Fixed number of Tasks)

가변 크기 분할

hole(사용가능 메모리 블럭)에서 필요한 만큼 할당

MVT(Multiprogramming with a Variable number of Tasks)

주로 일괄처리 환경

OS지원 : Operating system maintains information about: a) allocated partitions b) free

partitions (hole)

• H/W지원 : 기준/한계 레지스터 → dynamic storage allocation



OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size

Produces the smallest leftover hole

Worst-fit: Allocate the largest hole; must also search entire list

Produces the largest leftover hole

기억장치 할당 예 (c)에서 100k, 100k, 200k, 160k 할당

How to satisfy a request of size n from a list of free holes

First-fit and best-fit better than worst-fit in terms of speed and storage utilization



An example of memory allocation



3.3 Fragmentation

외부 단편 (External Fragmentation )

프로세스의 메모리 적재가 반복작은 메모리 조각(사용이 불가능한)

50-pecent-rule : first-fit 할당 방식의 경우 통계적으로 N 할당 블록에 대해 0.5N

블록의 영역이 단편화 즉 1/3이 메모리는 사용불가

Compaction이 필요

내부단편(Internal Fragmentation)

partition 내부에 생긴 단편이 사용되지 않음

Compaction

사용가능 메모리를 한곳으로 모음

dynamic relocation인 경우에만 가능 : 각 program마다 base

register이용

Compaction + Swapping : roll-back될 때 dynamic relocation으로

compaction(적절한위치로 roll-back됨으로써)



compaction


8.4 Paging

Address

논리주소(logical address)

address generated by the CPU

also referred to as ―virtual address”.

물리주소(physical address)

address seen by the memory unit.

MMU (Memory-Management Unit)

is a Hardware device that maps virtual address to physical address

In MMU scheme

the value in the relocation register is added to every address generated by a

user process at the time it is sent to memory (from CPU).

The user program

deals with logical addresses

never sees the real physical addresses.


8.4 Paging

Paging

is a scheme that permits address space to be noncontiguous

Basic Method

Divide physical memory into fixed-sized blocks called frames (size is power of 2,

between 512 bytes and 8192 bytes).

Divide logical memory into blocks of same size called pages.

Keep track of all free frames.

Set up a page table to translate logical to physical addresses.

Internal fragmentation.

Address generated by CPU is divided into:

Page number (p)

used as an index into a page table which contains base address of each page in

physical memory.

Page offset (d)

combined with base address to define the physical memory address that is sent

to the memory unit.


8.4 Paging(~)

Fig. 8.7 Address Translation Archetecture(Paging Hardware

Logical address register (page number, page offset) Physical address register (frame base, page offset) frame base = tpage table[page number]


8.4 Paging(~)

Paging Model of Logical and Physical Memory

An Paging example of 32 byte memory and 4 byte pages

physical memory size = 32 byte=25

Frame size=page size= 4-byte =22 P.A F #

0 1 2 3 4 5 6 7

Logical address [00,0011] 3:(0,2) Physical address [0101,0011] (5,3):23

Logical address 3:(0,3)

(5,3):23 physical address


논리주소 ------ 물리주소 (address-translation H/W)

OS가 올바른 물리주소 생성 지원

각 프로세스 마다 page table유지 => context-switch time 증가

frame 할당 상황 담은 frame table 유지 : 사용가능 frame list

사용자 프로세스가 자신의 주소공간에서 동작하는지 파악

페이징은 동적 재배치(dynamic relocation)의 한 형태


8.4 Paging(~)

페이징 주소변환 하드웨어(Address Translation Hardware)


8.4 Paging(~)

Before allocation After allocation

가용프레임(Free Frames)


8.4.2 하드웨어 지원

(Implementation of Page Table

Page Table의 기본 구조(Structure of the Page Table)

Register로 구현

빠르다. page table 크기 작을 때 가능

DEC PDP-11 : 16bits address, page size 8K -> 8 page

registers

memory에 구현

PTBR(Page-Table Base Register)와

PTLR(Page-Table Base Register)로 접근

느리다(memory에 2회 접근해야 : One for the page table

and one for the data/instruction.

fast-lookup hardware cache에 구현

associative register, Translation Look-aside Buffers(TLBs)

address-space identifiers (ASIDs) for process to provide

address-space protection; key & value)로 보완 register

구현보다 10%의 느린 속도로


8.4.2 하드웨어 지원 (~)

Associative Memory

Associative memory(TLB) – parallel search

Address translation (p, d)

If p is in associative register, get frame # out

Otherwise get frame # from page table in memory

Page # Frame #


8.4.2 하드웨어 지원 (~)

Paging Hardware With TLB


8.4.2 하드웨어 지원 (~)

» 유효 접근 시간(effective access time) • (page를 cache에서 찾을) hit-ratio 80% : 16 registers

» i) cache에 있으면 • 20ns(cache access) + 100ns(memory access) -> 120 ns

» ii) cache에 없으면 • 20ns + 2 x 100ns ->220ns

» 유효 접근 시간 = 0.80 x 120 + 0.20 x 220 = 140ns(40% slow down) • hit radio 98%

» 유효 접근 시간 = 0.98 x 120 + 0.02 x 220 = 122ns(22% slow down) • TLB 10~512 개 이용하여 80~98% hit-ratio

» Motorola 68030 processor : 22 entry TLB » Intel 80486 PU : 32 entry TBL로 98% hit-ratio


8.4.3 Memory Protection

Memory Protection

Memory protection implemented by associating protection bit

with each frame

Valid-invalid bit attached to each entry in the page table:

―valid‖ indicates that the associated page is in the process’

logical address space, and is thus a legal page

―invalid‖ indicates that the page is not in the process’

logical address space


8.4.3 Memory Protection

Valid (v) or Invalid (i) Bit In A Page Table


Shared Pages

Shared code

One copy of read-only (reentrant) code shared among processes

(i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logical address space of all

processes.

Private code and data

Each process keeps a separate copy of the code and data.

The pages for the private code and data can appear anywhere in the logical

address space

ppt

code

P1

text

font

P2

text

font

P3 text

font

base address (private data)


shared code Pages and private code and data pages Example

Editor is shared

Editor consists of 3 pages -- ed1, ed2, ed3

ppt - code

ppt - code

ppt - code

ppt - private data

ppt - private data

ppt - private data

ppt - private data

ppt - private data

ppt - private data

ppt - code

ppt - code

ppt - code


Advantages of Paging

Easy to allocate physical memory

Physical memory is allocated from free list of frames

To allocate a frame, just remove it from its free list

No external fragmentation

Easy to ―page out‖ chunks of a program

All chunks are the same size (page size)

Use valid bit to detect reference to ―paged-out‖ pages

Pages sizes are usually chosen to be convenient multiple of disk block

sizes

Easy to protect pages from illegal accesses

Easy to share pages


Disadvantages of Paging

Can still have internal fragmentation

Process may not use memory in exact multiple of pages

Memory reference overhead

2 references per address lookup (page table, then memory)

Solution

get a hardware support (TLB)

Memory required to hold page tables can be large

Need one page table entry(PTE) per page in virtual address space

32-bit address space with 4KB pages = 220 PTEs(232 /212 =22 210)

4 bytes/PTE x 220 PTEs = 4x 220 = 4MB per page table

OS’s typically have separate page tables per process, memory required for 25

processes ?

(4MB/table x 1table/process x 25processes= 100MB for one system)

=>프로세스는 자기 공간의 page table만 참조할 수 있으면 된다.

=> page table의 분리가 필요하다.

Solution

page the page tables, multi-level page tables, hashed page tables, inverted

page tables, etc.


4.5 Structure of the Page Table

Hierarchical Paging

Hashed Page Tables

Inverted Page Tables


5.1 Hierarchical Page Tables

Break up the logical address space into multiple page tables

A simple technique is a two-level page table

다중 레벨 페이징(Multilevel Paging) 논리주소공간 : 232에서

단일 페이지 테이블

논리주소공간(전체) : 232 페이지 크기 : 4K(212)

페이지테이블 개수:100만(232/212= 220 )

페이지테이블크기 220 x 4 bytes(32bit) = 4M

총메모리 : 220 x 220 = 16MB

2 레벨 테이블 페이지

10bit page number + 10 bit page number

page table의 page number공간을 페이지크기 1K(210)으로 다시 paging

page table page number공간(전체): 220 페이지크기 : 1k(210 )

페이지테이블갯수:220/210= 210 (1K)

페이지테이블크기 : 210 x 4 bytes(32bit) = 4K

총메모리 : (210 +1) x 210 = 220 + 210 =1.1M


5.1 Hierarchical Page Tables(~)

Two-Level Page-Table Scheme



A logical address (on 32-bit machine with 1K(210) page size) is divided into:

a page number consisting of 22 bits : 232/210= 222

a page offset consisting of 10 bits

Since the page table is paged, the page number is further divided into:

a 12-bit page number

a 10-bit page offset

Thus, a logical address is as follows: where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table

Address-Translation Scheme of 2 level paging structure

Two-Level Paging Example



Three-level Paging Scheme for 62bit machine with 4K(212) page size

Two-level Paging Scheme for 62bit machine with 4K(212) page size


5.2 Hashed Page Tables

Common in address spaces > 32 bits

The virtual page number is hashed into a page table

This page table contains a chain of elements hashing to the

same location

Virtual page numbers are compared in this chain searching for a

match

If a match is found, the corresponding physical frame is

extracted


5.2 Hashed Page Tables(~)

Hashed Page Table


5.3 Inverted Page Table

Page table Only one entry for each real page of memory

Entry consists of

the virtual address of the page stored in that real memory

location,

with information about the process that owns that page

Decreases memory needed to store each page table, but

increases time needed to search the table when a page

reference occurs

Use hash table to limit the search to one

— or at most a few page-table entries

Used in the 64 bit UltraSparc, PowerPC


Inverted Page Table Architecture

Frame Number associative

search with (pid & p)

(3) Frame i has 7th page p of Pppt

a.out

(1) pid=“ppt” accesses its 7th page (p=7)

(2) Check all memory page frames “Any frame has 7th page of Pppt?


6. Segmentation

Memory-management scheme that supports user view of

memory.

A program is a collection of segments.

A segment is a logical unit such as:

main (),

function,

global variables,

stack,

symbol table, arrays


6. Segmentation(~)

Logical address space user space

Physical address (memory) space

User’s View of a Program logical view of segmentation


Segmentation Architecture

Logical address consists of a two tuple:

< segment-number, offset >,

Segment table

maps two dimensional physical addresses

each table entry has:

base – contains the starting physical address where the

segments reside in memory.

limit – specifies the length of the segment.

Segment-table base register (STBR)

points to the segment table’s location in memory.

Segment-table length register (STLR)

indicates number of segments used by a program;

segment number s is legal if s < STLR.


6. Segmentation(~)

Protection

With each entry in segment table associate:

validation bit = 0 illegal segment

read/write/execute privileges

Protection bits associated with segments; code sharing

occurs at segment level

Since segments vary in length, memory allocation is a

dynamic storage-allocation problem

A segmentation example is shown in the following diagram

Segmentation Architecture (Cont.)


6. Segmentation(~)

Segmentation Hardware


6. Segmentation(~)

Example of Segmentation


7. Pentium Segmentation

Supports both segmentation and segmentation with paging

CPU generates logical address

Given to segmentation unit

Which produces linear addresses

Linear address given to paging unit

Which generates physical address in main memory

Paging units form equivalent of MMU

Pentinum에서 논리주소가 물리주소로 변환되는 과정

Example: The Intel Pentium


7. Pentium Segmentation(~)

논리주소 : (select, offset)

select : 16 bit : <s(13),g(1),p(2)>

s: segment number, g:GDTor LDT, p: protection information

GDT(Global Descriptor Table), LDT(Local Descriptor Table) : 8byte로 구성,

segment의 기준위치과 길이 등의 정보

Segmentation unit


Pentium Paging

32bit linear address :

Pentium paging

Page size flag=1

0

210

0

210

0

212

0

212

P.s.f=0

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