Chapter 6 Experimental Verification in FPGA

After the design of the proposed DPWMs (two kinds of Hybrid DPWM in Chapter3) and

the proposed digital control algorithms (PID, RST in Chapter4 and SMC in Chapter5), the

next step is to implement the proposed digital control system on a test platform and verify its

performances. Currently due to the absence of IC fabrication in the time of this work, all

experimental tests are implemented on a Virtex-II FPGA board. The analog-to-digital

conversion is performed using a discrete A/D chip (AD9203), while the DPWM and control

algorithms are implemented in FPGA.

Since the digital controller is applied to the high-frequency SMPS, the computation speed

and the capacity to process complex algorithms are the main concerns for the digital processor

in practical implementation. Compared to traditional digital processors such as DSP and

MCU, FPGA has very fast computation speed and more flexibility in word length for

algorithm calculation. In addition the most outstanding feature of FPGA is the advantage of

parallel calculation, i.e. the Concurrent Statements in Hardware Description Language (HDL).

Thus many components of a circuit can simultaneously operate and concurrently drive distinct

signals to new values. This would dramatically reduce the computation time when the control

algorithm is complicated. The proposed advanced control algorithms are initially verified

through FPGA implementation, but all developments are ready to be used for a final digital IC

design. It should be noted that the current discrete FPGA-based approach versus the final

monolithic IC approach falls into the limitation in the practical switching frequency that can

be achieved, less than 10MHz compared to 100MHz at least.

In this chapter, the hardware implementation of the digitally controlled buck converter

system and experimental results will be illustrated. The operation condition and parameters of

the buck converter are the same as those used in the simulation shown in Section 4.2 and 5.3.

6.1 Brief Introduction to FPGA “A field programmable gate array (FPGA) is a general purpose integrated circuit that is

programmed by the designer rather than the device manufacturer”. FPGA can be viewed as

the newer and more advanced form of the earlier complex programmable logic devices

(CPLDs) which dates back to late 1980s. One of the fundamental advantage of FPGA over

100

DSP and other microprocessors is the freedom of operation in concurrence. Since different

parts of the FPGA can be configured to perform independent functions simultaneously, its

performance is just not tied to clock rate as in DSPs. Once hardware is designed at the system

level, logic cell or Register-Transfer-Level (RTL) is performed using hardware design

language (VHDL or Verilog), and the synthesis software generates the configuration program

file. This program file also called bitstream is stored in a PROM (or other non-volatile

memory) and upon application of power is written into the FPGA.

6.1.1 VHDL And Design Flow

Very-high-speed-integrated-circuits Hardware Description Language (VHDL) and Verilog

are the two languages, which allow designers to specify digital logic. VHDL allows a

designer to work at various levels of abstraction. The design abstraction hierarchy (shown in

Fig. 6-1) gives increasing abstraction in the direction of the arrow according to Gajski-Kuhn

Y chart [D6]. The Y chart has three levels of design description: Behavioral, Structural and

Physical. Each level has many levels of abstraction. The design process is represented by

step-wise refinement in all three levels from outer levels towards the centre. It is possible to

represent synthesis, design verification and analysis tools for VLSI design on the Y chart. The

digital design is generally done in the behavioral and structural domain and does not start at

physical level, which however outputs the final chip layout.

Behavioral

System

Register-TranferLogic

Structural

Physical / Geometry

Architectural

Algorithmic

Functional Block

Logic

Circuit

TransistorGates, Flip-Flops

ALUs, Registers

BUS, Subsystem

Processor , CPU

Polygons

Cell, Modules plans

Marcos, Floor plans

Clusters

Physical partitions , Chips

Algorithms

Tranfer-Function

© IEEE [Gajski1983]

Fig. 6-1 Gajski-kuhn Y chart

101

Design starts with the functional designing at the Behavioral level, and then goes to system

level, algorithmic and the RT level. After top-bottom partitioning, a bottom-up approach is

necessary to describe the design flows at the RT levels, then algorithmic and then system

level. Once the design is written in HDL or drawn through a schematic editor, it is

synthesized by logic synthesizer, which transforms it into a net-list. Synthesis is done using

commercial synthesis tools (XST for Xilinx). During synthesis the HDL code is translated (or

compiled) to the corresponding structural elements. At this point a functional simulation is

generally carried out, which checks the correctness of the HDL description. ModelSim Xilinx

Edition-II is used as the verification software in this case. The generated net-list contains

information of the various logic gates and their interconnections in the structural level.

Next step is the Design Implementation stage. Here implementation tools physically maps

the gates and logics from the net-list into the FPGA. At this time the design path reaches the

physical level. Implementation consists of three stages: Mapping, Place and Route. The

Mapping tool fits the net-list gates into groups that fit into the LUTs (Look-Up Table) inside

the CLBs (Configurable Logic Block). Then the Place and Route tool assigns these gates to

specific CLBs and interconnect them through making and breaking of the appropriate gate

arrays. The choice of interconnection and CLBs are guided by the need to meet various

optimization targets. Optimization may be done for area/real estate of the design or

speed/fastness of the design. At this stage various design verifications can be done through

timing simulations based on the post-layout timing net-list, which contains various gate-to-

gate, gate-to-pad and pad-to-pad timing information extracted after placing and routing teps.

Such timing simulation gives more accurate results than the previous functional simulation.

After implementation, the bitstream which contains the gate and placing information is

generated and downloaded to the physical FPGA chip. In the Gajski-kuhn Y chart the final

stage of abstraction is reached at this point and design is complete. The in-circuit verification

can be carried out at this point.

Fig. 6-2 shows the design flow chart of the digital controller in the Xilinx FPGA

implementation, where the overall design is built on a top-down approach. The design flow

includes four parts: Design entry, Synthesis, Implementation and Verification. The design is

performed using Xilinx ISE 9.2i tool and verified on Virtex-II Pro FPGA board.

102

Idea/Plan/

Budget

VHDL Code /Schematic /

IP CoreSyntax Check

FunctionalSimulation

Synthesize to Generate NetlistTranslate

Mapping

Place & Route

Design Entry

Synthesis

TimingSilmulation

Generate bitsream File

DownloadProgramming

Implementation

Verification

UserConstraints

Fig. 6-2 Steps in VHDL based Xilinx ISE/Modelsim design-flow

6.1.2 Xilinx Virtex-II Pro FPGA Family

The FPGA device used is XC2VP30 from Virtex-II Pro family FPGA of Xilinx [X3]. The

package used is ft896 with speed grade -7. Xilinx Synthesis Tool (ISE9.2i) and VHDL are

used as synthesis tool and programming language respectively. ModelSim Xilinx Edition-II

from Model Technologies is used as the simulation tool. A Xilinx University Program Virtex-

II Pro Development System Board (Xilinx XUP Virtex II Pro) is used. XC2VP30 has 3

million gates, 136 dedicated 18x18-bit multipliers, 8 DCMs, 644 user I/Os. In this work, we

employ an external 32MHz clock and use inside DCMs to obtain several clocks for different

blocks, such as A/D converter (16MHz), algorithm computation (128MHz), DPWM counter-

comparator (32MHz, 64MHz and 128MHz with their four phase-shift 0o, 90o, 180o and 270o,

etc.). Compared with DSP which is tied by the unique rigid clock, FPGA facilitates the

configuration of clock resource and offers more flexible clock choices for diverse function

blocks. The maximum speed of signal process inside Virtex-II Pro family FPGA can reach

400MHz, and interface I/Os signal transfer speed can reach as high as 200MHz. The number

of I/Os can be a determining factor for device or family of FPGA suitable for any particular

application. Table 6-1 summaries the resource of Virtex-II Pro Family Members, where the

shadow area is XC2VP30 in this case.

6.2 Test Platform Description To demonstrate the functionality of the proposed digitally-controlled prototype buck

converter, a test platform is built and set up as shown in Fig. 6-3. A corresponding system

block diagram is shown in Fig. 6-4. The test platform consists of three boards.

103

Table 6-1: Virtex-II Pro/Prox Family Members

Device RocketIO Transceiver

PowerPC Processor Logic cells

CLBs (1=4 Slices=max 128bits)

SlicesMax Distr RAM (kb)

18x18 BitMultiplier

Block SelectRAM+

Max Block RAM (kb)

18 kbBlocks

DCMMaximum

User I/O Pads

XC2VP2 4 0 3,168 1,408 44 12 216 4 204

XC2VP4 4 1 6,768 3,008 94 28 504 4 308

XC2VP7 8 1 11,088 4,928 154 44 792 4 396

XC2VP20 8 2 20,880 9,280 290 88 1584 8 564

XC2VPX20 8 1 22,032 9,792 306 88 1584 8 552

XC2VP30 8 2 30,816 13,696 428 136 2448 8 644

XC2VP40 0 or 8 or12 2 43,632 19,392 606 192 3456 8 804

XC2VP50 0 or 16 2 53,136 23,616 738 232 4176 8 852

XC2VP70 16 or 20 2 74,448 33,088 1,034 328 5904 8 996

XC2VPX70 20 2 74,448 33,088 1,034 308 5544 8 992

XC2VP100 0 or 20 2 99,216 44,096 1,378 444 7992 12 1,164

12

28

44

88

88

136

192

232

328

308

444 1). A FPGA board with USB controller is used to connect to a host PC, which runs

software Xilinx ISE9.2i that can program on-line the digital controller. The implementation of

DPWM and digital algorithm are designed in VHDL and schematic editor using Xilinx ISE

tool (design, function simulation, time simulation, mapping, placement and route). The USB

connector is used to download the final bitstream (routed circuits) to FPGA.

2). A voltage feedback synchronous buck converter is fabricated with a dynamic load

trigger circuit. The elements of buck converter are: 6.8L µH= , , 22C µ= F 5R = Ω ,

, and switching frequency 3.0inV V= 1.5outV = V sf is set up to 4MHz. The dynamic load

trigger circuit is used to test the transient response of the buck.

3). A third board that serves as the feedback voltage sampling contains an A/D component

AD9203, which takes analog-to-digital sample at 16MHz rate and the sampling clock is

offered by DCM of FPGA.

The detailed functionalities of these three boards will be discussed in the following sections.

6.2.1 FPGA Board

Fig. 6-5 (a) shows the FPGA development board, where XCV2P30 FPGA supports the

DPWM (Chapter 3), and digital control algorithms PID, RST (Chapter 4) and SMC (Chapter

5). The FPGA board communicates with a host PC through an USB which downloads the

final synthesized circuit. The software Xilinx ISE9.2i supports the program on-line to modify

the function of the digital controller. Since the automatic synthesis, simulation, timing

analysis, and verification tools are available for FPGA implementation, it is delightful that

these well-established and automated tools can dramatically speed-up the design procedure.

104

Moreover the design can be easily moved to another target or be modified to meet new

requirements.

Except the DCM (Digital Clock Management) parts, the blocks of the proposed digital

controller (DPWMs and control-algorithms) are implemented in VHDL. Like the DLL/and

PLL functions, the DCM is provided by FPGA manufacturing as an IP Core. Recently large

numbers of research have focused on low-jitter low-skew DLL/and PLL design. The

technique of designing a similar DLL IP Core in ASIC is not a critical issue in IC design. This

issue is not discussed here. The complete design is reusable for the design of an ASIC.

Fig. 6-3 Experimental test platform

VinC(t)NMOS

L

CPMOS

Xilinx FPGA XC2VP30

Power supplies1.5V, 2.5V, 3.3V, 5V

USB Connector

PCFPGA Board

R2R1

R4R3

VoutADCBoard

V[n]

Buck Converterand Dynamic Load Borad

Vin

Fig. 6-4 Block diagram of the experimental test platform

105

(a)

(b)

(c)

Fig. 6-5 Test platforms: FPGA board (a), Buck converter board (b) and A/D converter board (c)

106

6.2.2 Buck Converter And Dynamic Load Board

The Buck converter and dynamic load board is shown in Fig. 6-5 (b). The Buck converter

board implements the hardware of the digitally-controlled single-phase voltage regulator with

switching frequencies range of hundreds of kHz to several MHz. Currently due to the speed

limit of discrete Mosfets and drivers, the experimental tests operate up to 4MHz. The low-

voltage high-frequency Mosfet STS8C5H30L is used with high-speed driver EL7457CS. In

the future ASIC application with proper technique of integrated circuit, the switching

frequency can be greatly increased to meet the miniaturization demand.

In order to test the dynamic performance of the digital controller, an additional transient

load variation circuit is also set on the board. In the steady-state, two parallel load-lines are

connected with the buck output terminal, where each load-line consists of two 5Ω resistors in

series, resulting in the total load ( ) ( )5 5 / / 5 5 5Ω+ Ω Ω+ Ω = Ω (see Fig. 6-4 and Fig. 6-5 (b)).

When the system switches into transient state, a 5Ω resistor of the first and/or second load-

line will be cut off and results in a final load of 5Ω//5Ω=2.5Ω or 5Ω//(5Ω+5 Ω)=3.3Ω. Table

6-2 summarizes the parameters of the voltage regulator (Appendix E shows the detailed

circuit schematic).

Table 6-2: Prototype buck voltage regulator parameters

N Number of phase 1

inV Input voltage 3.0V

refV Reference voltage 1.5V

maxI Max. load current 1.2A

sf Switching frequency 1MHz ~ 4MHz L TAIYO YUDEN Inductance CBC2518T4R7M (4.7µH)

Lr Inductance ESR (DC) 8mΩ C TAIYO YUDEN Capacitor JMK212BJ226MG-T (22µF)

Cr Capacitor ESR (1kHz) 10mΩ R TYCO Resistor 5Ω

High side MOS− ST Microchip Mosfet STS8C5H30L (P-Channel) Low side MOS− ST Microchip Mosfet STS8C5H30L (N-Channel)

Hr δ High-side switch on-resistance 0.018Ω ~ 0.055Ω

Lr δ Low-side switch on-resistance 0.020Ω ~ 0.075Ω MOS Driver Intersil Mosfet driver EL7457

107

6.2.3 A/D Converter Board

As discussed in section 2.1.1, the resolution of the A/D converter should be fine enough

such that the output voltage error of power converter tightly falls within the allowed voltage

range. Thus a high resolution and high speed ADC topology is desirable for high performance

SMPS. However high resolution and fast sampling rate will consume energy and deteriorate

the SMPS efficiency. In order to reduce the power consumption, a window ADC topology is

conceived (section 2.2), which has high resolution only in a small window around reference

voltage . The advantage of the window ADC is to reduce the quantization window to the

possible variation range, which is usually tens of milli-volts centered around the reference

voltage. As a consequent, the window ADC has fine resolution with low energy consumption.

refV

As the preliminary research work for the project, the experiment here is only dedicated to

validate the functional performance of digital controller. Strategy looking for evaluation of

energy consumption still relies on the subsequent IC fabrication. Thus the A/D conversion

here is implemented using an A/D component (AD9203) shown in Fig. 6-5 (c). Table 6-3 lists

the configuration of AD converter board and Appendix F shows the detailed circuit schematic.

The A/D device is probably a high energy consuming block in the system, and remains an

effort-consuming task in ASIC implementation. This issue is not discussed here.

Table 6-3: AD converter configuration parameters

A/D Converter Analog Device AD9203 V∆ Sampling voltage range 0V~2V

NADC ADC resolution 10-bit

samplef Sampling frequency 16MHz

_d outt Data output delay 5ns

DDV Power supply 3.3V

6.3 Experimental Results The proposed digital control system consists of a synchronous Buck converter, a discrete

ADC and a FPGA-based digital controller shown in Fig. 6-6. Fig. 6-7 shows the RTL level

schematic map of the FPGA-based digital controller implementation. Due to page limit, the

details of VHDL codes and logic schemas of the digital controller are not shown here, and

Appendix G only shows the top-level architecture of the digital controller.

The experimental results for open-loop operation are shown in section 6.3.1, where the 11-

bit Hybrid dither DPWM (Chapter 3) operates up to 2MHz and the 11-bit Hybrid ∆-Σ DPWM

108

(Chapter 3) operates up to 4MHz. The experimental results for closed-loop operation are

shown in section 6.3.2, where the digital PID, RST and Tri-mode (Chapter 4) and SMC

(Chapter 5) algorithms operate at switching frequency up to 4MHz with 11-bit Hybrid ∆-Σ

DPWM. The experimental results of closed-loop operation below 4 MHz (1MHz and 2MHz)

are posted in Appendix F to Appendix I.

A/Dc1(t) c2(t) Vout [9:0]

VinPMOS

NMOS

L 4.7µHC

22µF

R 5Ω

3.3Ω

3.0V AD 9203

Mosfetdriver

iload0.3A

0.46A

Softmethod

d[10:0]Control

lawe[9:0]

x

Vref[9:0]digital

algorithm

-+

NCore

Vref digital ramp

4-bit DCMPhase-shift

Dead-time

4

c(t)

Sc11-bit

Hybrid DPWM

Buck converter ADC

FPGA-based digital controller

NCore+4

CounterNCore-bit

Fig. 6-6 Diagram block of the digital controller of a synchronous buck converter

Slope_function Clk_count

AD_filter

DCM_Clk

System_on_off

PID_control

RST_control

Dynamic_load

Output_PWM

Output_LED

REST_system

CLK_32M

button_startbutton _stop

data_AD[9:0]

button _CANCELbutton_SW1button_SW2

Switch2

Switch1

PWM2

PWM1

LED_verf_slopeLED_system_onLED_power_charge

LED_clk_ready

Clk_AD

Control_flag

Fig. 6-7 The schematic map of the FPGA-based digital controller synthesized in RTL level

109

6.3.1 Open-Loop Test for DPWM

In this section, the experimental results of open-loop test for DPWM (Hybrid dither and

Hybrid ∆-Σ DPWM) are illustrated.

As detailed in Chapter 3, both of two kinds of Hybrid DPWM consist of soft method

(digital dither approach or MASH ∆-Σ modulator) and hardware Core DPWM (counter-

comparator and segmented DCM phase-shift block). The Hybrid dither DPWM (shown in Fig.

3-11) operates up to 2MHz in this case, where the digital dithering is mathematic way to deal

with the LSB [2:0], and the hardware Core DPWM is to implement the HSB [10:3]. The

Hybrid ∆-Σ DPWM (shown in Fig. 3-23) operates up to 4MHz here, where the MASH ∆-Σ

modulator is the soft way to deal with the LSB [4:0], and the hardware Core DPWM is to

implement the HSB [10:5]. The operation conditions of the two DPWM architectures are

illustrated in Table 3-5. The following pages will present the operation waveforms of the

DPWM in FPGA implementation.

To demonstrate the functionality of the four-phase-shift DCM (shown in Fig. 3-6), Fig. 6-8

shows the experimental waveforms verified in FPGA. It can be seen the experimental results

validate the previous timing-simulation (shown in Fig. 3-13).

Fig. 6-8 Experimental waveforms of four-phase-shift DCM at 16MHz

Fig. 6-9 shows the waveforms and spectrums of Hybrid dither DPWM in open-loop test

(2MHz switching frequency and duty ratio 50%), where (a) shows the PWM gate signals of

110

high-side (P-channel) Mosfet and low-side (N-channel) Mosfet, and (b) shows the high-side

(P-channel) Mosfet gate signal and output voltage . From the view of spectrums of PWM

gate signals and voltage , the performance of Hybrid dither DPWM is quite satisfying. outV

outV

(a)

(b)

Fig. 6-9 Waveforms and spectrums of Hybrid dither DPWM in open-loop test (2MHz and duty ratio 50%):

PWM gate signals of high-side and low-side mosfets (a), and high-side PWM signal and output voltage (b).

Fig. 6-10 shows the similar waveforms and spectrums, but using the Hybrid ∆-Σ DPWM in

open-loop test (4MHz switching frequency and duty ratio 50%), where (a) shows the PWM

gate signals of Mosfets, and (b) shows the high-side (P-channel) Mosfet gate signal and

111

output voltage . From the view of spectrums of voltage , the noise produced by

Hybrid ∆-Σ DPWM is less than that of Hybrid dither DPWM. outV outV

(a)

(a)

Fig. 6-10 Waveforms and spectrums of Hybrid ∆-Σ DPWM in open-loop test (4MHz and duty ratio 50%):

PWM gate signals of high-side and low-side mosfets (a), and high-side PWM signal and output voltage (b).

6.3.2 Closed-loop Operation

The experimental results of closed-loop operation of the digital PID, RST, Tri-mode and

Sliding-mode controllers are detailed in following pages. The buck converter operates at

switching frequency 4sf MHz= with the Hybrid ∆-Σ DPWM.

112

A. PID and RST Controller Operation

Fig. 6-11 shows the steady-state output voltage and the corresponding PWM gate

signals (high-side Pmos and low-side Nmos) of PID operation. Fig. 6-12 shows the similar

ones, where the results are generated using RST controller. It can be seen in steady-state the

PID controller with simple algorithm computation can obtain satisfying output voltage as well

as RST does. The spectrum waveforms of PWM signals and output voltage show that there is

no oscillation in closed-loop operation.

outV

(a)

(b)

Fig. 6-11 Experimental waveforms of PID controller in steady-state:

PWM gate signals of high-side and low-side mosfets (a), high-side PWM signal and output voltage (b).

113

(a)

(b)

Fig. 6-12 Experimental waveforms of RST controller in steady-state:

PWM gate signals of high-side and low-side mosfets (a), high-side PWM signal and output voltage (b).

Fig. 6-13 shows the steady-state characteristic of PID controller, of which (a) shows the

comparison between reference voltage and output voltage in from 0.15V to 1.90V,

and (b) pictures the output voltage linearity refV outV

ref out refV V V− . It illustrates that the low-cost PID

controller maintains a stable output voltage quite well.

114

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vout Reference (V)

Vout

Mea

sure

men

t (V

)ideal

measurement

(a)

33.453.9

4.354.8

5.255.7

6.156.6

7.057.5

7.958.4

8.85

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Vout Reference (V)

∆Vou

t Er

ror (

%)

(b)

Fig. 6-13 Steady-state characteristics of PID controller: static error of output voltage (a) and linearity (b).

When the load suddenly changes from 0.3A to 0.46A (R: 5Ω→3.3Ω), the output voltage

transient responses of PID and RST controllers are respectively illustrated in Fig. 6-14 (a)

and (b). The PID controller takes 82µs to recover an undershoot (28mV) to the steady-state.

By contrast, the RST controller has a faster response (14µs) and smaller undershoot (20mV).

It can be seen that the RST controller has better dynamic performances than PID controller.

outV

115

(a)

(b)

Fig. 6-14 Transient output voltage of PID controller (a) and RST controller (b) when load goes from

0.3A to 0.46A (R: 5Ω→3.3Ω)

B. Tri-Mode Controller Operation

Under the same loading conditions from 0.3A to 0.46A (R: 5Ω→3.3Ω), Fig. 6-15 shows the

output voltage transient response using the tri-mode controller. It can be seen that when

the buck converter is in steady-state or stand-by mode, the PID controller maintains the

deserved output voltage. While in transient-mode, the RST robust controller can quickly

outV

116

regulate the dynamic output. It can be seen that the tri-mode controller offers the dynamic

performances of RST control but at the cost of a PID controller. Although the output voltage

suffers a small overshoot when the controller switches from transient mode (RST) to steady-

state mode (PID), this is acceptable compared to a PID controller alone (see Fig. 6-14 (a)).

These results show that the transient response time is small and the offset on the output

voltage is also less than 20mV, i.e. 1.4% of the output voltage (1.5V).

(a)

(b)

Fig. 6-15 Output voltage of Tri-mode controller when load varies from 0.3A to 0.46A (a) and 0.46 to 0.3A (b)

117

C. SMC Operation

Fig. 6-16 shows the steady-state output voltage and the corresponding PWM gate signals

(high-side and low-side Mosfets) of SMC operation. The spectrum waveforms of PWM

signals and output voltage show that there is no oscillation in closed-loop operation.

(a)

(b)

Fig. 6-16 Measured waveforms for CMS in steady-state: high-side (P-channel) and low-side (N-channel)

PWM signals (a), high-side PWM signal and output voltage (b).

When the load suddenly changes from 0.3A to 0.46A (R: 5Ω→3.3Ω), the output voltage

transient responses is illustrated in Fig. 6-17. It can be seen that the SMC has good

dynamic performances with short response time and low voltage overshoot/undershoot. outV

118

Fig. 6-17 Transient output voltage of SMC when load varies from 0.3A to 0.46A (R: 5Ω→3.3Ω).

6.4 Summary In this Chapter, the FPGA-based implementations of digital controllers on a discrete buck

converter are detailed. The experimental results of open-loop and closed-loop operations are

illustrated, which includes the experimental test of Hybrid dither DPWM and Hybrid ∆-Σ

DPWM in open-loop, and includes the operation results of PID, RST and SMC controllers.

Also introduce the result of Tri-mode controller.

From the above experimental results, the performance comparison of PID, RST and SMC

controllers can be drawn in Table 6-4. It is clear that both RST and SMC have better

performance than PID. In addition, the FPGA resources consumption of the three controllers

is summarized in Table 6-5. As described in equation (4.22), (4.23) and (5.34), the SMC has

the simplest calculation architecture and requires the least FPGA resource among three

controllers. That means the energy consumption will be least under the same manufacturing

process in future ASIC application.

The fast transient response, good configurability, high linearity and noise immunity, make

the proposed digital controllers attractive candidates for high-frequency and low-power SMPS.

Table 6-4 Performance comparison of PID, RST and SMC

Controller Response time Undershoot voltage Performance Computaion architecture

PID Long (82µs) Large (28mV) Medium Medium (5 Multipliers)

RST Fast (14µs) Small (20.4mV) Good Complicated (9 Multipliers)

SMC Fast (22.5µs) Small (19.8mV) Good Simple (3 Multipliers)

119

Table 6-5 FPGA Utilization for PID, RST and SMC Controllers (Xilinx Virtex-II Pro XC2VP30) Logic Utilization Controller Used Available Utilization

Number of Slice Flip-Flops PID RST SMC

771 1139 593

27,392

2.8% 4.16% 2.16%

Number of 4-input LUTs PID RST SMC

583 853 426

27,392

2.1% 3.11% 1.56%

Logic Distribution

Number of occupied Slice PID RST SMC

498 685 402

13,696

3.64% 5%

2.94% Number of Slice containing only related logic PID

RST SMC

498 685 402

Number of Slice containing unrelated logic PID RST SMC

0 0 0

Total Number of 4-input LUTs PID RST SMC

612 882 455

27,392

2.2% 3.2%

1.66% Number used as logic PID

RST SMC

583 853 426

Number used as a route-thru PID RST SMC

23 23 23

Number used as a Shift registers PID RST SMC

6 6 6

Number of bonded IOBs PID RST SMC

26 26 26

556

4.67% 4.67% 4.67%

IOB Flip-Flops PID RST SMC

5 6 7

Number of PPC405s PID RST SMC

0 0 0

2

0% 0% 0%

Number of MULT18x18s PID RST SMC

10 18 6

136

7.35% 13.24% 4.41%

Number of GCLKs PID RST SMC

4 4 4

16

25% 25% 25%

Number of DCMs PID RST SMC

2 2 2

8

25% 25% 25%

Number of GTs PID RST SMC

0 0 0

8

0% 0% 0%

120