Chapter 5 MOSFET differential amplifierfuuu.be/polytech/ELECH402/Quitin/Ch5_Diff_Amp.pdf · 2017....

MOSFET differential amplifier

ELEC-H402/CH5: MOSFET differential amplifier 1

Chapter 5

Outline

• Introduction

• Ideal MOS differential pair– Common-mode voltage

– Large-signal operation

– Small-signal operation

• Nonidealities– Common-mode rejection ratio

– Input offset voltage

• Differential amplifier with active load

• Frequency response of differential amplifier

• Multistage amplifiers


Why a differential amplifier ?

• Many sensors provide a differential voltageWhen transmitting this differential voltage over cables, they become

susceptible to common-mode voltage (power lines, RF interference, magnetic fields, …)

Common-mode voltage also appears if ground of sensor is different from ground of circuit

Differential voltage can be small w.r.t. common-mode voltage


… differential voltage – polluted by common mode

cV

cV

ECG

cV

cV 1iV

2iV oV

idv

1iV

2iV oV

automotive sensors

idv

oV

1iV

2iV

dA

Ideal differential amplifier

• Ideal differential amplifierHigh differential gain Ad

Small common gain Ac

High input resistance

• How to build this in MOSFET technology ?


only amplifies the difference between input voltages

1 21 2

2

i io c d i i

c c d id

V VV A A V V

AV A v

1 2o d i iV A V V

1 21

1 22

22

2

idi ii c

c

idid i ii c

vV VV V

V

vv V VV V

Ideal MOS differential pair

• 2 inputs are the two gates of the transistorsHigh input impedance !!!


2 matched transistors, biased by current source

Assumptions: - Transistors identical- Drain resistors identical- Perfect current source

1 2

1 2

1

2

2

2

2

G GCM

id G G

idG CM

idG CM

v vv

v v v

vv v

vv v

Common mode and differential mode:


• Identical voltage at both inputs


Common-mode input voltage

Symmetry arguments:

1 2

1 2

2 1

/ 2

/ 2

0

D D

D DD D D

o D D

i i I

v V R I v

v v v

Common gain is zero



Max. and min. common-mode input voltage

Q1 and Q2 in saturation:

2

DS GS t

DD D D S CM S t

DCM DD t

v v V

V R i v v v V

R Iv V V

Current source must operateproperly: Minimum voltage VCS over current source

S SS CS

CM GS SS CS

CM SS CS GS

v V V

v V V V

v V V V



Differential input voltage: large-signal behavior

1

1 2

20

id GS S

id GS GS

GS S

v v vv v v

v v

2 1 2 1

1 2

o D D DD D D DD D D

oD D

D

v v v V R i V R i

vi i

R

1 2D Di i I

01

02

2 2

2 2

od

d

od

d

I vi

R

I vi

R




2

1 1

2

2 2

1

2

1

2

D n GS t

D n GS t

Wi k v V

L

Wi k v V

L

1 2 1 2

2

id

GS GS D D

nv

Lv v i i

k W

1

2

2 2

2 2

oD

D

oD

D

vIi

R

vIi

R

21

12 2

ido D id n n

vW Wv R v k I k

L L I




2

2

1

2

2

11

2 2

/ 21

2 21/

/ 21

2 21/

ido D id n n

ididD n

n

ididD n

n

vW Wv R v k I k

L L I

vvI Wi k I

WLk

L

vvI Wi k I

WLk

L

vid controls how much current flows through eachbranch of the circuit- vid positive: more current through left branch- vid negative: more current through right branch




Note that when vid = 0 :

1 2

1 2

2

/ 2

1

2 2OV

D D

GS GS GS

n GS t

V

i i I

v v V

I Wk V V

L

2

1

2

2

/ 21

2 2

/ 21

2 2

id idD

OV OV

id idD

OV OV

v vI Ii

V V

v vI Ii

V V


• currents iD1 and iD2




• VOV can be changed (e.g. by changing W or L for unchanged I)

Controls slope of currents



21

2 2n OV

I Wk V

L



Differential input: small-signal behavior

1

2

2

2

idG CM

idG CM

vv v

vv v

1 1 1

2 2 2

o D d D m gs

o D d D m gs

o m D id

v R i R g v

v R i R g v

v g R v



Differential input: small-signal behavior

o m D id

d m D

v g R v

A g R

with m

GS t OV

I Ig

V V V

idv

ov

m Dg R

DR I

DR I

all current flowsthrough left branch

all current flowsthrough right branch


• NMOS output resistance plays role in final gain

• Resistance of current source for biasing plays no role in gain prove this as an exercise!


effect of MOSFET’s ro

1

2

|| / 2

|| / 2

||

o m D o id

o m D o id

o m D o id

v g R r v

v g R r v

v g R r v

Nonidealities of MOS differential pair

• For a ideal MOS differential pair:


Common-mode rejection ratio

CMRR d

cm

A

A

2 1

2 1

0

CMRR

o ocm

icm

o od m D

id

v vA

v

v vA g R

v


• Q1 has load RD and Q2 has load RD +ΔRD

•


Effect of RD mismatch

1

2

2

2

2

Do icm

SS

D Do icm

SS

Dcm

SS

Rv v

R

R Rv v

R

RA

R

d m DA g R

CMRR/ 2

2CMRR

/

m D

D SS

m SS

D D

g R

R R

g R

R R

D DR R



Effect of gm mismatch

1 1 1 1 1

2 2 2 2 2

d m gs d m

d m gs d m

i g v i g

i g v i g

1 2S

d d

SS

vi i

R

1 2

largeSS S icm

icmd d

SS

R v v

vi i

R

11

1 2

22

1 2

m icmd

m m SS

m icmd

m m SS

g vi

g g R

g vi

g g R



Effect of gm mismatch

11

22

2

2

m icmd

m SS

m icmd

m SS

g vi

g R

g vi

g R

1 2

1 2

2 small

m m m

m

m m m

g g gg

g g g

2 1 2 1

2

o o o d D d D

m Do icm

m SS

v v v i R i R

g Rv v

g R

2CMRR

/

m SS

m m

g R

g g

Nonidealities: input offset voltage

• Imagine both inputs groundedNonidealities will cause output offset voltage VO

We divide VO by Ad to get input offset voltage VOS


Mismatches in circuit cause output offset voltage



Effect of RD mismatch on VOS

11

2 2

22

2 2

DDD DD D DD D

D DD D D DD D D

RR V V I RR R

R RR R V V I R

2 12

2

O D D D

OV DOS

D

IV V V R

V RV

R

/OS O dV V A



Effect of (W/L) mismatch on VOS

1

1

22

/1

2 2 2 /2

1 /

2 2 2 2 /

W LI IW W W IW LL L L

W W W W LI II

L L L W L

1 2

/

2 /

O D

OVOS

V R I I

W LVV

W L



Effect of Vt mismatch on VOS

1

2

2

2

tt t

tt t

VV V

VV V

2

1

2

2

2

1

2 2

11

2 2

11

2

tn GS t

tn GS t

GS t

tn GS t

GS t

VWI k V V

L

VWk V V

L V V

VWk V V

L V V

2

2

11

2

tn GS t

GS t

VWI k V V

L V V



Effect of Vt mismatch on VOS

1 2O D

tO D

OV

OS t

V R I I

VV R I

V

V V


• Circuit is linear and three sources of offset voltage are uncorrelated superposition can be applied


Combined effect of mismatches on VOS

/

2 2 /

OV OVDOS t

D

W LV VRV V

R W L

eo+

-

Rid

I+

Ro

I-

Ampli parfait

Input offset voltage in op-amp isdue to assymetries in NMOS differential pair

Differential amplifier with active load

• Mulitstage circuits usually use single-ended voltages – Voltage w.r.t. ground of circuit

Differential output cannot always be used


Differential to single-ended conversion

2

ido m D

vv g R

we lose a factor 2 (6dB) « wasting » the signal


• differential pair Q1 and Q2 loaded in a PMOS current mirrorby Q3 and Q4


Active-loaded differential MOS pair

Reminder

• Current through Q3 determinescurrent going through Q4


PMOS current mirror

3 3

3 3

Q3 saturation

0

SD SG t

D G t

t

v v V

v v V

V

Q3 always in saturation region

2

3 3

2

4

3 4

1

2

1

2

D n SG t

n SG t

D D

Wi k v V

L

Wk v V

L

i i

3Di 4Di


• Q1 and Q2 have same common-mode voltage current I/2 flowing through Q1 and Q2

current I/2 flowing throug Q3

mirror current => current I/2 through Q4

output current is zero

equilibrium state




• Differential voltage causes– increase of i in Q1 and decrease of i in Q2

– current i going through Q3

current i going through Q4

output current of 2i



2

2

idm

m id

vi g

i g v

m idg v

Norton equivalentcircuit:

o o m id

d o m

v R g v

A R g


• Many intermediate steps…


Output resistance Ro

3oR

1oR



Output resistance Ro – step 1: compute RO3

xi

3

3

1o

m

Rg

xi

0Gi

3 3 3x o x m SGv r i g v

3 0SG xv v

3 3

33

3 31

x o x m x

x oo

x o m

v r i g v

v rR

i r g




1

1

1o

m

Rg

3 1 1 1x o x o x m GSv R i r i g v

3 0SG xv v

3 1 1

3 1 3 11

1 1 1 1

1/

1 1

x o x o x m x

x o o m oo

x o m o m

v R i r i g v

v R r g rR

i r g r g

xi

xi

3oR




1oR

xi

xi 2 2 2 2

1

11o o m o

m

R r g rg

1 2 2 2x o x o x m GSv R i r i g v

1 2m mg g

1 2 2 1

2 1 2 2 2 1

x o x o x m o x

xo o o o m o

x

v R i r i g R i

vR R r r g R

i

2 10 0GS S o xv v R i

2 22o oR r



Output resistance Ro – step 4: compute RO

3oR

1oR

4

xx

o

vi i i

r

2/x oi v R

2 4||o o oR r r

2 4

2 4

2 x xx

o o

x xx

o o

v vi

R r

v vi

r r

2 4||

d o m

d o o m

A R g

A r r g


• Effect of current source resistance RSS


Common-mode gain and CMRR

Equal current in bothbranchesSplit RSS into 2RSS on eachbranch




1 22

icm

SS

vi i

R RSS large =>

1 2 2 2o o o SS m o SSR R r R g r R

4 4 2

4 1 4 3 2

3

1||

o o

o m o

m

v r i i

r i g r ig

3 1 3

3

1||g o

m

v i rg

4 4 3

1 4 3

3

1||

m g

m o

m

i g v

i g rg




1 22

icm

SS

vi i

R RSS large =>

4 4 3

3

4

3 3

1|| 1

2

1

2 1

icmo o m o

m SS

o ocm

icm SS m o

vv r g r

g R

v rA

v R g r

3 4m mg g

3

1

2cm

m SS

Ag R

2 4 3CMRR || 2

CMRR

dm o o m SS

cm

m o m SS

Ag r r g R

A

g r g R

3 2 4if and m m o o og g r r r

Frequency response of differential amplifier

• Capacitance CSS contains: – Cdb and Cgd of QS

– Csb of Q1 and Csb of Q2

• No change for differential input


Resistively-loaded MOS amplifier


• Common-mode half-circuit:– Frequency of CSS/2 and 2RSS is much lower than frequency de to other

capacitances

=> Other capacitances (Cgs, Cgd, Cdb) of transistors ignored



2

Dcm

SS

RA

R

Reminder:

2 2

1

2

12

D Dcm SS

SS

Dcm SS

SS

Dcm SS SS

SS

R RA Y

Z

RA j C

R

RA j R C

R

1

2Z

SS SS

fR C


• Acm increases with frequencyAt some point, other capacitances of transistor kick in

Acm starts to decrease




• Differential signal common-source amplifier

See frequency response of CS amplifier in previous chapter






CMRR decreases (strongly) withfrequency, starting at fZ


• Capacitance Cm formed by several capacitances:

• Capacitance CL formed by several capacitances:


Active-loaded MOS amplifier

1 1 3 3 4m gd db db gs gsC C C C C C

2 2 4 4L gd db gd db xC C C C C C

Load capacitance




1 / 2d m idI g V

3 1

3

3

3

1||

2

g m d

m

m idg

m m

V C Ig

g VV

g j C

4 4 3

4

3

/ 2

1 /

d m g

m idd

m m

I g V

g VI

j C g

3 4m mg g

4 2

3

/ 2/ 2

1 /

o d d

m ido m id

m m

I I I

g VI g V

j C g




3

/ 2/ 2

1 /

m ido m id

m m

g VI g V

j C g

||o o o LV I R C

3

1 11

2 11

ido m o

m L o

m

VV g R

j C j C R

g




3

1 11

2 11

ido m o

m L o

m

VV g R

j C j C R

g

3

3

121

11

m

md m o

mL o

m

j C

gA g R

j Cj C R

g

32

2

mZ

m

gf

C

1

1

2P

L o

fC R

32

2

mP

m

gf

C

Often dominant pole

Very high frequency!

Note that fZ due to current source is usually main cause of CMRR degradation

Multistage amplifier


Two-stage CMOS amplifier

1 1 2 4||m o oA g r r

2 6 6 7||m o oA g r r

1 2totA A A

6 7||o o oR r r

• Q1-Q2 MOS differentialamplifier with active load (Q3-Q4)• Q6 common-source amplifier• Current mirror Q8-Q5 for polarizing Q1-Q2• Current mirror Q8-Q7 for polarising Q6

Capacitor Cc (see next slide)dominant pole-20dB/decadestability

Multistage amplifier


Frequency response

1 4 4 2 2 6gd db gd db gsC C C C C C 2 6 7 7db db gd LC C C C C

2

2

mZ

C

Gf

C

1

1 1 2 2

1

2 1P

C m

fR C C G R

22

2

mP

Gf

C

Choose CC so that fP1 lowerthan fZ and fP2, in order to ensure -20dB/decade

Chapter 5 MOSFET differential amplifierfuuu.be/polytech/ELECH402/Quitin/Ch5_Diff_Amp.pdf · 2017....

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