1

Prof. Sang-Jo Yoo

Chapter 5 Field-Effect Transistors (FET)

2

Prof. Sang-Jo Yoo

5.1 NMOS Field Effect Transistor

MOSFET = Metal Oxide Semiconductor Field Effect Transistor

Four terminal device (gate, source, drain, substrate)

Unipolar transistor – one type of charge carrier

FET is a current control mechanism based on an electric field established by the voltage applied to the control terminal

3

Prof. Sang-Jo Yoo

Creating a Channel for Current Flow

A positive voltage is applied to the gate which forms an inversion layer, or an n-type channel

Threshold voltage Vt : the value of VGS at which sufficient number of mobile electrons accumulate in the channel region to form a conducting channel.

4

Prof. Sang-Jo Yoo

Operation with Small vDS

Effective voltage: (VGS –Vt)

Enhancement-mode operation or enhancement-type MOSFET: increasing VGS above Vtenhances the channel

vDS(mV)

iD(mA)

50 100 150 200

0.4

0.3

0.2

0.1

vGS ≤Vt

vGS=Vt+1V

vGS=Vt+2V

vGS=Vt+3V

vGS=Vt+4V

vDS(mV)

iD(mA)

50 100 150 200

0.4

0.3

0.2

0.1

vGS ≤Vt

vGS=Vt+1V

vGS=Vt+2V

vGS=Vt+3V

vGS=Vt+4V

5

Prof. Sang-Jo Yoo

Operation as vDS is Increased

G

S

B

D

n+

p-type substrate

n+

+vGS

-

+vDS

-VGS

VGS-VDS

Increasing vDS causes the channel to acquire a tapered shape

Eventually, as vDS reaches vGS-Vt, the channel is pinched off at the drain end

Increasing vDS above vGS-Vt has little effect (theoretically no effect) on the channel’s shape

Source Channel DrainvDS

vDS ≥ vGS-Vt

vDS =0

Source Channel DrainvDS

vDS ≥ vGS-Vt

vDS =0

Increased resistance

6

Prof. Sang-Jo Yoo

Operation as vDS is Increased (cont.)

vDS

iD

vDS < vGS −VtvDS ≥ vGS −Vt

vDSsat = vGS −Vt

vGS >Vt

Triode Saturation

Curve bends because the channel resistance increases with vDS

Almost a straight line with slope proportional to (vGS-Vt)

Current saturates because the channel is pinched off at the drain end, and vDS no longer affects the channel

7

Prof. Sang-Jo Yoo

Derivation of the iD - vDS Relationship

( ) ( )( )[ ]dxVxvvWCxdq tGSox −−−=The voltage drop between thegate and the channel, in excessof the threshold voltage Vt

determines the amount of charge

Charge dq

Capacitor per unit area

Electric field E(x)=-dv(x)/dx causes the electron charge dq(x) to drift toward the drain with a velocity dx/dt.

8

Prof. Sang-Jo Yoo

Derivation of the iD - vDS Relationship

( ) ( )dx

xdvxE

dt

dxnn µµ =−=

( ) ( )

( ) ( )( )[ ]tGSox

n

VxvvWCdx

xdqdx

xdvvelocity

dt

dx

dt

dx

dx

xdq

dt

dqi

−−−=

==== µ

( )( )[ ] ( )xdvVxvvWCdxi tGSoxnD −−= µ ( )( )[ ] ( )∫∫ −−=DSv

tGSoxn

L

D xdvVxvvWCdxi00

µ

( ) ⎥⎦

⎤⎢⎣

⎡−−=

2

2DS

DStGSoxnD

vvVv

L

WCi µ

Terminal potentials

Layout GeometriesProcessTechnology

9

Prof. Sang-Jo Yoo

Derivation of the iD - vDS Relationship

Triode Region

( )

ratioaspect

parameter ctance tansconduprocess'

2'

2

=

=⎥⎥⎦

⎤

⎢⎢⎣

⎡−−=

L

W

k

vvVv

L

Wki

n

DSDStGSnD

Saturation Region

( )

tGSDS

tGSnD

Vvv

VvL

Wki

−=←

−= 2'

10

Prof. Sang-Jo Yoo

PMOS Field Effect Transistors

Gate (G)Drain (D)

Body (B)

Source (S)

p+

L

Channelregion

n-type substrate (Body)

MetalOxide (SiO2)

p+

Sub-threshold RegionFor values of vGS smaller than but close to Vt, a small drain current flows.

11

Prof. Sang-Jo Yoo

CMOS technology

12

Prof. Sang-Jo Yoo

5.2 Current-Voltage Characteristics of Enhancement MOSFET

D

S

G

D

S

GB

S

D

G

S

D

G B

NMOS PMOS

MOSFET Circuit symbols

13

Prof. Sang-Jo Yoo

The iD-vDS Characteristics (NMOS)

( )

( )[ ]DStGSn

DSDStGSnD

vVvL

Wk

vvVv

L

Wki

−≈

⎥⎥⎦

⎤

⎢⎢⎣

⎡−−=

'

2'

2

Linear relationship

( )⎥⎦⎤

⎢⎣⎡ −=≡∴ tGSn

D

DSDS Vv

L

Wk

i

vr '1

14

Prof. Sang-Jo Yoo

iD vs. vGS Characteristic for an NMOS transistor in saturation

( )2' tGSnD VvL

Wki −=

Current amplifier( )2'

2

1tGSnD VV

L

Wki −=

G

S

DiG=0 iD

+

-

+

-

vGS vDS

vDS ≥ vGS-Vt

vGS ≥ Vt

Large Signal Model of a MOSFET in Saturation

Fig 5.14 (important)

15

Prof. Sang-Jo Yoo

Finite Output Resistance in Saturation

( ) ( )DStGSnD vVVL

Wki λ+−= 1

2

1 2'

Channel Length Modulation:Increasing vDS beyond vDSsat causes the channel pinch-off point

to move slightly away from the drain

03.0~005.0=λ

16

Prof. Sang-Jo Yoo

Channel Length (Drain Current) Modulation due to changes in VDS

[ ] 1−== DD

AO I

I

Vr λ

17

Prof. Sang-Jo Yoo

Large Signal Model of the MOSFET Incorporating the Output Resistance

Body-Effect : page 374

18

Prof. Sang-Jo Yoo

5.3 The Depletion-type MOSFET

Similar to that of the enhancement-type MOSFET.

The depletion MOSFET has a physically implanted channel.

N-channel depletion-type MOSFET has an n-type silicon region connecting the n+ source and the n+ drain regions at the top of the p-type substrate.

Even when vGS=0, there is iD current.

The negative vGS (channel becomes shallower and its conductivity decreases) is said to deplete the channel of its charge carriers(depletion mode).

19

Prof. Sang-Jo Yoo

The Depletion-type MOSFET

( )2'

2

1tnDSS V

L

Wki =

20

Prof. Sang-Jo Yoo

Example 5.1

Design the circuit shown below so that the transistor operates at ID = 0.4 mA and VD= 1V. The NMOS transistor has Vt = 2 V, µnCox = 20 υA/V2, L = 10µm, and W = 400 µm. Assume λ = 0.

Since VD = 1V, we are operating in the saturation region. (page 370)

( )

( )

( )( )( )

1or 3

130

3420

210

4001020

2

14.0

2

1

22

23

2

==−−=

+−=−=

−×××=

−=

−

GSGS

GSGS

GSGSGS

GS

tGSoxnD

VV

VV

VVV

V

VVL

WCI µ

Ω=−−−

=−

= kI

VVR

D

SSSS 5

4.0

)5(3

Choose VGS = 3V. (VGS >Vt)

To establish +1V at the drain,

Ω=−

=−

= kI

VVR

D

DDDD 10

4.0

15

VV DD5+=

VV SS5−=

RD

RS

I D

I D

V D

21

Prof. Sang-Jo Yoo

Example 5.3Design the circuit shown below to establish a drain voltage of 0.1V. What is the effective resistance between drain and source at this operating point? Let Vt = 1 V, and kn’(W/L) = 1 mA/V2.

The MOSFET is operating in the triode region, since the drain voltage is lower than the gate voltage, and Vt is 1V.

( ) mA 395.001.02

11.0151 =⎥⎦

⎤⎢⎣⎡ ×−×−×=I D

VV DD5+=

RD

VV D1.0+=

I D

Ω=== 253395.0

1.0

D

DSDS I

Vr

Effective drain-to-source resistance,

Ω=−

=−

= k 4.12395.0

1.05

D

DDDD I

VVR

The required resistor value,

tGSDS VVV −≤ ( )⎥⎥⎦

⎤

⎢⎢⎣

⎡−−=

2'

2DS

DStGSnDv

vVvL

Wki

22

Prof. Sang-Jo Yoo

Example 5.4 NMOS

Analyze the following circuit to determine all the node voltages and branch currents, given that Vt=1V and k’n(W/L) is 1mA/V2. Neglect the channel length modulation effect (i.e. assume λ=0)

Since the gate current is zero (why?), the voltage at the gate is simply determined by voltage division between RG1 And RG2, and since they are equal VG is VDD/2 or 5 Volts.

We will assume that it is saturated and solve the problem and then check the validity of our assumptions.

The saturation equations are easier to work with and that makes a good choice for starting out. If our assumptions do not check out we have to go back and use the triode region equations

The drain current has to be equal to the source current since IG is zero

VGS = 5 - 6,000(ID)

And in saturation

D

SG

+vS

-

RG1 = 10 MΩ

RG2 = 10 MΩ

RD = 6 kΩ

RS = 6 kΩ

VDD = +10 V

assumed+5 V

ID =IS

IS =ID

( )2'2

1tGSnD VV

L

WkI −=

23

Prof. Sang-Jo Yoo

Example 5.4 continued

Again, in saturation

( )2'2

1tGSnD VV

L

WkI −= ( ) ( )( )( )( )21000,65001.0

2

1−−= DD II

082518 2 =+− DD II

This yields two values for ID, 0.89 mA and 0.5 mA

Which is valid for our assumption of saturation?

For ID of 0.89 mA the source voltage would be 6,000(0.00089) or 5.34 Volts which is higher than the gate voltage and since the gate to source voltage to turn the device on (i.e. threshold voltage) is +1 Volt the device would be off not saturated this answer is not valid.

For ID of 0.5 mA the source voltage would be 6,000(0.0005) or 3 Volts which means the gate to source voltage is 5-3 or 2 Volts which is greater than the threshold voltage (+1 Volt) and the device is on. But is it saturated?

The drain is at 10-(6,000)(0.0005) or 7 Volts

VDS=7-3 or 4 Volts

Since VDS (4V) is greater than VGS-Vt (2V-1V) the device is by definition in saturation so our initial assumption was correct

24

Prof. Sang-Jo Yoo

5.5 MOSFET as an Amplifier

We can obtain amplification of a small analog signal by use of an enhancement mode MOSFET.

This circuit is not practical because

The dc voltage source at the input is difficult to implement

Integrated circuit resistors take up too much room

MOSFETs are used for loads

To be used as an amplifier the MOSFET must be biased in the saturation region

To find the dc bias we set the ac component of the input to zero and determine the dc drain current in saturation

( )2'2

1tGSnD VV

L

WkI −=

25

Prof. Sang-Jo Yoo

The Signal Current at the Drain

The dc voltage at the drain, VD will be equal to VDD - RDID

To ensure saturation we must have

Now we go back to the situation where we have both the dc bias and the ac signal

The resulting total instantaneous drain current to be

We can focus on the ac response if we keep the input signal small, such that

tGSDS VVV −>

gsGSGS vVv +=

( )

( ) ( ) ( )2''2'

2'

2

1

2

12

1

gsngstGSntGSnDS

tgsGSnDS

vL

WkvVV

L

WkVV

L

Wki

VvVL

Wki

+−+−=

−+=

dc bias ac response non-linear ac response

( ) ( )tGSgsgstGSngsn VVvvVVL

Wkv

L

Wk −<<−< 2or

2

1 '2'

26

Prof. Sang-Jo Yoo

Transconductance

If the small-signal condition specified on the previous page is satisfied we can neglect the last non-linear term in the current equation and express iD as

Where

And we know that the ratio of id to vgs is the transconductance gm

In general

dDD iIi +≅

( ) gstGSnd vVVL

Wki −= '

( )tGSngs

dm VV

L

Wk

v

ig −=≡ '

GSGS VvGS

Dm v

ig

=∂∂

≡

27

Prof. Sang-Jo Yoo

Voltage Gain

The total instantaneous drain voltage is

Using the small signal condition

The small-signal component of the drain voltage is

The voltage gain is then given by

DDDDD iRVv −=

( ) dDDDdDDDDD iRVviIRVv −=+−= or

gsDmDdd vRgRiv −=−=

Dmgs

d

in

out Rgv

v

v

v−==

28

Prof. Sang-Jo Yoo

DC Bias with an ac small signal

The DC bias level determines the ac parameters

By restricting the input signal swing to small values we can “linearize” the characteristic.

+

vDS(t)

-

vgs(t)

iDS(t)

VGS +DC

ac(DC+ac)

(DC+ac)

D

SG

VDD

RD

29

Prof. Sang-Jo Yoo

The Input and Output Signals

The output is 180 degrees out of phase from the input. We have an inverting small signal amplifier in this configuration

In order for the transistor to operate in the saturation region at all times there is a minimum drain voltage that must be maintained.

30

Prof. Sang-Jo Yoo

Small-Signal Saturation Equivalent Circuit Models

From a small-signal point of view the FET behaves like a voltage controlled current source.

The input resistance is high (ideally infinite)

After the DC analysis is done to determine the ac parameters and then the ac equivalent circuit is drawn.

In the first model is was assumed that the drain current did not change with increasing VDS in saturation but we know that it does.

The dependence can be modeled by a finite resistance ro, between source and drain, whose value is approximated by the equation shown at the left.

D

Ao I

Vr ≅

31

Prof. Sang-Jo Yoo

The Transconductance - gm

The transconductance is the incremental change in drain current due to an incremental change in gate voltage or

If we solve the saturation current equation for VGS-Vt we get

and by substitution

So gm is proportional to the square root of the dc bias current

At any bias current gm is proportional to the square root of W/L

( )tGSnm VVL

Wkg −⎟

⎠⎞

⎜⎝⎛= '

( )⎟⎠⎞

⎜⎝⎛

=−

LW

k

IVV

n

DtGS

'

2

Dnm IL

Wkg '2= rs transistoBJTfor

T

Cm V

Ig =

32

Prof. Sang-Jo Yoo

Example 5.8 - Complete Amplifier Analysis

We will assume that the coupling capacitors are large enough so that they act as short circuits for the ac signal frequencies of interest. We wish to analyze the amplifier circuit to determine its small-signal voltage gain and its input resistance. The transistor has Vt=1.5V, kn

’(W/L) = 0.25mA/V2, and VA = 50V.

+

vDS(t)

-

+vi

-

ac

D

SG

VDD=15V

RD=10kΩ

Rin

RG=10MΩ

RL=10kΩ∞∞

Start by doing the dc analysis (saturation)

( )( )

( )( )2

2

5.1000125.0

5.100025.02

1

0 since

−=

−=

==

DD

GSD

GDGS

VI

VI

IVV

( )DDDD IIRV 000,101515 −=−=

mAIVV DD 06.1 4.4 ==

33

Prof. Sang-Jo Yoo

ac equivalent circuit for Example 5.8

+vgs

-

D

gmvgs

G

ro+vgs

-RD

+vo

-RL

Rin

vi

RG

The value of gm is given by

The MOSFET output resistance ro is

We can now us the ac equivalent circuit.

( ) ( )V

mAVV

L

Wkg tGSnm 725.05.14.400025.0' =−=−⎟

⎠⎞

⎜⎝⎛=

Ω=== kI

Vr

D

Ao 47

00106.0

50

( ) igsoLDgsmo vvrRRvgv =−≅ ,||||

( )

( )3.3

000,47||000,10||000,10000725.0

||||

=−=

−==

v

v

oLDmi

ov

A

A

rRRgv

vA

( ) ( )( )

Ω===≡

=−=⎟⎟⎠

⎞⎜⎜⎝

⎛=

−=

M33.23.4

000,000,10

3.4

3.43.31 1

G

i

iin

G

i

G

i

i

o

G

i

G

oii

R

i

vR

R

v-

R

v

v

v-

R

v

R

vvi

34

Prof. Sang-Jo Yoo

The Source Absorption Theorem (Appendix E)Used to derive the “T” Model for a MOSFET

35

Prof. Sang-Jo Yoo

5.6 Biasing in MOS Amplifier Circuits

Biasing is the establishment of an appropriate dc operating point for the transistor.

An appropriate dc bias point has a stable and predictable dc drain current ID, and a dc drain to source voltage that ensures operation in the saturation mode for all expected input signal levels.

The circuit shown at the right is commonly used when a single power supply is available.

Since the gate current is zero the two gate bias resistors RG1 and RG2 can be selected to be very large (MΩ range)

This will provide a large amplifier input resistance

A resistor, called a self bias resistor is connected to the source.

RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.

V DD

RG1

RS

I D

RG2

RD

36

Prof. Sang-Jo Yoo

MOSFET Biasing - Dual Supplies

For symmetric supplies a simpler bias arrangement can be used.

The resistor RG establishes a dc ground at the gate of the transistor.

Directly grounding the gate will also establish a dc bias but RG is used to increase the input resistance seen by a signal source that may be capacitively coupled to the gate

RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.

V DD

RS

I D

RG

RD

V SS−

37

Prof. Sang-Jo Yoo

MOSFET Biasing with a Constant Current Source

Having a constant current source establishes the source and drain current level.

We will look at how to construct a constant current source shortly

I D

RG

RD

V SS−

I

Common-Source Circuit with Resistive Gate

Feedback

V DD

I D

RG

RD

0

The feedback resistor RG forces the dc voltage at the gate to be the same as that of the drain (since IG = 0).

38

Prof. Sang-Jo Yoo

Exercise 5.22

Exercise 5.22 Design the circuit below for a MOSFET having k’n(W/L) = 0.5 mA/V2 and Vt = 2V, and utilizing two power supplies, ± 10V. Design for ID = 1mA and allow for a signal swing at the drain of ±2V. The amplifier is required to present a 1MΩ input resistance to a signal source. Assume λ=0.

V10+

RS

I D

RG

RD

V10−

ΩM1

∞( )

( )Ω=

−−−=

−===

−×=

=Ω=

==

kR

VV

V

V

IR

VL

Wk

S

SG

GS

GS

DG

tn

6001.

104

V4 ,0

V4

25.02

11

Thus,

mA1 ,M1

V2 and mA/V5.0'

2

2

V220min −=−≈−= tGD VVV Ω=−

== kRV DD 10001.

010 thusV,0

To allow for a ±2V signal swing at the drain, Where we have neglected the signal component of VG

39

Prof. Sang-Jo Yoo

Design Philosophy

The circuits that we have just looked at are not suitable for integrated circuit design.

They use too many resistors which take up room and are therefore expensive.

It turns out that since we are making small MOSFETs anyways, that if we can use transistors that act sort of like resistors we can make much smaller (more dense) circuits.

The coupling capacitors also take up way to much room so coupling and bypass capacitors are not used in the design of MOSFET amplifier circuits.

40

Prof. Sang-Jo Yoo

Basic MOSFET Constant Current SourceUse a reference current through one transistor (Generated through Q1) to set the voltage across the gate to source of another transistor (Q2) and hence replicate the reference current through the drain of the second transistor.

Q1 is saturated since VGS = VDS

( )

R

VVII

VVL

WkI

GSDDREFD

tGSnD

−==

−⎟⎠⎞

⎜⎝⎛=

1

2

11 '

2

1

( )

( )( )1

2

2

22 '

2

1

LW

LW

I

I

VVL

WkII

REF

O

tGSnDO

=

−⎟⎠⎞

⎜⎝⎛==

V DD

R

V O

Q1

-

V GS

+

0 0

0

I REF

I D1

Q2

I O

constant current source

V DD

_

V O

+Q

1

-

V GS

+

I REF

I D1

Q2

I O

current mirror

For Q2,

For Q1,

Io=IREF

41

Prof. Sang-Jo Yoo

Effect of VO on IO

In the previous current source description we assumed that the transistor Q2 is operating in saturation

GSVtGS VV −

OI

Or

1Slope =

OV

tGSO VVV −≥

O

AO

O

OO I

Vr

I

VR 2

2 ==∆∆

=REFI

Region of “constant” current operation

Output Resistance of the Current Mirror

42

Prof. Sang-Jo Yoo

5.7 Basic Configurations of Single-Stage IC MOS Amplifiers

I

V DD

vO

vI

I

V DD

vO

vI V SS−

V DD

vO

vI

Common Source Common Gate Common Drain(Source Follower)

43

Prof. Sang-Jo Yoo

Resistive Load Common Source Amplifier

An ideal current source has an infinite resistance, the current does not depend on the voltage at the node to which it is connected, but what happens if we use a resistive load.

On the solid curve the valid operating points (curve intersections) are labeled with a letter and on the dashed curve the letters have a prime

REFI

1DiQ1 in triode

Q1 in saturation

0

IAGS VVv == 11

DDV ODS vv =1

ICGS VVv == 31

Load curve

A

B

1 2 3 4 5V

IBGS VVv == 21

IDGS VVv == 41

CD

A’

D’

Vout

Vin

VVtn 8.0≅

R

V DD

vO

vI

common-source

VVtn 8.0≅

G

S

D

+VR-

VR=VDD-VDS

44

Prof. Sang-Jo Yoo

Resistive Load Common Source Amplifier continued

Transfer characteristic of the common-source amplifier with a resistive load

Since the resistor is not an ideal current source the gain varies with the load resistance

The higher the load resistance the higher the gain but the smaller the allowed input signal swing (an still have the transistor saturated)

DDV

tnV

A’

B’

0 1 2 3 4 5

5

4

3

2

1

0

A

B

C D

D’C’

Vin

Vout

R1>R2

gain is proportional to the slopeGain1>Gain2

triode

saturation

45

Prof. Sang-Jo Yoo

The CMOS Common-Source Amplifier(PMOS current source load)

The magnitude of VA is large or the transistor output resistance ro is large.

vO

vI

V DD

Q3

iI REF

-

V SG

+

Q1

Q2

-

v+

+-

i-v characteristic of the active-load Q2CMOS common-source amplifier circuit

SGV

( )tpSG VV −

REFI2

1Slope

Or=

v

iQ2 in triode

Q2 in saturation

0

REF

AO I

Vr 2

2 =

46

Prof. Sang-Jo Yoo

Graphical construction to determine transfer characteristic

We expect to have a transfer characteristic that has a high gain since output resistance of the load transistor can be made high.

The load curve is like a high value resistor that has been translated upwards

We are most interested in the area of intersection between A and B for amplification

SGDD VV −

( )tpSGDD VVV −−

REFI

1DiQ1 in triode

Q1 in saturation

0

AGS Vv 11 =

DDVODS vv =1OBV

BGS Vv 11 =

Load curve

AB

Q2=Triode or CutoffId<Iref

47

Prof. Sang-Jo Yoo

Transfer Characteristic of the active load common source amplifier

When the input is low the load transistor is in the triode region, as the input voltage is increased the active load becomes saturated.

The gain is relatively high and depends on the output resistanceof the transistor used in the current mirror

48

Prof. Sang-Jo Yoo

Small-signal equivalent circuit of the common-source config.

REF

AnV

AA

REF

AA

n

v

REF

AoREFnm

I

V

L

WkA

VV

IVV

LW

k

A

I

VrI

L

Wkg

1

21

21

1

11

11

'2

1

that assume weIf

111

'2

becomesgain then The

'2

⎟⎠⎞

⎜⎝⎛−≈

≅

+

⎟⎠⎞

⎜⎝⎛

−=

=⎟⎠⎞

⎜⎝⎛=

+-

11 gsm vg1or 2or

-

1vgs

+

iv

-

vo

+D1,D2

S1,S2

( )211 oomi

oV rrg

v

vA −=≡

Since ro1 and ro2 are usually large the gain can be large without taking up a lot of room on the chip with an integrated resistor.

Voltage gains on the order of 20-100 are obtained using CMOS common-source configuration

49

Prof. Sang-Jo Yoo

The CMOS Common-Gate Amplifier

V DD

vO

vBIAS

Q3

iI REF

-

V SG

+

Q1

Q2

-

vI

+

small-signal equivalent circuit

In this case a constant dc level is applied to the gate of the transistor and the input signal is applied to the sourceThe signal source at the gate will be zero (hence the name common gate)There will be a potential difference between the source and the bulk (body) so we need to use the model which includes that effect.

B1+-

11 gsm vg1or

-

1vgs

+

iv

-

vo

+

D1,D2

2or11 bsmb vg

G1

S1 vbs1

-

+

iR Body effect

Vgs1=-vi vbs1=-vi

mmb gg χ=

50

Prof. Sang-Jo Yoo

Simplified circuit

The body effect adds to the gain but reduces the input resistance

The active load (ro2) slightly increases the input resistance

iR

( )

( )

( )( )2111

211

11

211

1

//

//1

oombmv

ooo

mbmi

ov

o

oimbm

o

oi

rrggA

rrr

ggv

vA

r

vvgg

r

vv

+≈

⎟⎟⎠

⎞⎜⎜⎝

⎛++=≡

=++−

+-

( ) imbm vgg 11 +

1or

2oriv

-

vo

+

D1,D2

S1

( ) 1ooi rvv −

ii

( )

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+

+≈≡

−++=

1

2

11

111

11

o

o

mbmi

ii

o

oiimbmi

r

r

ggi

vR

r

vvvggi

output node equation

if 1/ro1<<gm1

Input resistance(input node equation)

51

Prof. Sang-Jo Yoo

The Common-Drain or Source-Follower Configuration

small-signal equivalent circuit(again the body effect is included)

The common-drain or source follower configuration is used as buffer amplifier. Although its voltage gain is less than unity it has a low output resistance.

Typically found in the output stage of a multi-stage amplifier.

The input impedance is very high since it is the gate of a MOSFET.

B1

+-

11 gsm vg1or

-

1vgs

+

iv

-

vo

+

2or

11 bsmb vg

G1

S1 vbs1

-

+

D1

Use the source absorption theorem to transform the dependent source into a resistance 1/gmb1

V DD

V DD

Q3

Q2

V SS−

I REF Q5

vi

vo

common-drainor

source-follower

52

Prof. Sang-Jo Yoo

Simplified circuit

+-

11 gsm vg-

1vgs

+

iv

-

v o

+SR

G1

S1

211

////1

oomb

S rrg

R =

( )

χ

χ

+=

=+

≈

+++=

+=≡

+=

+=+=

==

1

1

,

11

1

1

1111

1

2121

1

1

1

11

11111

111

v

mmbmbm

mv

oombm

mv

Sm

Sm

i

ov

gsSmi

gsSmgssgsi

gsSmso

A

gggg

gA

rrgg

gA

Rg

Rg

v

vA

vRgv

vRgvvvv

vRgvv

typically 0.1<χ<0.3

The body effect reduces the gain by ~10 to 30 percent

0

53

Prof. Sang-Jo Yoo

All NMOS Amplifier Stages

v

i+

-v

i

V t

( ) ttn VvVvL

Wki ≥−= ,'

2

1 2

0

Saturated Enhancement Mode LoadVGS=VDS therefore always saturated

G

D

S

locus of points on many curves

VGS=VDS

2tDD VV −

VGS2=VDS2

DDV

i

0

i+

VDS2

-

DDV

G2

D2

S2 +

VDS1=Vout

-

G1

S1

D1

x

xx

VGS1=Vin

54

Prof. Sang-Jo Yoo

NMOS Amplifier with Enhancement Load

( )( )

( )( )

( )( )( )( ) 22

1

2

1

2

1

2

1

1

1

χ+−=

−=

−⎟⎟⎠

⎞⎜⎜⎝

⎛+−=

LW

LWA

LW

LWA

vLW

LWV

LW

LWVVv

v

v

IttDDO

Q1

12 DD ii =Q

2

-

vI

+-

vO

+

V DD

2tV

1Di

0

...1 =GSv

DDV 1DSv3V

VvGS =1

Load curve

A

B

11 tGS Vv =

1V

I Q1 cutoff

3V

1 V

VIv

A’

B’

0

Ov

IIQ1 in

saturationIII

Q1 intriode region

Due to the body effect

2t DDV V−

DDV

1t V

55

Prof. Sang-Jo Yoo

NMOS Load Devices - Saturated Depletion Mode

Depletion Mode Load, VGS=0 Always on

VGS

IDS

Q2

Di

Q1

-

vI

+

-

vO

+

V DD

+-

11 gsm vg1or 2or

-

1vgs

+

iv-

vo

+D1,G2.S2

D2,B2

G1

S1,B1

22 bsmb vg

( )( ) χ

χ

1

////1

2

1

2

1

2

1

212

1

LW

LWA

g

g

g

gA

rrg

gv

vA

v

m

m

mb

mv

oomb

mI

Ov

−=

−=−≈

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛−=≡

56

Prof. Sang-Jo Yoo

5.8 The CMOS Digital Logic Inverter

For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.

The inverter uses two matched enhancement-type MOSFETS; an n-channel and a p-channel. The body of each device is connected to its source which eliminates any body effect.

CMOS inverter simplified inverter circuit

V DD

vOvI

QP

QN

iDN

iDPvOvI

QP

QN

V DD

57

Prof. Sang-Jo Yoo

Circuit Operation

We assume that the n-channel device is the driver, and the p-channel device is the load.

When the input is high, vO=VOL=0 Volts, and the power dissipation in the inverter is 0.

Operation of the CMOS inverter when vI is high

DDV0≈OLV Ov

i DDOHGSN VVv ==

0

Operatingpoint

Load curve( )0=SGPv

( )⎥⎦

⎤⎢⎣

⎡−⎟

⎠⎞

⎜⎝⎛= tnDD

nnDS VV

LW

kr '1-

DDSGNVv =

+

V DD

vO

QP

QN

i

V DD-

0

=

+

vSGP

V DD

0=vO

rDSN

Page 368

58

Prof. Sang-Jo Yoo

Circuit Operation, cont’d

We assume that the n-channel device is the driver, and the p-channel device is the load.

When the input is low, vO=VDD, and the power dissipation in the inverter is 0.

Operation of the CMOS inverter when vI is low

( )⎥⎥⎦

⎤

⎢⎢⎣

⎡−⎟

⎠⎞

⎜⎝⎛= tpDD

ppDSP VV

LW

kr '1

DDV0≈OLV Ov

i

0== OLGSN Vv

0

Operating point

Load curve

DDOH VV ≈

( )DDGSP Vv =

V DD

-

0

=

+

vSGN

vO

QP

QN

i

-

DDSGPVv =

+

V DD

DLOVv =

rDSP

59

Prof. Sang-Jo Yoo

Circuit Operation, cont’d

The basic CMOS logic inverter behaves as an ideal inverter

The output voltage levels are 0 and VDD, and the signal swing is the maximum possible. This results in wide noise margins.

The static power dissipation in the inverter is 0

A low-resistance path exists between the output terminal and ground (in the low-output state) or VDD (in the high-output state). The low output resistance makes the inverter less sensitive to the effects of noise and other disturbances.

The input resistance of the inverter is infinite (because IG=0). Thus the inverter can drive an arbitrarily large number of similar inverters with no loss in signal level.

60

Prof. Sang-Jo Yoo

The Voltage Transfer CharacteristicFor QN,

( )

( ) tnIOtnIn

nDN

tnIOOOtnIn

nDN

VvvVvL

Wki

VvvvvVvL

Wki

−≥−⎟⎠⎞

⎜⎝⎛=

−≤⎥⎦⎤

⎢⎣⎡ −−⎟

⎠⎞

⎜⎝⎛=

for '2

1

and

for 2

1'

2

2

( )( ) ( )

( ) tpIOtpIDDp

pDP

tpIOODDODDtpIDDp

pDP

VvvVvVL

Wki

VvvvVvVVvVL

Wki

−≤−−⎟⎠⎞

⎜⎝⎛=

+≥⎥⎦⎤

⎢⎣⎡ −−−−−⎟

⎠⎞

⎜⎝⎛=

for '2

1

and

for 2

1'

2

2

For QP,

tptn VV =p

pn

n L

Wk

L

Wk ⎟

⎠⎞

⎜⎝⎛=⎟

⎠⎞

⎜⎝⎛

''

Usually designed

61

Prof. Sang-Jo Yoo

The Voltage Transfer Characteristic, cont’d

62

Prof. Sang-Jo Yoo

The Analog Switch

The MOSFET is often used as a voltage-controlled switch.

The voltage applied to the gate of each QN and QP turns them on and off.In the off position, the MOSFET behaves as an open circuit between drain and source

In the on position, the MOSFET presents a resistance rDS between drain and source

Analog Switch

( )tGSn

DS

VVL

Wk

r−⎟

⎠⎞

⎜⎝⎛

='

1

+-Av

-

vO

+LR

LC

(5.13) for small vDS

More stringent requirements are placed on an analog switch, relative to a digital switch.

When the switch is open, we want it to operate as an open circuit--the off-resistance switch should be very high (ideally infinite off resistance)

A high on-resistance would result in signal attenuation (small on resistance)

The switch should be bidirectional (able to conduct in both directions)

63

Prof. Sang-Jo Yoo

MOSFET Internal Capacitances and High-Frequency Model

The MOSFET has internal capacitances, however, they are neglected in the small-signal model.

The gain of every MOSFET amplifier falls off at some high frequency.

There are basically two types of internal capacitances in the MOSFET:

The gate capacitive effect: the gate electrode (polysilicon) forms a parallel-plate capacitor with the channel, with the oxide layer serving as the capacitor dielectric.

The source-body and drain-body depletion-layer capacitances: these are the capacitances of the reversed-biased pn junctions formed by the n+ source region (source diffusion) and the p-type substrate, and by the n+ drain region (drain diffusion) and the substrate.

There will be five capacitances in total:

Cgs, Cgd, Cgb, Csb, and Cdb, where the substrates indicate the location of the capacitances in the model.

64

Prof. Sang-Jo Yoo

The Gate Capacitive Effect

The gate capacitive effect can be modeled by three capacitances Cgs, Cgd, and Cgb.

In the triode region at small vDS

In saturation

In the cutoff region

Overlap capacitance

oxgdgs WLCCC2

1==

03

2

=

=

gd

oxgs

C

WLCC

oxgb

gdgs

WLCC

CC

=

== 0

oxovov CWLC =

gsmvgor

-

vgs

+

bsmb vg

gdC

gbCsbC

dbC

B

G

S

D

gsC

+

−

vbs

65

Prof. Sang-Jo Yoo

The Junction Capacitances

0

0

1V

V

CC

SB

sbsb

+=

0

0

1V

V

CC

DB

dbdb

+=

For source diffusion, the source-body capacitance, Csb

For drain diffusion, the drain-body capacitance, Cdb

Csb0 is the value of Csb at zero body biasVSB is the magnitude of the reverse-bias voltageV0 is the junction built-in voltage

Cdb0 is the capacitance value at zero reverse-bias voltageVDB is the magnitude of the reverse-bias voltageV0 is the junction built-in voltage

The above formulas assume small-signal operation.

66

Prof. Sang-Jo Yoo

The High-Frequency MOSFET Model

gsmvgor

-

vgs

+

gdC

dbC

G

S

D

gsC

gsmvgor

-

vgs

+

bsmbvg

gdC

gbCsbC

dbC

B

G

S

D

gsC

+

−

vbs

gsmvgor

-

vgs

+

gdCG

S

D

gsC

67

Prof. Sang-Jo Yoo

Unity-Gain Frequency (fT)

The unity-gain frequency (fT) is defined as the frequency at which the short-circuit current-gain of the common-source configuration becomes unity.

gsmvgor

-

vgs

+

gdC

gsC

oI

iI

gsmo

gsgdgsmo

VgI

VsCVgI

≅

−=

( )gdgs

igs CCs

IV

+=

( )gdgs

m

i

o

CCs

g

I

I

+=

( )gdgs

mT CC

g

+=ω

Π=

2T

Tfω

( )gdgs

mT CC

gf

+Π=

2

The magnitude of the current gain becomes unity at thefrequency