Chapter 4.1 - Integer...
Transcript of Chapter 4.1 - Integer...
Chapter 4.1 - Integers 1
Integer RepresentationIntroduction to Digital LogicInteger Arithmetic & Adder
Chapter 4.1 - Integers 2
Representing Numbers: Review• 32-bit binary representation of (unsigned) number:
– b31 × 231+ b30 × 230 + ⋅⋅⋅ + b2 × 22 + b1 × 21 + b0 × 20
– One billion (1,000,000,00010 ) in binary is
0011 1011 1001 1010 1100 1010 0000 00002
228 224 220 216 212 28 24 20
= 1×229 + 1×228 + 1×227 + 1×225 + 1×224 + 1×223 + 1×220 + 1×219 + 1×217 + 1×215
+ 1×214 + 1×211 + 1x29
= 536,870,912 + 268,435,456 + 134,217,728 + 33,554,432 + 16,777,216 +
8,388,608 + 1,048,576 + 524,288 + 131,072 + 32,768 + 16,384 + 2,048 +
512 = 1,000,000,000
Chapter 4.1 - Integers 3
What If Too Big?
• Binary bit patterns are simply representations of numbers.
• Numbers really have an infinite number of digits (non-significant zeroes to the left).
– with almost all being zero except for a few of the rightmost digits.– Don’t normally show leading zeros.
• If result of add (or any other arithmetic operation) cannot be represented by these rightmost hardware bits, overflow is said to have occurred.
• Up to Compiler and OS what to do.
Chapter 4.1 - Integers 4
How to Avoid Overflow? Allow It Sometimes?
• Some languages detect overflow (Ada, Fortran), some don’t (C)
• MIPS solution is 2 kinds of arithmetic instructions to recognize 2 choices:
– add (add), add immediate (addi), and subtract (sub) cause exceptions on overflow
– add unsigned (addu), add immediate unsigned (addiu), and subtract unsigned (subu) do not cause exceptions on overflow
• unsigned integers commonly used for address arithmetic where overflow ignored
• MIPS C compilers always produce addu, addiu, subu
Chapter 4.1 - Integers 5
What If Overflow Detected?• If "exception" (or "interrupt") occurs
– Address of the instruction that overflowed is saved in a register– Computer jumps to predefined address to invoke appropriate
routine for that exception– Like an unplanned hardware function call
• Operating System decides what to do– In some situations program continues after corrective code is
executed
• MIPS hardware support: exception program counter (EPC) contains address of overflowing instruction --- (more in Chpt. 5)
Chapter 4.1 - Integers 6
Representing Negative NumbersTwo’s Complement
• What is result for unsigned numbers if subtract larger number from a smaller one?– Would try to borrow from string of leading 0s,
so result would have a string of leading 1s– With no obvious better alternative, pick representation that made
the hardware simple:• leading 0s ⇒ positive, • leading 1s ⇒ negative
000000...xxx ≥ 0
111111...xxx < 0
• This representation is called two’s complement
Chapter 4.1 - Integers 7
Two’s Complement (32-bit)0111 ... 1111 1111 1111 1111two = 2,147,483,647ten
0111 ... 1111 1111 1111 1110two = 2,147,483,646ten
0111 ... 1111 1111 1111 1101two = 2,147,483,645ten
. . .
0000 ... 0000 0000 0000 0010two = 2ten
0000 ... 0000 0000 0000 0001two = 1ten
0000 ... 0000 0000 0000 0000two = 0ten
1111 ... 1111 1111 1111 1111two = -1ten
1111 ... 1111 1111 1111 1110two = -2ten
1111 ... 1111 1111 1111 1101two = -3ten
. . .
1000 ... 0000 0000 0000 0001two = -2,147,483,647ten
1000 ... 0000 0000 0000 0000two = -2,147,483,648ten
Indicates sign of the integer
Chapter 4.1 - Integers 8
Two’s Complement Formula, Example• Recognizing role of sign bit, can represent positive and negative
numbers in terms of the bit value times a power of 2:
– d31 × -231 + d30 × 230 + ··· + d2 × 22 + d1 × 21 + d0 × 20
• Example (given 32-bit two’s comp. number)
1111 1111 1111 1111 1111 1111 1111 11002
= 1 × -231 + 1 × 230 + 1 × 229 + ··· + 1 × 22 + 0 × 21 + 0 × 20
= -231 + 230 + 229 + ··· + 22 + 0 + 0
= -2,147,483,64810 + 2,147,483,64410
= -410
Chapter 4.1 - Integers 9
Ways to Represent Signed Numbers(1) Sign and magnitude
– separate sign bit
(2) Two’s (2’s) Complement (n bit positions)
– n-bit pattern dn-1 ... d2d1d0 means:
-1 × dn-1 × 2n-1 + ⋅⋅⋅ + d2 × 22 + d1 × 21 + d0 × 20
– also, unsigned sum of n-bit number and its negation = 2n
0001 positive one +
+ 1111 negative one (2’s comp)
10000 = 24 (=zero if only 4 bits)
0001001100101 1
Chapter 4.1 - Integers 10
Ways to Represent Signed Numbers(3) One’s (1’s) Complement
– unsigned sum of n-bit number and its negation = 2n - 1
0001 positive one
+1110 negative one (1’s comp)
1111 (24 - 1)
– better than sign and magnitude but has two zeros (+0=0000 and -0=1111)
– some scientific computers use 1’s comp.
(4) Biased notation
– add positive bias B to signed number, store as unsigned; useful in floating point (for the exponent).
– number = x - B
Chapter 4.1 - Integers 11
Bias= 8(Subtract 8)
1111111011011100101110101001100001110110010101000011001000010000
-1-2-3-4-5-6-7-876543210
0-1-2-3-4-5-6-776543210
76543210
-1-2-3-4-5-6-7-8
1514131211109876543210
b3b2b1b0
Bit-Pattern, Unsigned, 2’s Comp, 1’s Comp, Biased
Chapter 4.1 - Integers 12
Signed Vs. Unsigned Comparisons• Note: memory addresses naturally start at 0 and continue to the
largest address – they are unsigned.– That is, negative addresses make no sense.
• C makes distinction in declaration.– integer (int) can be positive or negative.– unsigned integers (unsigned int) only positive.
• Thus MIPS needs two styles of comparison.– Set on less than (slt) and set on less than immediate (slti)
work with signed integers.– Set on less than unsigned (sltu) and set on less than immediate
unsigned (sltiu). (Will work with addresses).
Chapter 4.1 - Integers 13
Signed Vs. Unsigned Comparisons
$s0 has1111 1111 1111 1111 1111 1111 1111 11002
$s1 has0011 1011 1001 1010 1000 1010 0000 00002
• What are $t0, $t1 after:slt $t0, $s0, $s1 # signed compare
sltu $t1, $s0, $s1 # unsigned compare
•$t0: -4ten < 1,000,000,000ten?
•$t1: 4,294,967,292ten < 1,000,000,000ten?
Key Point: Instructions decide what binary bit-patterns mean
Chapter 4.1 - Integers 14
Two’s Complement Shortcut: Negation• Invert every 0 to 1 and every 1 to 0, then add 1 to the result
– Unsigned sum of number and its inverted representation must be 111...1112
– 111...1112= -110
– Let x´ mean the inverted representation of x
– Then x + x´ = -1 ⇒ x + x´ + 1 = 0 ⇒ x´ + 1 = -x
• Example: -4 to +4 to -4
• x : 1111 1111 1111 1111 1111 1111 1111 11002
x´ : 0000 0000 0000 0000 0000 0000 0000 00112
+1: 0000 0000 0000 0000 0000 0000 0000 01002
( )x´: 1111 1111 1111 1111 1111 1111 1111 10112
+1: 1111 1111 1111 1111 1111 1111 1111 11002
IMPORTANT SLIDE
Chapter 4.1 - Integers 15
Two’s Complement ShortcutUsing Sign extension
• Convert number represented in k bits to more than k bits– e.g., 16-bit immediate field converted to 32 bits before adding to 32-bit
register in addi
• Simply replicate the most significant bit (sign bit) of smaller quantity to fill new bits
– 2's comp. positive number has infinite 0s to left– 2's comp. negative number has infinite 1s to left– Finite representation hides most leading bits; sign extension restores
those that fit in the integer variable– 16-bit -410 to 32-bit:
1111 1111 1111 11002
1111 1111 1111 1111 1111 1111 1111 11002
Chapter 4.1 - Integers 16
Do It Yourself• Convert the two’s complement number
1111 1111 1111 1111 1111 1010two
into decimal (base ten):
Chapter 4.1 - Integers 17
Do It Yourself
• Convert the two’s complement number
1111 1111 1111 1111 1111 1111 1111 10102
into decimal (base ten):• Could use conversion formula (hard)
1 x -231 + 1 x 230 + … 1 x 21 + 1 x 20
• Or, first use negation shortcut (easy)0000 0000 0000 0000 0000 0000 0000 0101
10000 0000 0000 0000 0000 0000 0000 0110
= 6 (therefore, answer: -6)
+
Chapter 4.1 - Integers 18
1-bit Binary Addition• two 1-bit values gives four cases:
0 0 1 10 1 0 1
0 1 1 (1) 0
• digital logic?: half-adder circuit
+ + + +
carry-out 1-bit sum
HAab
sumcarry-out
Chapter 4.1 - Integers 19
Multi-bit Addition (and Subtraction)– 00 0111 = 710 +
00 0110 = 610
00 1101 = 1310
–
(0) (0) (1) (1) (0) 00 0 0 1 1 1
+ 0 0 0 1 1 0
(0) 0 (0)0 (0)1 (1)1 (1)0 (0)1
Subtract? Simply negate and add!
(carries)
HAab
sumcarry-out
carry-in
HAab
sumcarry-out
carry-in
carry-inab
Chapter 4.1 - Integers 20
Detecting Overflow in 2’s Complement?• Adding 2 31-bit positive 2’s complement numbers
can yield a result that needs 32 bits
– sign bit set with value of result (1) instead of proper sign of result (0)
– since need just 1 extra bit, only sign bit can be wrong
Op A B Result
A + B >=0 >=0 <0A + B <0 <0 >=0A - B >=0 <0 <0A - B <0 >=0 >=0
° Adding operands with different signs, (subtracting with same signs) overflow cannot occur
Chapter 4.1 - Integers 21
Overflow for Unsigned Numbers?
• Adding 2 32-bit unsigned integers could yield a result that needs 33 bits
– can't detect from "sign" of result
• Unsigned integers are commonly used for address arithmetic, where overflows are ignored
• Hence, MIPS has unsigned arithmetic instructions, which ignore overflow:
– addu, addiu, subu
– Recall that in C, all overflows are ignored, so unsigned
instructions are always used (different for Fortran, Ada)
Chapter 4.1 - Integers 22
Do It Yourself
• Add 4-bit signed (2’s complement) numbers:
1111 -110+ 1110 -210
• Did overflow occur?
Chapter 4.1 - Integers 23
Do It Yourself• Add 4-bit signed (2’s comp.) numbers :
1111 -110.+ 1110 -21011101.
• Did overflow occur?– overflow in 2’s complement only if.
Negative + Negative → "Positive."Positive + Positive → "Negative."
– overflow = carry-out only if numbers considered to be unsigned.
• So: addition works same way for both unsigned, signed numbers.
• But overflow detection is different.
Chapter 4.1 - Integers 24
Logical Operations
• Operations on less than full words– Fields of bits or individual bits
• Think of word as 32 bits vs. 2’s comp. integers or unsigned integers
• Need to extract bits from a word, insert bits into a word
• Extracting via Shift instructions– C operators: << (shift left), >> (shift right)
• Inserting via And/Or instructions– C operators: & (bitwise AND), | (bitwise OR)
Chapter 4.1 - Integers 25
Shift Instructions• Move all the bits in a word to the left or right, filling the emptied bits
with 0’s
• Before and after shift left 8 of $s0 ($16):
0000 0000 0000 0000 0000 0000 0000 1101two
0000 0000 0000 0000 0000 1101 0000 0000two
• MIPS instructions– shift left logical (sll) and shift right logical (srl)–sll $s0, $s0, 8 # $s0 = $s0 << 8 bits– R Format, using shamt (shift amount)!
0 0 16 16 08op rs rt rd functshamt
Chapter 4.1 - Integers 26
Extracting a Field of Bits° Extract bit field from bit 9 (left bit) to bit 2 (size = 8 bits) of
register $s1, place in rightmost part of register $s0
012345678931
0000 00000000000000000000
$s1
$s0
• Shift field as far left as possible (31-bit no.) and then as far right as possible (32-size)
$s1
$s0
$s0
00 000000000000000000000000 00000000000000000000
sll $s0, $s1, 22 # 8bits to left end (31-9)srl $s0, $s0, 24 # 8bits to right end(32-8)
Chapter 4.1 - Integers 27
And Instruction
• AND: bit-by-bit operation leaves a 1 in the result only if both bits of the operands are 1. For example, if registers $t1 and $t2
– 0000 0000 0000 0000 0000 1101 0000 00002
– 0000 0000 0000 0000 0011 1100 0000 00002
• After executing MIPS instruction–and $t0, $t1, $t2 # $t0 = $t1 & $t2
• Value of register $t0– 0000 0000 0000 0000 0000 1100 0000 00002
• AND can force 0s where 0 in the bit pattern– Called a “mask” since mask “hides” bits
Chapter 4.1 - Integers 28
Or Instruction
• OR: bit-by-bit operation leaves a 1 in the result if either bit of the operands is 1. For example, if registers $t1 and $t2
– 0000 0000 0000 0000 0000 1101 0000 00002
– 0000 0000 0000 0000 0011 1100 0000 00002
• After executing MIPS instruction– or $t0, $t1, $t2 # $t0 = $t1 | $t2
• Value of register $t0
– 0000 0000 0000 0000 0011 1101 0000 00002
• OR can force 1s where 1 in the bit pattern
– If 0s in field of 1 operand, can insert new value
Chapter 4.1 - Integers 29
Inserting a Field of Bits (Almost OK;-)° Insert bit field into bits 9⎯2 (leftmost bit is 9; size = 8 bits) of
register $s1 from rightmost part of register $s0 (rest is 0)
0123456789310000 00000000000000000000
$s1
$s0
• 1. Mask out field; 2. shift left field 2; 3. OR in field
000000000000 00 000000000000000000
1. $s1
2. $t0
3. $s1
andi $s1, $s1, 0xfc03 # mask out $s1[2..9] = 0 sll $t0, $s0, 2 # field left 2 $t0[2..9]or $s1, $s1, $t0 # OR in field $s1 OR $t0
Chapter 4.1 - Integers 30
Sign Extension of Immediates•addi and slti: deal with signed numbers, so immediates are
sign extended
• Branch and data transfer address fields are sign extended too
•andi and ori work with unsigned integers, so immediates padded with leading 0s
–andi won’t work as a mask in upper 16 bits
– Use register version instead
addiu $t1, $zero, 0xfc03 # 32b mask in $t1 and $s1, $s1, $t1 # mask out 9-2sll $t0, $s0, 2 # field left 2or $s1, $s1, $t0 # OR in field
Chapter 4.1 - Integers 31
The 5 Components of Any Computer
Personal Computer
Processor (CPU)
Computer
Control("brain")
Datapath("brawn")
Memory Devices
Input
Output
We WillStart Here:
Arithmetic-Logic Unit(ALU)
Chapter 4.1 - Integers 32
Overview: Digital Logic Design
• Topics we assume you know: – Combinational and Sequential Logic Blocks– Boolean Algebra/Logic Equations– Truth Tables– Logic Gates
• Appendix B gives review – need B.1 - B.3 for Chapter 4– will need B.4 - B.6 for Chapter 5-7
Chapter 4.1 - Integers 33
Combinational, Sequential Logic
• Two kinds of Logic Blocks (Circuits)– Combinational Logic Block
• described by a logic equation or truth tableX = AB + CD
• no memory: output of block depends only on the current inputs; no feedback loops
– Sequential Logic Block• described by a finite state machine• contains memory (local state); output depends on current
inputs and stored value; permits feedback loops– Will use combinational logic blocks first for the datapath, then
sequential logic for the control unit (Chapter 5)
Chapter 4.1 - Integers 34
Implementing Logic Blocks• Logic Gates : primitives
AND OR NOT (inverter)
• Combine gates to implement more complex Boolean function:W = X + (YZ)
• Some shorthand:
XW
YZ
NOR=
= NAND
Chapter 4.1 - Integers 35
MIPS arithmetic instruction format31 25 20 15 5 0
R-type:op Rs Rt Rd funct
I-Type: op Rs Rt Immed 16
Type op funct
ADDI 10 xx
ADDIU 11 xx
SLTI 12 xx
SLTIU 13 xx
ANDI 14 xx
ORI 15 xx
XORI 16 xx
LUI 17 xx
Type op funct
ADD 00 40
ADDU 00 41
SUB 00 42
SUBU 00 43
AND 00 44
OR 00 45
XOR 00 46
NOR 00 47
Type op funct
00 50
00 51
SLT 00 52
SLTU 00 53
Chapter 4.1 - Integers 36
Refined Requirements(1) Functional Specificationinputs: 2 x 32-bit operands A, B, 4-bit modeoutputs: 32-bit result S, 1-bit carry, 1 bit overflowoperations: add, addu, sub, subu, and, or, xor, nor, slt, sltU
(2) Block Diagram (powerview symbol, VHDL entity)
ALUALUA B
movf
S
32 32
32
4c
Chapter 4.1 - Integers 37
Gates, Truth Tables and Logic Equations
• Digital Electronics: Circuits that operate with only two voltages of interest.
• "High" and "Low" voltage, corresponding to logic values. Other values occur only during transitions.
• Example.– "High" ∈ [ 5.0V, 3.5V ]; "Low" ∈ [ 0.0V, 1.5V ];
• Associate Logic 1 with High and Logic 0 with Low.• We will talk about logic signal values, instead of voltage levels.
– Signal "asserted" ↔ 1; "de-asserted" ↔ 0.
Chapter 4.1 - Integers 38
Combinational Circuits & Truth Tables• Combinational logic blocks have no memory and can be fully described by truth
tables.
• Each function with n inputs → 2n entries.• Let Z = G (A, B, C ).• A Truth Table describes the behaviour of G.
A B C Z D E F.0 0 0 z000 0 0 0.0 0 1 z001 1 0 0.0 1 0 z010 1 0 0.0 1 1 z011 1 1 0.1 0 0 z100 1 0 0.1 0 1 z101 1 1 0.1 1 0 z110 1 1 0.1 1 1 z111 1 0 1.
Chapter 4.1 - Integers 39
Hardware Building Blocks
AND Gate
CAB
SymbolA B C0 0 00 1 01 0 01 1 1
DefinitionOR Gate
AB C A B C
0 0 00 1 11 0 11 1 1
DefinitionSymbol
CASymbol
Inverter
A C0 11 0
Definition
C
SymbolMultiplexor
S C0 A1 B
Definition
A
B
0
1
S
Chapter 4.1 - Integers 40
Multiplexors
• AND, OR, Inverter (NOT) are the logic primitives (smallest logic elements)
• Multiplexors, e.g., Selector, Mux, can be constructed from primitives:
A
B
S
C
C
Symbol Definition
A
B
0
1
S
C = SB + S'A
Mux
S C0 A1 B
Chapter 4.1 - Integers 41
Multiplexors
• Larger muxes: need multiple "select" inputs: interpret as binary number
– Can implement directly with gates, or – use decoder (see B.3) to enable a single input, or– combine several 2-input muxes
C
AB
01
D
Mux2
3
S1S2
E
S1 S2 E0 0 A0 1 B1 0 C1 1 D
Appendix B.3 for more details
Chapter 4.1 - Integers 42
Arithmetic Logic Unit (ALU)
• MIPS ALU is 32 bits wide
• Start with 1-bit ALU, then connect 32 1-bit ALUs to form a 32-bit ALU in a "bit slice" manner
• Since hardware building blocks include an AND gate and an OR gate, and since AND and OR are two of the operations of the ALU, start here:
Op C0 A and B1 A or B
DefinitionAB C
0
1
Op